JP3128077B2 - Method for manufacturing bipolar transistor and method for manufacturing semiconductor device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a manufacturing method and a manufacturing method of a semiconductor device using the bipolar transistor, the method and it particularly bipolar transistors bipolar transistors are formed on the light-transmissive on the substrate prepared The present invention relates to a method for manufacturing a semiconductor device used.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and involves a number of things that cannot be achieved with a bulk Si substrate for fabricating a normal Si integrated circuit. Much research has been done on the advantages of devices utilizing SOI technology. In other words, by using SOI technology,
. Dielectric separation is easy and high integration is possible. Excellent radiation resistance. The stray capacitance is reduced and the speed can be increased. Well steps can be omitted. Latch-up can be prevented. Advantages such as the possibility of a fully depleted field-effect transistor by thinning can be obtained.

[0003] In order to realize many of the above advantages in device characteristics, researches have been made on a method of forming an SOI structure for several decades. This content can be found, for example, in Special Issue: "Single-crystal silicon on n
on-single-crystal insulators "; edited by GWCulle
n, Journal of Crystal Growth, volume 63, no3, pp 4
29-590 (1983).

In the past, SOS (silicon on sapphire), which is formed by heteroepitaxy of Si on a single crystal sapphire substrate by CVD (chemical vapor deposition), is known, and is the most matured. Despite the success of SOI technology, a large amount of crystal defects due to the lattice mismatch between the Si layer and the underlying sapphire substrate, the incorporation of aluminum from the sapphire substrate into the Si layer, and above all, the high cost of the substrate The delay in increasing the area has hindered the spread of its applications. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two. (1) After oxidizing the surface of the Si single crystal substrate, open a window to open the Si
The substrate is partially exposed, and the portion is epitaxially grown in the lateral direction using the seed as a seed to form a Si single crystal layer on SiO ₂ (in this case, a Si layer is deposited on SiO ₂ ). (2) using the Si single crystal substrate itself as an active layer,
SiO ₂ is formed thereunder (this method does not involve the deposition of a Si layer).

Various semiconductor devices and integrated circuits comprising them have been fabricated on a silicon layer on an insulator formed by these methods.

[0006]

As means for achieving the above (1), a single crystal layer Si is directly formed by a CVD method.
A method in which amorphous silicon is deposited and a solid-phase lateral epitaxial growth is performed by heat treatment, an electron beam is applied to an amorphous or polycrystalline Si layer.
A method of converging and irradiating an energy beam such as a laser beam to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape by a rod heater (Zone melting recrystallization) are known. ing. Each of these methods has advantages and disadvantages,
There remain many problems in controllability, productivity, uniformity, and quality, and none has been industrially used yet. For example, the CVD method requires sacrificial oxidation to make a thin film flat, and the solid phase growth method has poor crystallinity. Further, the beam annealing method has a problem in controllability such as processing time by convergent beam scanning, beam overlap, focus adjustment, and the like. Of these, the Zone Melting Recrystallization method is the most mature, and although relatively large-scale integrated circuits have been prototyped, crystal defects such as sub-grain boundaries still remain.
There are many remaining, and there is no way to make a minority carrier device. In addition, any of these methods requires a Si substrate, so that a high-quality Si single crystal layer cannot be obtained on a transparent amorphous insulator substrate such as glass.

In the method (2) in which the Si substrate is not used as a seed for epitaxial growth, there are the following three methods.

[0008] An oxide film is formed on a Si single crystal substrate having a V-shaped groove anisotropically etched on its surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is to form a dielectrically separated Si single crystal region surrounded by V-grooves on a thick polycrystalline Si layer. In this method, the crystallinity is good, but polycrystalline Si is deposited several hundred microns thick.
Since a step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer is required, there is a problem in terms of controllability and productivity.

[0009] Simox (SIMOX: Seperati
This is a method called “on by ion implanted oxygen” in which a SiO ₂ layer is formed by ion implantation of oxygen into a Si single crystal substrate, and is the most mature method at present because of its good compatibility with the Si process. However, in order to form a SiO ₂ layer, oxygen ions must be supplied at 10 ¹⁸ ions / cm ^2.
It is necessary to perform the above implantation, the implantation time is long, the productivity is not high, and the wafer cost is high. Furthermore, many crystal defects remain, and from an industrial point of view, the quality has not reached a level sufficient to produce a minority carrier device.

[0010] This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method uses P
Ion implantation of N-type Si layer on the surface of single-crystal Si single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, an island is formed by epitaxial growth and patterning, and only the P-type Si substrate is made porous by anodizing in an HF solution so as to surround the Si island from the surface. This is a method for dielectric isolation. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited.

The formation of a semiconductor element on a light-transmitting substrate is important in forming a contact sensor as a light receiving element and a projection type liquid crystal image display device. Furthermore, pixels (picture elements) of sensors and display devices
In order to further increase the density, resolution and definition, a high-performance driving element is required. Further, the number of terminals of a switching element for switching pixels and the number of terminals of a driving circuit and peripheral circuits thereof are enormous, and the two are separately formed, and the mutual connection thereafter has a density that cannot be obtained by mechanical connection anymore. As a result, it is desirable that the semiconductor element and the peripheral drive circuit be manufactured by performing the same process on the same substrate and the connection between them is performed in a normal integrated circuit. In this case, high-density mounting can be realized only by patterning a conductive thin film. Further, due to the inevitable industrial demand for higher performance of a product to be produced, it is necessary to produce a device provided on a light-transmitting substrate by using a single crystal layer having excellent crystallinity.

However, on a light-transmitting substrate typified by glass, generally, only an amorphous or good polycrystalline layer is formed, reflecting the disorder of the crystal structure, and defects of the defect are formed. Due to the large number of crystal structures, it has been difficult to produce a drive element having required or sufficient performance in the future. This is due to the fact that the crystal structure of the substrate is amorphous, and a high quality single crystal layer cannot be obtained simply by depositing a Si layer. Any of the above-described methods using a Si single crystal substrate is not suitable for the purpose of obtaining a good quality single crystal layer on a light transmitting substrate.

The present invention provides a bipolar transistor, which is a basic unit of an integrated circuit that can be formed on a high-quality single-crystal semiconductor layer on a light-transmitting insulator substrate and can meet the above-mentioned problems and the above-mentioned requirements. And an integrated circuit comprising the same.

Another object of the present invention is to provide a semiconductor integrated circuit which realizes the advantages of the conventional SOI device.

The present invention also provides a semiconductor device and an integrated semiconductor device on an insulator-on-semiconductor substrate that can be replaced with expensive SOS or SIMOX, and that can be used for manufacturing a large-scale integrated circuit having an SOI structure. It is intended to provide a circuit.

[0016]

According to a method of manufacturing a bipolar transistor of the present invention, at least a single crystal layer constituting an active region of the bipolar transistor is formed by the following steps.
Bipolar formed by steps including (a) and (b)
This is a method for manufacturing a transistor. (A) a member having a porous monocrystalline semiconductor layer and a nonporous single crystal semiconductor layer, and a light transmissive substrate having optical transparency at least in the visible light region, wherein said non-porous single-crystal semiconductor layer is an inner and removing the porous monocrystalline semiconductor layer from allowed <br/> Awa bonded to the multilayer structure is obtained that the step (b) the multilayer structure located on said single crystal on the light-transmissive on the substrate Layer
Step of forming the non-porous single crystal layer Also, the method of manufacturing a bipolar transistor of the present invention, the bipolar transistor, at least a single crystal layer constituting the active region,
It is formed by a step including the following steps (a) and (b)
This is a method for manufacturing a bipolar transistor. (A) a member having a porous monocrystalline semiconductor layer and a nonporous single crystal semiconductor layer, and a light transmissive substrate having optical transparency at least in the visible light region through the insulating layer, said non-porous single crystal semiconductor layer and removing the porous monocrystalline semiconductor layer from step (b) the multilayer structure Ru bonded to the multilayer structure is obtained which is located inside the insulating layer on the light transmitting on a substrate Through
Forming the non-porous single-crystal layer to be the single-crystal layer;
About

Further, a semiconductor device according to the present invention is characterized in that the bipolar transistor is used.

Here, the light-transmitting substrate includes a substrate provided with a metal electrode, a transparent electrode and the like on the substrate.

[0019]

[Operation] Although the density of porous silicon is less than half that of single crystal Si, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on top of a porous layer. It is possible. In addition, since the porous layer has a large amount of voids formed therein, the density is reduced to less than half. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the ordinary etching rate of the single crystal layer.

According to the present invention, utilizing such properties of porous silicon, a single crystal semiconductor layer is formed on a substrate having a light transmitting property at least in a visible light region (hereinafter referred to as a light transmitting substrate). A bipolar transistor is manufactured using this single crystal semiconductor layer. That is, the present invention forms a non-porous single crystal layer having excellent crystallinity on a porous silicon substrate, and forms a surface of the non-porous single crystal layer or an oxidized surface of the non-porous single crystal layer. After bonding to a light-transmitting substrate, the porous silicon substrate having an increased etching rate compared to a normal single-crystal layer is removed by at least a step including wet chemical etching to obtain a light-transmitting substrate. A single crystal semiconductor layer is formed over a base, and a bipolar transistor and a semiconductor device using the same are formed using the single crystal semiconductor layer.

In the present invention, an Si single crystal layer formed on a light-transmitting substrate, which is excellent in economical efficiency, is uniform and flat over a large area, has extremely excellent crystallinity, and has extremely few defects. Since the element is created, a bipolar transistor with reduced capacitance between the substrate and the collector can be manufactured,
It is possible to provide a semiconductor device which can operate at high speed and has excellent radiation resistance without soft errors due to α rays.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic sectional view of one embodiment of a semiconductor device according to the present invention. In FIG. 1, a substrate 1 is a light-transmitting substrate made of SiO ₂ formed by selectively removing porous Si as described later.

An NPN-type bipolar transistor 2 and a PNP-type bipolar transistor 3 are formed on the base 1, and a desired semiconductor device is manufactured by appropriately combining both elements. Although the bipolar transistor in FIG. 1 is a planar type, the bipolar transistor of the present invention may have a shape other than the planar type, such as a lateral type.

Hereinafter, the steps of manufacturing the transistors 2 and 3 will be described with reference to FIGS. 2 and 4 from the step of manufacturing a single crystal semiconductor layer on a light-transmitting substrate.

FIGS. 2A to 2C are process diagrams for explaining a method of manufacturing a semiconductor substrate according to the present invention, which are shown as schematic cross-sectional views in each process. FIG.
(A), (b) is a typical sectional view which shows the manufacturing process of the NPN-type bipolar transistor 2 and the PNP-type bipolar transistor 3 shown in FIG. In FIG. 2,
The porous Si single crystal substrate 21 and the thin film single crystal layer 22 are porous
Portion having single crystal semiconductor layer and non-porous single crystal semiconductor layer
The material (FIG. 2A), the light-transmitting substrate 23 is a light-transmitting substrate,
The oxide layer 25 is an insulating layer, a porous Si single crystal substrate 21, a thin film
The single crystal layer 22, the oxide layer 25, and the light-transmitting substrate 23 have a multilayer structure.
The structure (FIG. 2B) is obtained.

As shown in FIG. 2A, first, a Si single crystal substrate is prepared and made porous to form a porous Si single crystal substrate 21. The Si substrate is made porous by an anodizing method using an HF solution. The porous Si layer, as compared with the density of 2.33 g / cm ³ of single crystal Si, by changing the density of HF solution concentration to 50 to 20%, a density 1.1~0.6g / cm It can be changed in the range of ³ . This porous layer is, for the following reasons,
It is easily formed on a P-type Si substrate. This porous Si layer
According to observation with a transmission electron microscope, holes having an average diameter of about 600 angstroms are formed.

The porous Si was prepared by Uhlir et al.
Was discovered during the research process of electropolishing of semiconductors (A.
Uhlir, Bell Syst. Tech. J., vol 35, p.333 (1956)). In addition, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol. 127, p. 476 (198
0)).

[0029] Si + 2HF + (2-n ) e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4 _{^{-λ) e + → SiF 4 +}} 4H + + λe - where _{SiF 4 + 2HF → H 2 SiF} 6, e + and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the number of holes required for dissolving one atom of silicon, respectively, and it is assumed that porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is easily made porous. The selectivity in this porosity has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Onaka, Kajiwara; IEICE Technical Report, vol 79, SSD 79-9549 (1979), (K. Imai; Solid-Sta
te Electronics vol 24,159 (1981)). Thus, P-type silicon having holes is easily made porous, and P-type silicon can be selectively made porous.

On the other hand, reports that high-concentration N-type silicon is also made porous (RP Holmstrom, IJYChi Appl. Phys.
tt. Vol. 42, 386 (1983)), and it is important to select a substrate that can realize porosity regardless of P-type or N-type.

Further, the density of the porous layer is reduced to less than half since a large amount of voids are formed therein. As a result, the surface area increases dramatically compared to the volume,
The chemical etching rate is significantly increased compared to the etching rate of a normal single crystal layer.

A method for epitaxially growing a single crystal after making all of the Si substrate porous will be described.

Epitaxial growth is performed on the porous substrate surface by various growth methods to form a thin film single crystal layer 22.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Regardless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on the porous layer. However, 1000 ° C
Above, rearrangement of the internal holes occurs, and the characteristics of the accelerated etching are impaired. For this reason, the Si layer is epitaxially grown by the molecular beam epitaxial growth method or the plasma C method.
Low-temperature growth such as a VD method, a thermal CVD method, a photo CVD method, a bias sputtering method, and a liquid phase growth method is preferable.

As shown in FIG. 2B, a light-transmitting substrate 23 typified by glass is prepared, and if necessary, the surface of the single-crystal Si layer on the porous Si substrate is oxidized. The light-transmitting substrate 23 is attached to the layer 25. The oxide layer plays an important role in making a device. That is,
The interface level generated by the underlying interface of the Si active layer can be lower at the oxide film interface according to the present invention than at the glass interface, and the characteristics of the electronic device are significantly improved.

As shown in FIG. 2B, an Si ₃ N ₄ layer 24 was deposited as an etching prevention film and bonded together.
The entire substrate is coated to remove the Si ₃ N ₄ layer on the surface of the porous silicon substrate. Apiezon wax or the like may be used instead of the Si ₃ N ₄ layer as another etching prevention film. Thereafter, the entirety of the porous Si substrate 21 is removed by means such as etching and the like, and the thinned single-crystal silicon layer 22 is formed on the light transmitting substrate 23 so as to remain.

FIG. 2C shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 24 as an etching prevention film in FIG. 2B, the single crystal Si layer 22 having a crystallinity equivalent to that of a silicon wafer is flattened on the light transmitting substrate 23. Moreover, the layer is uniformly thinned and formed over a large area over the entire wafer. The semiconductor substrate thus obtained can be suitably used from the viewpoint of producing an insulated electronic element.

Next, the single crystal thin layer on the surface of the light-transmitting substrate thus manufactured is separated by a partial oxidation method or an island-like etching as shown in FIG. Next, NPN
An N-type impurity ion is formed on a single crystal silicon island (4 in FIG. 1) for forming a transistor (2 in FIG. 1), and a single crystal silicon island (5 in FIG. 1) for forming a PNP transistor (3 in FIG. 1). ) Are independently implanted with P-type impurity ions to form collector regions.

Next, as shown in FIG. 4A, an oxide film 8 is formed on the surface by dry oxidation or wet oxidation by pyrogenesis. Subsequently, the oxide film is partially removed using photolithography or the like, and an ion implantation method, a thermal diffusion method, or the like is used for a part of the collector region 6.
The base region 7 is formed by diffusing impurities different from those of the collector region. Next, ions are implanted into the emitter region 9 and the collector contact region 10 by using a photoresist by using the formed mask pattern, so that an impurity having the same type as that of the collector region is doped at a high concentration.

Next, as shown in FIG. 4B, an interlayer insulating layer 11 is deposited by using a CVD method, a bias sputtering method or the like. Further, after contact holes are formed by photolithography and etching, the electrodes 12, 13, and 14 of the base region 7, the emitter region 9, and the collector contact region 10 are respectively formed by Al, Al-Si, W, M
The bipolar transistor of the present invention can be obtained by being formed of o, W silicide, Ti, Ti silicide, or the like. An integrated circuit is manufactured by connecting the elements to each other by thin-film metal wiring or the like. Note that the type of the integrated circuit is not particularly limited.

Hereinafter, another method of manufacturing a semiconductor substrate according to the present invention will be described in detail with reference to the drawings.

FIGS. 3A to 3D are process diagrams for explaining another method of manufacturing a semiconductor substrate according to the present invention, and are shown as schematic cross-sectional views in each process. Figure
In 3, the porous Si substrate 33 and the single-crystal Si layer 32
It has a porous single crystal semiconductor layer and a non-porous single crystal semiconductor layer.
(FIG. 3B), the light-transmitting substrate 34 is light-transmitting
Substrate, porous Si substrate 33, single crystal Si layer 32, light transmission
The conductive base 34 becomes a multilayer structure (FIG. 3C).

First, as shown in FIG. 3A, a low-impurity-concentration layer 32 is formed on a high-concentration silicon single-crystal substrate 31 by epitaxial growth using various thin film growth methods.
Alternatively, protons are ion-implanted into the surface of the P-type Si single crystal substrate 31 to form the N-type single crystal layer 32.

Next, as shown in FIG.
The single crystal substrate 31 is transformed into a porous Si substrate 33 from the rear surface by an anodizing method using an HF solution. The porous Si layer, the monocrystalline Si as compared with the density of 2.33 g / cm ^3, the density of 1.1~0.6g / cm ³ by changing the density of HF solution concentration to 50 to 20% Range. This porous layer is formed on the P-type substrate as described above.

As shown in FIG. 3C, the light transmitting substrate 3
4 is prepared, and the light transmitting substrate is attached to the surface of the single crystal Si layer on the porous Si substrate. As shown in FIG. 3C, the porous Si substrate 33 is removed by etching to leave a thin single-crystal silicon layer on the light transmitting substrate.

FIG. 3D shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 35 as the etching prevention film in FIG. 3C, the single crystal Si layer 32 having the same crystallinity as the silicon wafer is flattened on the light transmitting base 34. Moreover, the layer is uniformly thinned and formed over a large area over the entire wafer.

The semiconductor substrate thus obtained can be suitably used from the viewpoint of producing an insulated electronic element.

The above is a method in which an N-type layer is formed before the formation of the porous body, and thereafter, only the P-type substrate is selectively made porous by anodizing.

The selective etching method for electroless wet etching of only porous Si will be described below.

As an etching solution having no etching action on crystalline Si and capable of selectively etching only porous Si, hydrofluoric acid, buffered hydrofluoric acid, hydrofluoric acid added with aqueous hydrogen peroxide or buffered hydrofluoric acid can be used. A mixed solution of an acid, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which an alcohol is added, and a mixed solution of hydrofluoric acid or buffered hydrofluoric acid to which an aqueous solution of hydrogen peroxide and an alcohol are added are suitably used. 5 to 12 show porous S
FIG. 7 is a characteristic diagram showing the etching time dependence of the thickness of the etched porous Si and single-crystal Si when i and single-crystal Si are infiltrated into the above various etching solutions. FIG. 5 shows a mixed solution of 49% hydrofluoric acid and hydrogen peroxide solution (1: 5), and FIG. 7 shows a mixed solution of 49% hydrofluoric acid and alcohol (FIG. 5). 10: 1), FIG. 8 shows 49%
A mixed solution of hydrofluoric acid, alcohol and aqueous hydrogen peroxide (10:
6:50) and FIG. 9 is buffered hydrofluoric acid, FIG.
0 is a mixed solution of buffered hydrofluoric acid and aqueous hydrogen peroxide (1:
5), FIG. 11 shows a mixed solution of buffered hydrofluoric acid and alcohol (10: 1), and FIG. 12 shows a mixed solution of buffered hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 50). In addition, what added alcohol was infiltrated without stirring, and what added no alcohol was infiltrated with stirring.

The porous Si is prepared by anodizing single crystal Si and the conditions are as follows. The starting material of porous Si formed by anodization is not limited to single-crystal Si, but may be Si having another crystal structure.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Porous Si thickness: 300 (μm) Porosity: 56 (%) The porous Si prepared under the above conditions was infiltrated with the above various etching solutions at room temperature.

When the thickness of the porous Si was reduced by infiltrating it into 49% hydrofluoric acid (open circles in FIG. 5) with stirring, the porous Si was rapidly etched.
90 μm in about 40 minutes, and 20 minutes after 80 minutes
Even 5 μm was etched uniformly with a high degree of surface properties.

A decrease in the thickness of the porous Si was measured for a sample infiltrated with a mixture of 49% hydrofluoric acid and aqueous hydrogen peroxide (1: 5) (open circles in FIG. 6) with stirring. The porous Si is rapidly etched to 112 μm in about 40 minutes and 256 μm after 80 minutes.
Etching was uniform with high surface properties.

A mixture of 49% hydrofluoric acid and alcohol (1
0: 1) (white circles in FIG. 7) without infiltration without stirring, the decrease in the thickness of the porous Si was measured. The porous Si was rapidly etched, and 85 μm in about 40 minutes. 195 μm after 80 minutes
Also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si, which was infiltrated without stirring into a mixture (10: 6: 50) of 49% hydrofluoric acid, alcohol and aqueous hydrogen peroxide (open circles in FIG. 8), was measured. As a result, the porous Si was rapidly etched, having a high surface property of 107 μm in about 40 minutes and 244 μm after 80 minutes, and was uniformly etched.

When a decrease in the thickness of the porous Si was measured for the buffered hydrofluoric acid (white circle in FIG. 9) which was stirred and infiltrated, the porous Si was rapidly etched and
70 μm in about 0 minutes, and 11 after 120 minutes.
Even 8 μm was etched uniformly with a high degree of surface properties.

When a mixture of buffered hydrofluoric acid and aqueous hydrogen peroxide (1: 5) (open circles in FIG. 10) was infiltrated and stirred, the decrease in the thickness of the porous Si was measured. The quality Si is rapidly etched to 88 μm in about 40 minutes, and 147 μm after 120 minutes.
Etching was uniform with high surface properties.

When a mixture of buffered hydrofluoric acid and alcohol (10: 1) (open circles in FIG. 11) was infiltrated without stirring, the decrease in the thickness of the porous Si was measured. The porous Si is rapidly etched,
67 μm in about 0 minutes, and 11 after 120 minutes.
Even 2 μm was uniformly etched with a high degree of surface properties.

The infiltration without stirring of the mixed solution (10: 6: 50) of buffered hydrofluoric acid, alcohol and aqueous hydrogen peroxide (open circle in FIG. 12) indicates the thickness of the porous Si. As a result, the porous Si was rapidly etched to 83 μm in about 40 minutes,
After 0 minutes, 140 μm was uniformly etched with a high degree of surface properties.

The solution concentration of the hydrogen peroxide solution is 30% here, but is set to a concentration that does not impair the effect of adding the following hydrogen peroxide solution and is practically acceptable in the manufacturing process and the like. You. As buffered hydrofluoric acid, ammonium fluoride (NH ₄ F) 36.2%, hydrogen fluoride (HF)
A 4.46% aqueous solution is used.

The etching rate depends on the concentration and temperature of the solution of hydrofluoric acid, buffered hydrofluoric acid and aqueous hydrogen peroxide.
By adding the hydrogen peroxide solution, the oxidation of silicon can be accelerated, and the reaction rate can be increased as compared with the case without addition. By further changing the ratio of the hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. In addition, by adding alcohol, bubbles of the reaction gas generated by the etching can be instantaneously removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

The conditions of the solution concentration and the temperature are set within a range in which the effects of hydrofluoric acid, buffered hydrofluoric acid, the above-mentioned hydrogen peroxide solution or the above-mentioned alcohol are exerted, and the etching rate is practically acceptable in the manufacturing process and the like.

In the present application, the case of the above-mentioned solution concentration and room temperature is taken as an example, but the present invention is not limited to such conditions.

The HF concentration in the buffered hydrofluoric acid is preferably set in the range of 1 to 95%, more preferably 1 to 85%, and still more preferably 1 to 70% with respect to the etching solution. The NH ₄ F concentration in the acid is set in the range of preferably 1 to 95%, more preferably 5 to 90%, and still more preferably 5 to 80% with respect to the etching solution.

The HF concentration is set in the range of preferably 1 to 95%, more preferably 5 to 90%, and still more preferably 5 to 80% with respect to the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably set in the range of 1 to 95%, more preferably 5 to 90%, and still more preferably 10 to 80%, and within a range in which the above-described hydrogen peroxide solution is exerted.

The alcohol concentration is set to preferably 80% or less, more preferably 60% or less, and still more preferably 40% or less with respect to the etching solution, and is set within a range in which the effect of the alcohol is exerted.

The temperature is set in the range of preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and still more preferably 5 to 60 ° C.

As the alcohol used in the present invention, besides ethyl alcohol, an alcohol such as isopropyl alcohol which can be practically used in the production process and the like and which can achieve the above-mentioned alcohol addition effect can be used.

Further, non-porous Si having a thickness of 500 μm was infiltrated into the above-mentioned various etching solutions at room temperature. Later
The decrease in thickness of the non-porous Si was measured. Non-porous Si
Was etched only 100 angstroms or less even after elapse of 120 minutes.

The porous Si and the non-porous Si after the etching
Was washed with water and the surface thereof was trace-analyzed with secondary ions. As a result, no impurities were detected.

[0074]

The present invention will be described below with reference to specific examples. In the embodiment described below, a case where a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution is used as an etching solution will be described as an example. Of course, a liquid can be used as well. (Example 1) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes.

The MB was placed on the P-type (100) porous Si substrate.
E (Molecular Beam Epitaxy: Molecular Beam)
The Si epitaxial layer was grown at a low temperature of 0.5 μm by the (M Epitaxy) method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec Next, the surface of the epitaxial layer was thermally oxidized by 50 nm. A fused quartz glass substrate that had been optically polished was superposed on the thermal oxide film, and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

The Si ₃ N ₄ is reduced to 0.1 by a low pressure CVD method.
The two substrates that have been deposited in μm and bonded together are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

After that, the bonded substrate is mixed with a mixed solution of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the etching rate is 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed and S
After removing the i ₃ N ₄ layer, a 0.3 μm layer was formed on the quartz glass substrate.
A single-crystal Si layer having a thickness of 5 μm was formed.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

An NPN bipolar transistor was formed on the single crystal silicon thin film. As a result, the capacitance between the collector and the substrate was reduced to approximately one-fourth to 3.4 fF, as compared with the case where a similar element was formed on a single-crystal substrate. A RAM (Random A) using the transistor as a main constituent element
ccess Memory), its electrical characteristics were evaluated, and the results were compared with those on a single crystal substrate.
The power consumption has been reduced by about 10% by 3%. It is to be noted that a method of manufacturing each transistor is omitted because a known integrated circuit manufacturing technique is used, and only a substantial method of forming a single crystal semiconductor layer is described. The same applies to the following embodiments. (Example 2) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes. An Si epitaxial layer was grown at a low temperature of 5 μm on the P-type (100) porous Si substrate by a plasma CVD method. The deposition conditions are as follows.

Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 2.5 nm / sec Next, the surface of the epitaxial layer was thermally oxidized by 50 nm. An optically polished glass substrate having a softening point near 500 ° C. on the thermally oxidized film is superimposed and placed in an oxygen atmosphere for 4 hours.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly joined.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method, and the two bonded substrates are coated, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrate was mixed with a mixed solution of 49% hydrofluoric acid, alcohol and aqueous hydrogen peroxide (10: 6: 5).
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, and the etching rate is 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 5 μm was formed on the low softening point glass substrate.

A bipolar transistor was formed on the single-crystal silicon thin film and connected to each other to form an integrated circuit. Note that a known bipolar transistor integrated circuit manufacturing technique is used for a method of manufacturing each transistor. (Example 3) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes.

On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 5 μm by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 l / min.) H ₂ (100 l / min.) Temperature: 850 ° C. Pressure: 50 Torr Time: 0.1 μm / min. Next, the surface of the epitaxial layer was thermally oxidized by 50 nm. An optically polished glass substrate having a softening point near 500 ° C. on the thermally oxidized film is superimposed and placed in an oxygen atmosphere for 4 hours.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly joined.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrate is mixed with a mixture of 49% hydrofluoric acid, alcohol and aqueous hydrogen peroxide (10: 6: 5).
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 5 μm was formed on the low softening point glass substrate.

The same effect can also be obtained when an apiesone wax or an electron wax is applied instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

A bipolar transistor was formed on the single crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 4) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes.

An Si epitaxial layer was grown at a low temperature of 1.0 μm on the P-type (100) porous Si substrate by bias sputtering. The deposition conditions are as follows.

RF frequency: 100 MHz High frequency power: 600 W Temperature: 300 ° C. Ar gas pressure: 8 × 10 ⁻³ Torr Growth time: 120 minutes Target DC bias: −200 V Substrate DC bias: +5 V Next, the surface of this epitaxial layer was It was thermally oxidized by 50 nm. An optically polished glass substrate having a softening point near 500 ° C. on the thermally oxidized film is superimposed and placed in an oxygen atmosphere for 4 hours.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly joined.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by a plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 1.0 μm was formed on the low softening point glass substrate.

The same effect can be obtained also when apiesone wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

A bipolar transistor was formed on the single crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 5) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time is 8.4 μm / m
in. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes.

A 10-micron low-temperature Si epitaxial layer was grown on the P-type (100) porous Si substrate by a liquid phase growth method. The growth conditions are as follows.

Solvent: Sn Growth temperature: 900 ° C. Growth atmosphere: H ₂ Growth time: 20 minutes Next, the surface of the epitaxial layer was thermally oxidized by 50 nm. An optically polished glass substrate having a softening point near 800 ° C. on the thermally oxidized film is superposed on the thermal oxide film.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly joined.

Si ₃ N ₄ is reduced to 0.1 by a low pressure CVD method.
The two substrates that have been deposited in μm and bonded together are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates were mixed with a mixture of 49% hydrofluoric acid, alcohol and aqueous hydrogen peroxide (10: 6: 5).
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, 10 μm
A single-crystal Si layer having a thickness of m was formed. Also, S
The same effect can be obtained when an apiesone wax or an electron wax is applied instead of the i ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

A bipolar transistor was formed on the single crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 6) P-type (10
0) A 0.5 micron Si epitaxial layer was grown on a Si substrate by CVD. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 1 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / min. P-type (100) Si with a thickness of 200 microns
The entire substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous and the Si epitaxial layer did not change.

Next, the surface of this epitaxial layer is
nm. An optically polished fused silica glass substrate is superimposed on the thermal oxide film, and 800
By heating at 0.5 ° C. for 0.5 hour, both substrates were firmly joined.

Si ₃ N ₄ is reduced to 0.1 by a low pressure CVD method.
μm was deposited and the two bonded substrates were covered, and only the nitride film on the porous substrate was removed by reactive ion etching.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide (10: 6: 5).
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed and S
After removing the i ₃ N ₃ layer, 0.5 μm
A single-crystal Si layer having a thickness of m was formed. Also, S
The same effect can be obtained when an apiesone wax or an electron wax is applied instead of the i ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

A bipolar transistor was formed on the single crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 7) P-type (10
0) By ion implantation of protons on the surface of the Si substrate, N
A 1-micron type Si layer was formed. H ⁺ injection volume is 5 × 1
0 ¹⁵ (ions / cm ² ). 50% of this substrate
In an HF solution of The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / min. The whole P-type (100) Si substrate having a thickness of 200 microns was made porous in 24 minutes. As mentioned above, in this anodization,
Only the P-type (100) Si substrate was made porous, and the N-type Si layer did not change. Next, the surface of the N-type single crystal layer was thermally oxidized by 50 nm. An optically polished fused silica glass substrate is superimposed on the thermal oxide film, and is placed in an oxygen atmosphere.
By heating at 0 ° C. for 0.5 hour, both substrates are
Strongly joined.

Si ₃ N ₄ is reduced to 0.1 by a low pressure CVD method.
The two substrates that have been deposited in μm and bonded together are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₃ layer, a 1.0
A single-crystal Si layer having a thickness of μm was formed.

The same effect can be obtained when apiesone wax or electron wax is applied instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

A bipolar transistor was formed on the single crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 8) P-type (10
0) A single crystal Si substrate was anodized in a 50% HF solution. The current density at this time was 10 mA / cm ²
Met. A porous layer having a thickness of 20 microns was formed on the surface in 10 minutes. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 1 / min.), H ₂ (100 1 / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer Was thermally oxidized by 50 nm. A fused silica glass substrate that had been optically polished was superposed on the thermal oxide film, and heated at 450 ° C. for 0.5 hour in an oxygen atmosphere, whereby both substrates were firmly joined.

Thereafter, 490 is applied from the back surface of the silicon substrate.
It was removed by micron polishing to expose the porous layer.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method, and the two bonded substrates are coated, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrate was mixed with a mixed solution of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5
In step 0), selective etching is performed without stirring. After 15 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-layer was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 15 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several angstroms) in the non-porous layer is a thickness reduction that can be ignored in practical use. After removing the Si ₃ N ₄ layer, a single-crystal Si layer having a thickness of 0.5 μm was formed on the fused quartz glass substrate.

[0125] The same effect can be obtained when an apiesone wax or an electron wax is applied instead of the Si ₃ N ₄ layer, and only the porous Si layer can be completely removed.

A bipolar transistor was formed on the single-crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 9) P-type (10
0) A Si epitaxial layer was grown on a Si substrate by 1 μm by a CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 1 / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . At this time, the rate of making porous is 8.4 μm / mi.
n. And a P-type (10
0) The entire Si substrate was made porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, a fused quartz glass substrate that has been optically polished is superposed on the surface of the epitaxial layer, and heated at 800 ° C. for 0.5 hour in an oxygen atmosphere, whereby the two substrates are firmly joined. Was.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method, and the two bonded substrates are coated, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrate was mixed with a mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5
In step 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains without being etched,
Using single crystal Si as an etch stop material, porous S
The i-substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 minutes even after 65 minutes.
The selectivity with the etching rate of the porous layer reaches about 10 times or more, and the etching amount (several tens of angstroms) in the non-porous layer is a practically negligible decrease in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, one layer is placed on the quartz glass substrate.
A single-crystal Si layer having a thickness of μm was formed.

As a result of observation of a cross section by a transmission electron microscope,
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained. A bipolar transistor was formed on the single-crystal silicon thin film and connected to each other to form an integrated circuit. A known integrated circuit manufacturing technique is used for the method of manufacturing each transistor.

[0133]

As described in detail above, the method of manufacturing the bipolar transistor of the present invention and the semiconductor device using the same
According to the manufacturing method described above, a high-performance bipolar transistor is manufactured by manufacturing a high-quality single crystal layer formed on a substrate having light transmittance at least in a visible light region. Therefore, a bipolar transistor having a reduced substrate and collector capacitance can be manufactured on a light-transmitting substrate, and high-speed operation is possible. In addition, low-cost elements and integrated circuits with excellent radiation resistance without soft errors due to α-rays are used. It can be provided by.

Conventionally, a high-quality single-crystal layer cannot be obtained on a light-transmitting substrate represented by glass because the crystal structure of the substrate is generally amorphous. According to the original, a high-quality single-crystal Si substrate as a starting material,
The single crystal layer can be transferred onto a light-transmitting substrate (eg, a glass substrate mainly composed of transparent SiO ₂ ), and can be transferred onto a light-transmitting substrate that is essential for a contact sensor or a projection-type liquid crystal image display device. Therefore, a high-performance driving element can be manufactured, a large number of processes can be performed in a short time, and the productivity and economic efficiency are greatly improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a bipolar transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a substrate manufacturing step of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a substrate manufacturing step of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining a process of the present invention.

FIG. 5 shows the etching characteristics of porous and non-porous Si.

FIG. 6 shows etching characteristics of porous and non-porous Si.

FIG. 7 shows etching characteristics of porous and non-porous Si.

FIG. 8 shows etching characteristics of porous and non-porous Si.

FIG. 9 shows etching characteristics of porous and non-porous Si.

FIG. 10 shows etching characteristics of porous and non-porous Si.

FIG. 11 shows etching characteristics of porous and non-porous Si.

FIG. 12 shows etching characteristics of porous and non-porous Si.

[Explanation of symbols]

1 light transmissive substrate, 2 NPN bipolar transistor, 3 PNP bipolar transistor, 4 island-shaped single crystal layer, 5 island-shaped single crystal layer, 6 collector region,
7 base region, 8 oxide film, 9 emitter region,
10 collector contact area, 11 interlayer insulating layer,
DESCRIPTION OF SYMBOLS 12 Base electrode, 13 Emitter electrode, 14 Collector electrode, 21 Porous Si substrate, 22 Non-porous Si single crystal layer, 23 Glass light transmissive substrate, 24 Etch prevention film, 25 Silicon oxide layer, 31 P-type S
i single crystal substrate, 32 N-type Si single crystal layer, 33 porous Si substrate, 34 light transmitting substrate, 35 etching prevention film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-150360 (JP, A) JP-A-62-174969 (JP, A) JP-A-3-110852 (JP, A) JP-A 61-174 114571 (JP, A) JP-A-1-196169 (JP, A) JP-A-2-252265 (JP, A) JP-A-3-131062 (JP, A) JP-A-4-35044 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 27/12 H01L 29/73

Claims (5)

(57) [Claims] In a bipolar transistor, a single crystal layer constituting at least an active region is formed by the following step (a):
Bipolar transistor formed by step including (b)
Star manufacturing method. (A) a member having a porous monocrystalline semiconductor layer and a nonporous single crystal semiconductor layer, and a light transmissive substrate having optical transparency at least in the visible light region, wherein said non-porous single-crystal semiconductor layer is an inner and removing the porous monocrystalline semiconductor layer from allowed <br/> Awa bonded to the multilayer structure is obtained that the step (b) the multilayer structure located on said single crystal on the light-transmissive on the substrate Layer
Forming the non-porous single crystal layer 2. The method according to claim 1, wherein the single crystal layer constituting at least the active region of the bipolar transistor comprises the following steps (a):
Bipolar transistor formed by step including (b)
Star manufacturing method. (A) a member having a porous monocrystalline semiconductor layer and a nonporous single crystal semiconductor layer, and a light transmissive substrate having optical transparency at least in the visible light region through the insulating layer, said non-porous single crystal semiconductor layer and removing the porous monocrystalline semiconductor layer from step (b) the multilayer structure Ru bonded to the multilayer structure is obtained which is located inside the insulating layer on the light transmitting on a substrate Through
Forming the non-porous single-crystal layer to be the single-crystal layer;
About 3. The method for manufacturing a bipolar transistor according to claim 1 , wherein the bipolar transistor is a semiconductor device.
Transistor is NPN type bipolar transistor
Manufacturing method. 4. The method for manufacturing a bipolar transistor according to claim 1 , wherein
Transistor is a PNP type bipolar transistor
Manufacturing method. 5. A bipolar transistor as a constituent element.
A method of manufacturing a semiconductor device, comprising:
5. A method for manufacturing a semiconductor device, comprising manufacturing a transistor by the method for manufacturing a bipolar transistor according to claim 3 .
Construction method.