JP2004356532A - Process for producing compound semiconductor substrate, compound semiconductor substrate, process for fabricating device, device, electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for producing a compound semiconductor substrate in which the yield is prevented from lowering due to dust particles being produced when a film is floated by wet etching. <P>SOLUTION: The process for producing a compound semiconductor substrate where a semiconductor substrate including a semiconductor layer 206a is provided on a supporting substrate 10A comprises a step for pasting the supporting substrate 10A and the semiconductor substrate, and a step for patterning the semiconductor layer 206a after both substrates are pasted. In the step for patterning the semiconductor layer 206a, circumferential edge part of the semiconductor layer 206a is removed simultaneously with the patterning. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a composite semiconductor substrate in which a semiconductor substrate having a semiconductor layer is bonded to a support substrate, and a composite semiconductor substrate in which a device formation layer having a semiconductor layer is bonded to a support substrate. The present invention relates to a method for manufacturing a device, and to a composite semiconductor substrate and a device, an electro-optical device, and an electronic apparatus obtained by the method.
[0002]
[Prior art]
SOI (Silicon on Insulator) technology, in which a semiconductor layer made of a silicon layer is formed on an insulator, and a semiconductor device such as a transistor element is formed on the semiconductor layer, uses high-speed, low power consumption, and high integration of the element. It is applied to the manufacture of a substrate for manufacturing an electro-optical device such as a liquid crystal device.
[0003]
To manufacture a substrate for an electro-optical device using SOI technology, first, a semiconductor substrate having a single crystal semiconductor layer made of single crystal silicon or the like is attached to a supporting substrate, and a thin film single crystal semiconductor layer is formed by a polishing method or the like. Formed into a composite semiconductor substrate. Next, a method of forming the thin film single crystal semiconductor layer of the composite semiconductor substrate into a device such as a thin film transistor (hereinafter abbreviated as “TFT”) for driving a liquid crystal is adopted.
[0004]
By the way, in such a composite semiconductor substrate (bonded SOI substrate) using the SOI technology, the bonding strength between the supporting substrate and the semiconductor substrate is weak, that is, at the peripheral end of the semiconductor substrate, Local peeling in which the semiconductor substrate floats from the supporting substrate may occur. In particular, a wet etching process at the time of manufacturing a device from a thin film single crystal semiconductor layer (device formation layer) causes a wet etching solution to enter a bonding interface between a semiconductor substrate and a supporting substrate, thereby causing film floating (peeling). .
[0005]
When such a film floating (peeling) occurs, the thin film single crystal semiconductor layer at the film floating portion is peeled off from the composite semiconductor substrate in, for example, a wet etching step, and this is thin film single crystal semiconductor of the composite semiconductor substrate via the wet etching solution. Foreign matter remains on the layer, causing a problem of lowering the yield. Therefore, in order to solve the above problem, for example, a technique for reducing foreign matter by arranging a single-crystal semiconductor layer inside the wafer rather than the base oxide film and having no single-crystal semiconductor layer on the floating portion of the film has been proposed. It is disclosed (for example, see Patent Document 1).
[0006]
[Patent Document 1]
JP 2000-243942 A
[Problems to be solved by the invention]
However, the method of Patent Document 1 has a separate step of arranging the single crystal semiconductor layer on the inner side of the wafer with respect to the base oxide film, which complicates the manufacturing process, lowers the manufacturing efficiency, and increases the cost. Sometimes they are connected.
[0008]
The present invention has been made in view of the above circumstances. In particular, even when a new film floating (peeling) occurs due to wet etching, foreign matter is generated due to the film floating, thereby reducing the yield. It is an object of the present invention to provide a method for manufacturing a composite semiconductor substrate and a method for manufacturing a device, which can easily prevent the above. It is still another object of the present invention to provide a composite semiconductor substrate and a device obtained by using these manufacturing methods, and to provide an electro-optical device and an electronic apparatus including the device.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a method for manufacturing a composite semiconductor substrate according to the present invention is a method for manufacturing a composite semiconductor substrate in which a semiconductor substrate including a semiconductor layer is provided on a support substrate, wherein the support substrate and the semiconductor A step of bonding the substrate to the substrate, and a step of patterning the semiconductor layer after the bonding. In the step of patterning the semiconductor layer, the peripheral edge of the semiconductor layer is removed simultaneously with the patterning. .
[0010]
According to such a manufacturing method, since the peripheral edge of the semiconductor layer is removed, when this composite semiconductor substrate is used, for example, as a substrate for a device, the film floats on the peripheral edge of the substrate by, for example, wet etching. Even when (peeling) or the like occurs, it is possible to prevent or suppress the generation of foreign matter from the semiconductor layer due to the film floating, thereby preventing the yield from decreasing. Further, in the present invention, since the peripheral edge removal of the semiconductor layer is performed simultaneously with the patterning step of the semiconductor layer, without separately performing a process for suppressing generation of foreign matter at the time of film floating, There is no reduction in manufacturing efficiency and therefore no increase in cost.
[0011]
The patterning of the semiconductor layer and the removal of the peripheral edge may be performed by the same dry etching process. In this case, in the step of patterning the semiconductor layer and the step of removing the peripheral edge portion, it is possible to prevent or suppress the occurrence of film floating or the like, and it is possible to provide a more reliable composite semiconductor substrate.
[0012]
Further, the method may include a step of removing a peripheral end of the semiconductor substrate after the bonding and before the step of patterning the semiconductor layer. In this case, in the bonding step, even if a film floating or the like occurs at the peripheral end portion of the semiconductor substrate, the semiconductor layer is patterned after removing the film floating. Can be provided.
[0013]
Next, a composite semiconductor substrate according to the present invention is characterized by being obtained by the above-described manufacturing method. Such a composite semiconductor substrate is preferably used, for example, as a substrate for a device, and when used as a substrate for a device, a film floats on the peripheral edge of the substrate by, for example, wet etching at the time of processing for a device. Even when (peeling) or the like occurs, it is possible to prevent or suppress the generation of foreign matter from the semiconductor layer due to the film floating, thereby preventing the yield from decreasing. That is, the composite semiconductor substrate of the present invention is suitable as a highly reliable device-forming substrate with few defects.
[0014]
Next, in order to solve the above problem, a method for manufacturing a device according to the present invention uses a composite semiconductor substrate obtained by bonding a semiconductor substrate having a semiconductor layer to be a device formation layer and a support substrate, In a method of manufacturing a device for forming a device from, the step of patterning the semiconductor layer for forming the device, and the step of wet etching the composite semiconductor substrate after the patterning, in the patterning step of the semiconductor layer, The method is characterized in that the peripheral edge of the semiconductor layer is removed at the same time as the patterning.
[0015]
According to such a manufacturing method, since the peripheral edge of the semiconductor layer is removed, even if film floating (peeling) or the like occurs at the peripheral edge of the substrate due to a later wet etching process, the film floating is prevented. As a result, the generation of foreign matter from the semiconductor layer is prevented or suppressed, thereby making it possible to prevent the yield from decreasing. Further, in the present invention, since the peripheral edge of the semiconductor layer is removed at the same time as the step of patterning the semiconductor layer for device formation, a process for suppressing the generation of foreign matter when the film floats is performed. Without any separate operation, there is no reduction in manufacturing efficiency and therefore no increase in cost. Note that patterning the semiconductor layer for device formation means that a region of the semiconductor layer where a device is to be formed is selectively formed in an island shape.
[0016]
The patterning and the peripheral edge removal of the semiconductor layer may be performed by the same dry etching process. In this case, in the step of patterning the semiconductor layer and the step of removing the peripheral edge, it is possible to prevent or suppress the occurrence of film floating or the like, and to provide a more reliable device.
[0017]
Further, the method may include a step of removing a peripheral end of the semiconductor substrate before the step of patterning the semiconductor layer. In this case, even if a film floating or the like occurs at the peripheral end of the semiconductor substrate in the bonding step, the semiconductor layer is patterned after removing the film floating, so that a more reliable device is provided. It becomes possible.
[0018]
Next, the device of the present invention is characterized by being obtained by the above-mentioned manufacturing method. According to such a device, the generation of foreign matter is prevented in the manufacturing process, and the occurrence of defects due to the generation of foreign matter is prevented, so that a stable yield is ensured and the device is extremely reliable. .
[0019]
Further, an electro-optical device according to the present invention includes the device. According to this electro-optical device, since the device has a highly reliable device, the electro-optical device itself has few defects and is highly reliable. According to another aspect of the invention, there is provided an electronic apparatus including the electro-optical device. According to the electronic apparatus, since the electronic apparatus includes the highly reliable electro-optical device, the electronic apparatus itself has few defects and is highly reliable.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail.
First, a liquid crystal panel as an example of the electro-optical device of the present invention, which is manufactured by applying the method of manufacturing a composite semiconductor substrate and the method of manufacturing a device of the present invention, will be described. FIG. 1 is a plan view for explaining the overall configuration of the liquid crystal panel, and is a plan view showing a state in which a TFT array substrate is viewed from the side of a counter substrate together with components formed thereon. FIG. 2 is a sectional view taken along the line AA ′ of FIG.
[0021]
The liquid crystal panel shown in FIGS. 1 and 2 has liquid crystal sealed between a pair of substrates, and includes a thin film transistor (hereinafter abbreviated as TFT) array substrate 10 which forms one of the substrates, and a thin film transistor (TFT) array substrate 10. And an opposing substrate 20 which is the other substrate disposed to oppose.
FIG. 1 shows a state in which a TFT array substrate 10 is viewed from a counter substrate 20 side together with components formed thereon. As shown in FIG. 1, a sealing material 51 is provided along the edge of the TFT array substrate 10, and a light shielding film 53 as a frame is provided inside the sealing material 51 in parallel with the sealing material 51. Have been. In FIG. 1, reference numeral 52 indicates a display area. The display area 52 is an area inside the light-shielding film 53 as a picture frame, and is an area used for display on a liquid crystal panel. Reference numeral 54 denotes a non-display area that is an area outside the display area.
[0022]
In the non-display area 54, a data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10, and a scanning line driving circuit 104 is provided along two sides adjacent to this one side, The precharge circuit 103 is provided along one remaining side. Further, a plurality of wirings 105 for connecting the data line driving circuit 101, the precharge circuit 103, the scanning line driving circuit 104, and the external circuit connection terminal 102 are provided.
At a position corresponding to the corner of the opposing substrate 20, a conductive material 106 for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 is provided. The opposite substrate 20 having substantially the same contour as the sealing material 51 is fixed to the TFT array substrate 10 by the sealing material 51.
[0023]
As shown in FIG. 2, the TFT array substrate 10 includes a substrate main body 10A made of a light-transmissive insulating substrate such as quartz, and a TFT (Indium Tin Oxide) film formed on the liquid crystal layer 50 side surface. A pixel electrode 9a made of a transparent conductive film, a pixel switching TFT (switching element) 30 provided in a display area, and a driving circuit TFT (switching element) (not shown) provided in a non-display area; It is mainly composed of an alignment film 16 formed of an organic film such as a polyimide film and subjected to a predetermined alignment treatment such as a rubbing treatment.
[0024]
On the other hand, the opposing substrate 20 is composed of a substrate main body 20A made of a light-transmitting substrate such as transparent glass or quartz, an opposing electrode 21 formed on the surface of the liquid crystal layer 50 side, an alignment film 22, a metal or the like. And a light-shielding film 53 provided in a region other than the opening region of each pixel portion, and a light-shielding film 53 as a frame made of the same or different material as the light-shielding film 23.
A liquid crystal layer 50 is formed between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and are arranged so that the pixel electrode 9a and the opposing electrode 21 face each other.
[0025]
As shown in FIG. 2, a light-shielding layer 11a is provided at a position corresponding to each pixel switching TFT 30 on the surface of the substrate body 10A of the TFT array substrate 10 on the liquid crystal layer 50 side. Further, a first interlayer insulating film 12 is provided between the light shielding layer 11a and the pixel switching TFT 30. The first interlayer insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the pixel switching TFT 30 from the light shielding layer 11a.
[0026]
As shown in FIG. 2, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a channel region 1a ′ of the semiconductor layer 1a where a channel is formed by an electric field from the scanning line 3a, and a scanning line 3a. Insulating film 2 that insulates the semiconductor layer 1a from the semiconductor layer 1a, the data line 6a, the low-concentration source region 1b and the low-concentration drain region 1c of the semiconductor layer 1a, the high-concentration source region (source region) 1d of the semiconductor layer 1a, and the high-concentration drain A region 1e (drain region) is provided.
[0027]
Here, the semiconductor layer 1a is made of single crystal silicon, and the thickness of the semiconductor layer 1a is desirably 150 nm or more. When the thickness is less than 150 nm, processing for providing a contact hole for connecting the pixel electrode 9a and the switching element (the pixel switching TFT 30 or the driving circuit TFT) or the processing of the switching element (the pixel switching TFT 30 or the driving circuit TFT) is performed. This is because there is a possibility that the withstand voltage may be adversely affected.
The gate insulating film 2 preferably has a thickness of, for example, about 60 to 80 nm. This is because, especially when the driving voltage of the pixel switching TFT 30 or the driving circuit TFT (not shown) is set to about 10 to 15 V, the thickness in the above range is necessary to secure the withstand voltage. .
[0028]
In this liquid crystal panel, the gate insulating film 2 extends from a position facing the scanning line 3a and is used as a dielectric film, and the semiconductor film 1a extends and serves as a first storage capacitor electrode 1f. The storage capacitor 70 is configured by using a part of the opposing capacitor line 3b as a second storage capacitor electrode. The capacitor line 3b and the scanning line 3a have the same polysilicon film or a laminated structure of a polysilicon film and a metal simple substance, an alloy, a metal silicide, etc., and have a dielectric film of the storage capacitor 70, a pixel switching TFT 30, and a driving circuit. The gate insulating film 2 of the circuit TFT (not shown) is made of the same high-temperature oxide film. The channel region 1a ', source region 1d, and drain region 1e of the pixel switching TFT 30, the channel region, source region, and drain region of the driver circuit TFT (not shown), and the first storage capacitor electrode are the same. Of the semiconductor layer 1a. The semiconductor layer 1a is formed of single-crystal silicon as described above, and is provided on the TFT array substrate 10 to which SOI (Silicon On Insulator) technology is applied.
[0029]
As shown in FIG. 2, a second interlayer insulating film 4 is formed on the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 12, and the second interlayer insulating film 4 includes A contact hole 5 leading to the high concentration source region 1d of the pixel switching TFT 30 and a contact hole 8 leading to the high concentration drain region 1e of the pixel switching TFT 30 are formed. Further, a third interlayer insulating film 7 is formed on the data line 6a and the second interlayer insulating film 4, and the third interlayer insulating film 7 is in contact with the high-concentration drain region 1e of the pixel switching TFT 30. A hole 8 is formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.
[0030]
Next, an example of a method for manufacturing a device and a method for manufacturing a composite semiconductor substrate of the present invention based on a method for manufacturing a liquid crystal panel having such a configuration will be described.
First, a method of manufacturing the TFT array substrate 10 in the method of manufacturing the liquid crystal panel shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 and 4 and FIGS. 5 to 7 and FIGS. 8 to 10 are shown on different scales.
First, a process of forming the light shielding layer 11a and the first interlayer insulating film 12 on the surface of the substrate main body 10A of the TFT array substrate 10 will be described with reference to FIGS. 3 and 4 are process diagrams showing a part of the TFT array substrate in each process corresponding to the cross-sectional view of the liquid crystal panel shown in FIG.
[0031]
First, a transparent substrate main body 10A such as a quartz substrate or hard glass is prepared. Here, the substrate main body 10A serves as a support substrate in the present invention. The substrate main body 10A is preferably annealed at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C. in an inert gas atmosphere such as N ₂ (nitrogen), and then subjected to a high-temperature process to be performed later. It is desirable to perform pre-processing so as to reduce distortion generated in the image. That is, it is desirable to heat-treat the substrate body 10A at the same temperature or higher in accordance with the highest temperature processed in the manufacturing process.
[0032]
As shown in FIG. 3A, a single metal or alloy containing at least one of Ti, Cr, W, Ta, Mo and Pb is provided on the entire surface of the substrate body 10A thus treated. The light shielding material layer 11 is formed by depositing a metal silicide or the like to a thickness of, for example, 150 to 200 nm by a sputtering method, a CVD method, an electron beam heating evaporation method, or the like.
[0033]
Next, a photoresist layer is formed on the entire surface of the substrate body 10A, and the photoresist layer is exposed using a photomask having a pattern of the light-shielding layer 11a to be finally formed. Thereafter, by developing the photoresist layer, a photoresist 207 having a pattern of the light-shielding layer 11a to be finally formed is formed as shown in FIG.
[0034]
Next, the light-shielding material layer 11 is etched using the photoresist 207 as a mask, and then the photoresist 207 is peeled off, so that the pixel switching TFT 30 formation region on the surface of the substrate body 10A is formed as shown in FIG. As shown in FIG. 2, a light-shielding layer 11a having a predetermined pattern (see FIG. 2) is formed. The thickness of the light-shielding layer 11a is, for example, 150 to 200 nm.
[0035]
Next, as shown in FIG. 4A, a first interlayer insulating film 12 is formed by a sputtering method, a CVD method, or the like on the surface of the substrate main body 10A on which the light shielding layer 11a is formed. At this time, a projection 12a is formed on the surface of the first interlayer insulating film 12 on the region where the light shielding layer 11a is formed. Examples of the material of the first interlayer insulating film 12 include silicon oxide, high insulating glass such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), and BPSG (boron phosphorus silicate glass). And the like.
[0036]
Next, the surface of the first interlayer insulating film 12 is polished by a method such as a CMP (Chemical Mechanical Polishing) method, and as shown in FIG. The surface of the film 12 is flattened. The thickness of the first interlayer insulating film 12 is about 400 to 1000 nm, more preferably about 800 nm.
[0037]
Next, a method for manufacturing the TFT array substrate 10 from the substrate main body (supporting substrate) 10A on which the first interlayer insulating film 12 is formed will be described with reference to FIGS. 5 to 10 are process diagrams showing a part of the TFT array substrate in each process corresponding to the cross-sectional view of the liquid crystal panel shown in FIG.
FIG. 5A is a diagram showing a part of FIG. 4B taken out and shown in a different scale. As shown in FIG. 5B, a substrate body 10A having a first interlayer insulating film 12 having a planarized surface shown in FIG. 5A, and a single crystal silicon substrate 206 on which a single crystal silicon layer 206a is formed. And bonding. Note that the substrate body 10A and the single-crystal silicon substrate 206 are usually bonded together from the viewpoint of cost or the like, as shown in FIG. For example, it is set to be about 3 mm inside from the end.
[0038]
Here, the single crystal silicon substrate 206 serves as a semiconductor substrate in the present invention, and the single crystal silicon layer 206a serves as a semiconductor layer in the present invention, that is, a device forming layer for forming a device. Then, the bonded substrate S of the present invention is formed from the single crystal silicon substrate 206, the substrate main body 10A and the first interlayer insulating film 12.
The thickness of the single crystal silicon substrate 206 is, for example, 600 μm, and an oxide film layer 206b is formed in advance on the surface of the single crystal silicon substrate 206 on the side to be bonded to the substrate body 10A. In addition, hydrogen ions (H +) are implanted into the single crystal silicon substrate 206 under the conditions of, for example, an acceleration voltage of 100 keV and a dose of 10 × 10 16 / cm 2. The oxide film layer 206b is formed by oxidizing the surface of the single crystal silicon substrate 206 by about 0.05 to 0.8 μm.
[0039]
For the bonding step, for example, a method of directly bonding two substrates by performing a heat treatment at 300 ° C. for 2 hours can be adopted. Further, in order to further increase the bonding strength, it is necessary to raise the heat treatment temperature to about 450 ° C. However, the thermal expansion coefficient of the substrate body 10A made of quartz or the like and the thermal expansion coefficient of the single crystal silicon substrate 206 are different. Since there is a large difference between them, if heating is continued as such, defects such as cracks may occur in the single crystal silicon layer 206a, and the quality of the manufactured TFT array substrate 10 may be degraded.
[0040]
In order to suppress the occurrence of defects such as cracks, the single-crystal silicon substrate 206 that has been once heat-treated at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, and then subjected to a higher-temperature heat treatment. It is desirable. For example, the single crystal silicon substrate 206 is etched using an aqueous solution of KOH at 80 ° C. so that the thickness of the single crystal silicon substrate 206 becomes 150 μm, then bonded to the substrate body 10A, and further heat-treated at 450 ° C. It is desirable to increase the joining strength.
[0041]
As another method for further increasing the bonding strength, a method of bonding the substrate body 10A and the single crystal silicon substrate 206 and then heating the substrate body by a rapid thermal processing (RTA) or the like can be adopted. The heating temperature is preferably from 600 ° C. to 1200 ° C., and more preferably from 1050 ° C. to 1200 ° C. in order to lower the viscosity of the first interlayer insulating film 12 and the oxide film layer 206b and to increase the atomic adhesion.
[0042]
After the bonded substrate S is formed in this manner, when forming a device from the single-crystal silicon layer 206, particularly before the first wet-etching process of the bonded substrate S, the peripheral portion of the single-crystal silicon substrate 206 is formed. That is, the peripheral edges of the single crystal silicon layer 206a and the oxide film layer 206b are removed by dry etching. This is because, after the bonding step, stress is applied particularly due to a difference in thermal expansion coefficient between the substrate main body 10A and the single crystal silicon substrate 206, and as a result, as shown in FIG. At the exposed end between the single-crystal silicon substrate 206 and the substrate main body 10A, in this example, at the interface between the oxide film layer 206b and the first interlayer insulating film 12 due to peeling. This is because it can happen.
[0043]
As for the dry etching of the peripheral portion of the single crystal silicon substrate 206, first, a resist pattern 80 is formed on the single crystal silicon substrate 206 as shown in FIG. . Here, the resist pattern 80 is formed so as to expose the peripheral end of the single crystal silicon substrate 206 with a width of, for example, about 2 mm and cover the entire inner surface thereof.
[0044]
Next, using the resist pattern 80 as a mask, the single crystal silicon layer 206a and the oxide film layer 206b at the peripheral end of the single crystal silicon substrate 206 are removed by dry etching. For the dry etching, conventionally known conditions can be adopted. Thereafter, the resist pattern 80 is removed as shown in FIG.
By doing so, even if the film floating T occurs at the interface between the single crystal silicon substrate 206 and the substrate body 10A as described above, the film floating T occurs as shown in FIG. The portion (peripheral end) that has been removed is removed, and as a result, a favorable state without the film floating T at the interface is obtained.
Here, since the first interlayer insulating film 12 which is the base of the oxide film layer 206b is basically made of the same material as the oxide film layer 206b, overetching of the first interlayer insulating film 12 is controlled by controlling the etching time and the like. Is preferably minimized. However, even if the first interlayer insulating film 12 is over-etched, it does not particularly hinder the subsequent device formation.
[0045]
Next, as shown in FIG. 6A, the single-crystal silicon layer 206b and the part of the single-crystal silicon layer 206a on the bonding surface side of the single-crystal silicon substrate 206 are left. A heat treatment is performed to peel (separate) the remaining portion of 206a from the substrate body 10A side. This substrate peeling phenomenon occurs because silicon bonds are broken in a layer near the surface of the single crystal silicon substrate 206 by hydrogen ions introduced into the single crystal silicon substrate 206. The heat treatment here can be performed, for example, by heating the two bonded substrates to 600 ° C. at a rate of 20 ° C./min. By this heat treatment, a part of the bonded single crystal silicon substrate 206 is separated from the substrate main body 10A, and a single crystal silicon layer 206a of about 200 nm ± 5 nm is formed on the surface of the substrate main body 10A.
[0046]
After the thickness of the single-crystal silicon layer 206a is reduced, the single-crystal silicon layer 206a is heated as shown in FIG. 6B so as to further reduce the thickness of the single-crystal silicon layer 206a to a desired thickness. Oxidation forms a sacrificial oxide layer 206c with a thickness of about 300 nm on the surface layer. Then, the formed sacrificial oxide layer 206c is wet-etched with a wet etchant such as HF (hydrofluoric acid), and is removed as shown in FIG. 6C to reduce the thickness of the single-crystal silicon layer 206a to, for example, 50 nm. To about. At this time, if the etching of the sacrificial oxide layer 206c is performed by wet etching instead of dry etching, the single crystal silicon layer 206a, which is the underlying layer of the sacrificial oxide layer 206c, is damaged by the dry etching. This is because when a device is made from the crystalline silicon layer 206a, desired characteristics may not be obtained.
[0047]
When wet etching is performed in this manner, the wet etching liquid permeates the interface between the single crystal silicon substrate 206 and the substrate body 10A, that is, the interface between the oxide film layer 206b and the first interlayer insulating film 12, and particularly the oxidizing solution. Due to the dissolution of the film layer 206b or the like, a film floating T due to peeling may occur here as shown in FIG. 6C.
[0048]
Therefore, immediately after the wet etching process, the peripheral edge of the single crystal silicon substrate 206 (the single crystal silicon layer 206a and the oxide film layer 206b) is dry-etched in order to remove the film floating T in the same manner as described above. I do.
That is, as shown in FIG. 6D, a resist pattern 81 is formed in a state where the peripheral end portion of the single crystal silicon substrate 206 is exposed with a width of, for example, about 2 mm, and then the resist pattern 81 is used as a mask. The single-crystal silicon layer 206a and the oxide film layer 206b at the peripheral edge of the crystalline silicon substrate 206 are removed by dry etching.
Thereafter, by removing the resist pattern 301, a portion (peripheral end) where the film floating T has occurred can be removed as shown in FIG. Not in good condition.
[0049]
Note that when there are a plurality of types of devices to be formed with respect to the single crystal silicon layer 206a to be a device formation layer, it may be desirable that the thickness of the single crystal silicon layer 206a be different for each type. In such a case, the thermal oxidation treatment, the wet etching treatment, the resist pattern formation, the dry etching treatment, and the resist pattern removal shown in FIGS. 6B to 6E are further repeated. The film floating T generated at the peripheral end of the crystalline silicon substrate 206 is removed.
[0050]
Next, a step of separating and forming a single crystal silicon layer 206a to be a device formation layer on the bonded substrate S in which the thickness of the single crystal silicon layer 206a has been adjusted as described above will be described.
First, as shown in FIG. 7A, the single crystal silicon layer 206a is patterned by a mesa type separation method using a photolithography technique, an etching technique, or the like. In particular, patterning is performed in such a manner that an island-shaped semiconductor layer remains corresponding to a region where a device is to be formed, thereby obtaining a composite semiconductor substrate W.
In this embodiment, dry etching is used as an etching technique, and the peripheral end 208 of the single crystal silicon layer 206a is etched away at the same time as the patterning of the single crystal silicon layer 206a. That is, a mask having an opening (a region where a mask is not formed) at the peripheral end 208 of the single crystal silicon layer 206a is used as a mask for etching the single crystal silicon layer 206a, The peripheral end 208 is to be removed.
Next, as shown in FIG. 7B, the patterned single-crystal silicon layer 206a is thermally oxidized at a temperature of about 800 to 1050 ° C. to form a thermal oxide film (silicon oxide film) 206d.
[0051]
Next, a process of forming a device from the composite semiconductor substrate W including the single crystal silicon layer 206a thus patterned will be described. Note that the drawings explaining the subsequent steps are shown on a scale different from those in FIGS. 5 to 7 and include a part of the parts shown in FIGS. 5 to 7, and the oxide film layer 206 b is The illustration is omitted on the assumption that the state is as shown in FIG.
First, as shown in FIG. 8A, a predetermined region of the single crystal silicon layer 206a is defined as a semiconductor layer 1a. In particular, as shown in FIG. 2, the region where the capacitance line 3b is formed below the data line 6a and the region where the capacitance line 3b is formed along the scanning line 3a are formed from the semiconductor layer 1a constituting the pixel switching TFT 30. An extended first storage capacitor electrode 1f is formed. Then, the thermal oxide film (silicon oxide film) 206d shown in FIG.
[0052]
Then, as shown in FIG. 8A, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a, and a dopant 302 of a group V element such as P (phosphorus) is added to the P-channel semiconductor layer 1a. Doping is performed at a low concentration (for example, P ions are doped at an acceleration voltage of 70 keV and a dose of 2 × 10 ¹¹ / cm ² ).
Next, as shown in FIG. 8B, a resist film is formed at a position corresponding to the P-channel semiconductor layer 1a (not shown), and a group III element such as B (boron) is formed on the N-channel semiconductor layer 1a. Is doped at a low concentration (for example, B ions at an acceleration voltage of 35 keV and a dose of 1 × 10 ¹² / cm ² ).
[0053]
Next, as shown in FIG. 8C, a resist film 305 is formed on the surface of the substrate 10 excluding the end of the channel region 1a 'of each semiconductor layer 1a for each of the P channel and the N channel. The dopant 306 of a group V element such as P having a dose of about 1 to 10 times that of the step shown in FIG. 8A and the dose of about 1 to 10 times that of the step shown in FIG. Of a group III element such as B.
Next, as shown in FIG. 8D, in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, a portion other than the first storage capacitor electrode 1f on the surface of the substrate body 10A is provided. A resist film 307 (which is wider than the scanning line 3a) is formed in a corresponding portion, and using this as a mask, a dopant 308 of a group V element such as P is applied at a low concentration (for example, P ions are accelerated at 70 keV). Doping at a voltage of 3 × 10 ¹⁴ / cm ² ).
[0054]
Next, as shown in FIG. 9A, a contact hole 13 reaching the light shielding layer 11a is formed in the first interlayer insulating film 12 by dry etching such as reactive ion etching (RIE) or by wet etching. At this time, there is an advantage that opening the contact hole 13 or the like by anisotropic etching such as reactive etching or reactive ion beam etching can make the opening shape almost the same as the mask shape. However, if the dry etching and the wet etching are performed in combination, the contact holes 13 and the like can be tapered, so that there is an advantage that disconnection during wiring connection can be prevented.
[0055]
Next, as shown in FIG. 9B, a polysilicon layer 3 is deposited to a thickness of about 350 nm by a low-pressure CVD method or the like, and then the polysilicon film 3 is made conductive by thermally diffusing phosphorus (P). I do. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. Thereby, the conductivity of the polysilicon layer 3 can be increased. Further, in order to enhance the conductivity of the polysilicon layer 3, a single metal, alloy, metal silicide, or the like containing at least one of Ti, W, Co, and Mo is formed on the polysilicon layer 3 by a sputtering method. For example, a layer structure deposited to a thickness of, for example, 150 to 200 nm by a CVD method, an electron beam heating evaporation method, or the like may be used.
Next, as shown in FIG. 9C, the capacitor lines 3b are formed together with the scanning lines 3a having the predetermined pattern shown in FIG. 2 by a photolithography process using a resist mask, an etching process, or the like. After that, the polysilicon remaining on the back surface of the substrate body 10A is removed by covering the surface of the substrate body 10A with a resist film and etching.
[0056]
Next, as shown in FIG. 9D, in order to form a P-channel LDD region of a driving circuit TFT (not shown) in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is resisted. The film 309 is covered with a gate electrode 3c as a diffusion mask, and a group III element dopant 310 such as B is doped at a low concentration (for example, BF ₂ ions are accelerated at 90 keV at an acceleration voltage of 3 × 10 ¹³ / cm ^{2 at} a dose of 3 × 10 ¹³ / cm ² ) ) Doping to form a lightly doped P-channel source region (not shown) and a lightly doped drain region (not shown).
[0057]
Subsequently, as shown in FIG. 9E, the P-channel high-concentration source region 1d and the high-concentration drain region 1e of the pixel switching TFT 30 and the driving circuit TFT (not shown) are formed in the semiconductor layer 1a. In a state where the position corresponding to the N-channel semiconductor layer 1a is covered with a resist film 309, the resist layer is connected to a P-channel scanning line using a mask (not shown) wider than the scanning line 3a. In the state formed on 3a, a dopant 311 of a group III element such as B is also doped at a high concentration (for example, BF ₂ ions are accelerated at 90 keV at a dose of 2 × 10 ¹⁵ / cm ² ).
[0058]
Next, as shown in FIG. 10A, an N-channel LDD region of a pixel switching TFT 30 and a driving circuit TFT (not shown) is formed in the semiconductor layer 1a, so that it corresponds to the P-channel semiconductor layer 1a. Is covered with a resist film (not shown), and using the scanning line 3a (gate electrode) as a diffusion mask, a dopant 60 of a group V element such as P is used at a low concentration (for example, P ions are accelerated at an accelerating voltage of 70 keV; Doping is performed at a dose of × 10 ¹² / cm ² ) to form an N-channel lightly doped source region 1b and a lightly doped drain region 1c.
[0059]
Subsequently, as shown in FIG. 10B, the N-channel high-concentration source region 1d and the high-concentration drain region 1e of the pixel switching TFT 30 and the driving circuit TFT (not shown) are formed in the semiconductor layer 1a. After a resist 62 is formed on the scanning line 3a corresponding to the N channel with a mask wider than the scanning line 3a, a dopant 61 of a group V element such as P is also applied at a high concentration (for example, P ions of 70 keV are applied). Doping (at an acceleration voltage of 4 × 10 ¹⁵ / cm ² ).
[0060]
Next, as shown in FIG. 10C, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, or the like is formed to cover the capacitance line 3b and the scanning line 3a by, for example, normal pressure or low pressure CVD. A second interlayer insulating film 4 made of a silicon oxide film or the like is formed, and a device D according to the present invention is manufactured. Note that the thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0061]
Thereafter, an interlayer film, various wirings, and the like are formed in the same manner as in the related art, and further, the pixel electrode 9a and the alignment film 16 are formed.
The counter substrate 20 is manufactured in the same manner as in the related art, and a liquid crystal panel is manufactured from the counter substrate 20 and the TFT array substrate 10.
That is, the TFT array substrate 10 and the counter substrate 20 manufactured as described above are bonded together with the sealing material 51 so that the alignment films 16 and 22 face each other. Then, by a method such as a vacuum suction method, a liquid crystal formed by mixing, for example, a plurality of types of nematic liquid crystals is sucked into the space between the two substrates to form a liquid crystal layer 50 having a predetermined thickness. Thereby, a liquid crystal panel having the above structure is obtained.
[0062]
In such a method of manufacturing a composite semiconductor substrate and a method of manufacturing a device, since the peripheral edge of the single crystal silicon layer 206a of the bonded substrate S is removed by dry etching, the wet etching is performed later. Even when a film float T occurs on the peripheral edge of the single crystal silicon substrate 206 due to the processing, the single crystal silicon layer 206a does not exist on the film float T, so that the generation of foreign substances can be suppressed. Therefore, in the manufacturing process of the composite semiconductor substrate W, defects such as a defect due to the generation of the foreign matter are less likely to occur, and a highly reliable composite semiconductor substrate W can be provided. In addition, since the step of removing the peripheral end of the single crystal silicon layer 206a is performed simultaneously with the step of patterning the single crystal silicon layer 206a, the manufacturing process does not become complicated.
[0063]
After the composite semiconductor substrate S is wet-etched in a state where the bonding interface between the substrate body (supporting substrate) 10A and the single crystal silicon substrate (semiconductor substrate) 206 is exposed, the single crystal silicon substrate 206 (See FIGS. 5C to 5D), it is possible to prevent the generation of foreign matter in a later step and to secure a stable yield.
Further, prior to the first wet etching of the bonded substrate S, the peripheral edge of the single crystal silicon substrate 206 is removed by dry etching, so that the single crystal silicon substrate 206 has already been removed before the first wet etching. Even if the film floating T occurs at the peripheral end, the film floating T can be removed by dry etching. Therefore, it is possible to further prevent the generation of foreign matters and secure a stable yield.
Note that, in the present invention, the peripheral edge removing step by the dry etching treatment of the semiconductor substrate 206 as described above is not necessarily required, and at least the peripheral edge removing step of the single crystal silicon layer 206a as described above is performed. The effect of improving the yield can be obtained. Then, by performing a peripheral edge removing step by dry etching of the semiconductor substrate 206, the yield can be further improved.
[0064]
Note that in this embodiment mode, single crystal silicon is used for the semiconductor layer in the present invention; however, polycrystalline silicon or amorphous silicon may be used instead, and a compound semiconductor may be used. May be.
Further, the device to be manufactured is not limited to a TFT or the like in a liquid crystal panel, and can be applied to manufacture of a device including various semiconductor elements.
[0065]
Next, a projection display device will be described as an example of the electronic apparatus of the invention.
FIG. 11 is a schematic configuration diagram illustrating an example of a projection display device including the electro-optical device (liquid crystal panel) illustrated in FIGS. 1 and 2. This projection display device is a so-called three-panel projection liquid crystal display device using three liquid crystal panels.
11, reference numeral 510 denotes a light source, 513, 514 are dichroic mirrors, 515, 516, 517 are reflection mirrors, 518, 519, 520 are relay lenses, 522, 523, 524 are liquid crystal light valves, 525 is a cross dichroic prism, 526 indicates a projection lens system.
[0066]
The light source 510 includes a lamp 511 such as an ultra-high pressure mercury lamp and a reflector 512 that reflects light from the lamp 511. The dichroic mirror 513 that reflects blue light and green light transmits red light of white light from the light source 510 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 517 and enters the red light liquid crystal light valve 522.
[0067]
On the other hand, among the color lights reflected by the dichroic mirror 513, green light is reflected by the dichroic mirror 514 that reflects green light, and is incident on the liquid crystal light valve 523 for green. On the other hand, the blue light also passes through the second dichroic mirror 514. For blue light, a light guide unit 521 including a relay lens system including an entrance lens 518, a relay lens 519, and an exit lens 520 is provided to compensate for a difference in optical path length from green light and red light. The blue light is incident on the liquid crystal light valve for blue light 524 via this.
[0068]
The three color lights modulated by the respective light valves enter the cross dichroic prism 525. This prism has four rectangular prisms bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is projected onto a screen 527 by a projection lens system 526, which is a projection optical system, and an image is enlarged and displayed.
Since such a projection-type liquid crystal display device includes the above-described electro-optical device (liquid crystal device), a stable yield is secured, and a highly reliable electronic device is obtained.
[0069]
Note that the technical scope of the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the spirit of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view of a liquid crystal panel as an example of an electro-optical device according to the invention.
FIG. 2 is a sectional view taken along line AA ′ of FIG. 1;
FIG. 3 is a view showing one manufacturing process of the liquid crystal panel according to the manufacturing method of the present invention.
FIG. 4 is a manufacturing process diagram of the liquid crystal panel following FIG. 3;
FIG. 5 is a manufacturing process diagram of the liquid crystal panel following FIG. 4;
FIG. 6 is a manufacturing process diagram of the liquid crystal panel following FIG. 5;
FIG. 7 is a manufacturing process diagram of the liquid crystal panel following FIG. 6;
FIG. 8 is a manufacturing process diagram of the liquid crystal panel following FIG. 7;
FIG. 9 is a manufacturing process diagram of the liquid crystal panel following FIG. 8;
FIG. 10 is a manufacturing process diagram of the liquid crystal panel following FIG. 9;
FIG. 11 is a configuration diagram of a projection display device.
[Explanation of symbols]
10A: substrate body (supporting substrate), 12: first interlayer insulating film, 80, 81: resist pattern, 206: single crystal silicon substrate (semiconductor substrate), 206a: single crystal silicon layer (semiconductor layer), 206b: oxide film Layer, 208: peripheral end, S: bonded substrate, W: composite semiconductor substrate

Claims (10)

A method of manufacturing a composite semiconductor substrate comprising a semiconductor substrate including a semiconductor layer provided on a support substrate,
Bonding the support substrate and the semiconductor substrate,
Patterning the semiconductor layer after bonding,
In the step of patterning the semiconductor layer, a peripheral edge of the semiconductor layer is removed simultaneously with the patterning. 2. The method according to claim 1, wherein the patterning and peripheral edge removal of the semiconductor layer are performed by the same dry etching process. 3. The composite semiconductor substrate according to claim 1, further comprising a step of removing a peripheral end of the semiconductor substrate after the bonding and before the step of patterning the semiconductor layer. Method. A composite semiconductor substrate obtained by the manufacturing method according to claim 1. Using a composite semiconductor substrate obtained by bonding a semiconductor substrate having a semiconductor layer serving as a device formation layer and a support substrate, and forming a device from the semiconductor layer,
Patterning the semiconductor layer for forming the device;
Wet etching the composite semiconductor substrate after the patterning,
In the step of patterning the semiconductor layer, a peripheral end of the semiconductor layer is removed simultaneously with the patterning. 6. The device manufacturing method according to claim 5, wherein the patterning and the peripheral edge removal of the semiconductor layer are performed by the same dry etching process. 7. The device manufacturing method according to claim 5, further comprising a step of removing a peripheral end of the semiconductor substrate before the step of patterning the semiconductor layer. A device obtained by the manufacturing method according to claim 5. An electro-optical device comprising the device according to claim 8. An electronic apparatus comprising the electro-optical device according to claim 9.

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