JP4366954B2 - Method for manufacturing composite semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a composite semiconductor substrate having an SOI structure. To the law Related.
[0002]
[Prior art]
SOI (Silicon On Insulator) technology, which uses a silicon layer provided on an insulator layer for the formation of a semiconductor device, has an α-ray resistance, a latch-up characteristic, or a short channel suppression effect in a normal single crystal silicon substrate. In order to show excellent characteristics that cannot be achieved, the development of semiconductor devices has been promoted for the purpose of high integration of semiconductor devices.
[0003]
In recent years, an excellent short channel suppression effect has been found by forming a device on an SOI layer thinned to a thickness of 100 nm or less. In addition, the SOI device formed in this way has high reliability due to its excellent radiation resistance, and can increase the speed and power consumption of the element by reducing parasitic capacitance, or can be completely depleted. It has excellent points such as miniaturization of process rules due to the ability to produce field effect transistors.
[0004]
As a method for forming such an SOI structure, there is a method for manufacturing an SOI substrate by bonding single crystal silicon substrates. This method, commonly referred to as a bonding method, is a method in which a single crystal silicon substrate and a support substrate are overlapped via an oxide film, bonded together at room temperature using OH groups on the substrate surface, and then the single crystal silicon substrate is ground. The film is thinned by polishing, polishing, or etching, and subsequently a siloxane bond (Si—O—Si) is formed by heat treatment at about 700 ° C. to 1200 ° C., and the single crystal silicon layer is formed on the supporting substrate by increasing the bonding strength. is there. According to this method, since the single crystal silicon substrate is directly thinned, the silicon thin film has excellent crystallinity, and thus a high-performance device can be manufactured.
[0005]
As an application of this bonding method, hydrogen ions are implanted into a single crystal silicon substrate, bonded to a supporting substrate, and then a thin film silicon layer is formed on the single crystal silicon substrate by heat treatment at about 400 to 600 ° C. Separated from the hydrogen injection region, and then increased the bonding strength by a heat treatment up to about 1100 ° C., or epitaxially grown a single crystal silicon layer on a porous silicon substrate and bonded it to a support substrate A method of forming an epitaxial single crystal silicon thin film on a supporting substrate by removing the silicon substrate and etching the porous silicon layer later is known.
[0006]
An SOI substrate by a bonding method can be used for manufacturing various devices in the same manner as a normal bulk semiconductor substrate (semiconductor integrated circuit). On the other hand, the difference from the conventional bulk substrate is that various materials can be used for the support substrate. That is, as the supporting substrate, not only a normal silicon substrate but also a translucent quartz substrate or a glass substrate can be used. Therefore, by forming a single-crystal silicon thin film on a light-transmitting substrate, even in a device that requires light transmission, for example, an electro-optical device such as a transmission-type liquid crystal device, A high-performance transistor element can be formed using a single crystal silicon layer that is excellent in the above. That is, by forming a pixel switching MIS type transistor for driving a pixel electrode or a driving circuit MIS type transistor constituting a driving circuit in a peripheral region of the image display region in an SOI layer which is a single crystal silicon layer, fine display can be achieved. And speeding up can be achieved.
[0007]
Here, when an SOI substrate is used for an electro-optical device such as a transmissive liquid crystal device, the thermal expansion coefficient of the SOI layer is different from that of the light-transmitting substrate such as a quartz substrate that is a support substrate. In the heat treatment process or thermal oxidation process for increasing the thermal stress due to the difference in thermal expansion coefficient, as a result, slip, dislocation, lattice defect, HF defect, etc. are formed in the single crystal semiconductor layer (SOI layer), There is a risk of hindering device characteristics.
[0008]
As a technique for dealing with thermal stress due to such a difference in thermal expansion coefficient, a technique in which a stress relaxation layer is provided between a semiconductor single crystal region and a glass material to reduce warpage of the substrate or the like has been known ( For example, see Patent Document 1).
In addition, in order to prevent thermal stress at the time of bonding from remaining in the single crystal semiconductor layer (single crystal silicon layer), an island silicon layer is formed by patterning the single crystal silicon thin film. A technique for performing thermal oxidation treatment on a layer is known (see, for example, Patent Document 2).
Furthermore, a technique is known in which a part of a single crystal semiconductor substrate is changed into a porous layer by anodic oxidation, and this porous layer is used as a stress relaxation layer (see, for example, Patent Document 3).
[0009]
[Patent Document 1]
JP-A-7-142570
[Patent Document 2]
JP 2000-12864 A
[Patent Document 3]
JP 2000-106424 A
[0010]
[Problems to be solved by the invention]
However, in the technique of providing the stress relaxation layer between the semiconductor single crystal region and the glass material, the formed stress relaxation layer cannot be removed, and the stress relaxation layer is colored and non-transparent. Therefore, for example, there is a problem that a transmissive liquid crystal device cannot be manufactured from the obtained composite semiconductor substrate.
[0011]
In the technique of performing thermal oxidation treatment on the island-shaped silicon layer, particularly when sacrificial oxidation is performed in order to reduce the thickness of the silicon layer, and then the sacrificial oxide layer is removed by wet etching, the wet etching solution is used for the island-shaped silicon layer. There is a possibility that the underlying insulating layer of the silicon layer is dissolved between the layers and reaches the bonding interface with the support substrate. Thus, when the wet etching solution reaches the bonding interface, it causes inconveniences such as peeling at the bonding interface. For example, a transmission type liquid crystal device (light When a bulb is manufactured, display defects occur due to peeling of the bonding interface.
[0012]
In the technique using the porous layer as the stress relaxation layer, as described above, hydrogen ions are implanted in advance to reduce the thickness of the single crystal silicon layer after bonding, and the thin film silicon layer is formed on the single crystal silicon substrate by heat treatment. At the time of separation from the hydrogen implantation region, there is a possibility that the separation is not satisfactorily performed because the profile of hydrogen ion implantation is different between the single crystal silicon layer and the porous layer. In addition, the single crystal silicon substrate thus separated is usually used as it is for another SOI substrate fabrication, but in this technique, the single crystal silicon substrate remains on the single crystal silicon substrate after the porous layer is separated. This cannot be used directly. In addition, when the silicon oxide layer for bonding is formed, a difference in film quality occurs between the silicon oxide layer formed from the single crystal silicon layer and the silicon oxide layer formed from the porous layer, which causes the bonding. There may be unevenness in the alignment.
[0013]
The present invention has been made in view of the above circumstances, and its purpose is to reduce thermal stress generated in a heat treatment step or the like for increasing the bonding strength to slip or dislocations, lattice defects in the single crystal semiconductor layer, HF defects and the like can be prevented, and can be applied to the manufacture of transmissive liquid crystal devices. In this case, display defects can be prevented, and uneven bonding can occur. Manufacturing method of composite semiconductor substrate The law It is to provide.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a composite semiconductor substrate according to the present invention is a method for manufacturing a composite semiconductor substrate in which a semiconductor substrate having a single crystal semiconductor layer is bonded onto a support substrate, A step of bonding the semiconductor substrate to a bonded substrate, a step of thinning a predetermined region of the single crystal semiconductor layer in the bonded substrate by etching, and a bonded substrate after the predetermined region is thinned And a step of heat-treating.
According to this method for manufacturing a composite semiconductor substrate, a predetermined region of the single crystal semiconductor layer in the bonded substrate is thinned by etching, and then heat treatment is performed. Therefore, the bonding strength can be improved by the heat treatment. Of course, at that time, the stress is easily concentrated on the thinned portion of the single crystal semiconductor layer, so that the thinned portion functions as a stress relaxation layer, and therefore, the region other than the predetermined region. Slip, dislocation, lattice defect, HF defect and the like are prevented from being formed in the single crystal semiconductor layer.
In addition, when a predetermined region of the single crystal semiconductor layer is thinned by etching, even if wet etching is employed, the thinned single crystal semiconductor layer remains as it is, so that the etching solution penetrates to the bonding interface. Therefore, inconveniences such as peeling at the bonding interface are prevented.
[0015]
Further, in the method of manufacturing the composite semiconductor substrate, between the step of bonding the supporting substrate and the semiconductor substrate to form a bonded substrate, and the step of thinning the predetermined region in the bonded substrate by etching. It is preferable that the method further includes a step of thinning the single crystal semiconductor layer by separating the semiconductor substrate of the bonded substrate in the thickness direction.
In this case, when the single crystal semiconductor layer is thinned by separating the semiconductor substrate in the bonded substrate in the thickness direction, the single crystal semiconductor layer before thinning has a porous layer or the like. Since it is not provided, the separated single crystal semiconductor substrate can be used as it is for another composite semiconductor substrate (SOI substrate). In addition, when an oxide layer for bonding is formed on the semiconductor substrate, the single crystal semiconductor layer is not provided with a porous layer or the like, so that an oxide layer formed from the single crystal semiconductor layer and a porous layer are formed. Occurrence of uneven bonding due to the difference in film quality between the oxide layer and the oxide layer is also prevented.
[0016]
The method for manufacturing a composite semiconductor substrate further includes a thermal oxidation step of thermally oxidizing the single crystal semiconductor layer in the bonded substrate after the step of heat-treating the bonded substrate, and the single crystal semiconductor layer The thinning of the predetermined region is preferably performed so that the thickness of the thinned single crystal semiconductor layer of the predetermined region is completely consumed by the thermal oxidation step.
In this way, by removing the thermal oxide film formed by the thermal oxidation process by etching, the portion previously thinned by etching in the predetermined region can be removed as it is. Therefore, for example, the process of forming a single crystal semiconductor pattern formed in the element formation region can be omitted, and the process can be simplified.
[0017]
In the method of manufacturing the composite semiconductor substrate, in the step of thinning the single crystal semiconductor layer in the bonded substrate by etching, a region other than a region where an element is formed in the single crystal semiconductor layer is thin. It is preferable that
In this case, as described above, since the stress is easily concentrated on the thinned portion of the single crystal semiconductor layer, the thinned portion functions as a stress relaxation layer. Slip, dislocation, lattice defect, HF defect, or the like is prevented from being formed in the single crystal semiconductor layer in the region where the film is formed.
[0018]
In the method for manufacturing the composite semiconductor substrate, it is preferable that the bonded substrate after the thickness of the predetermined region is heat-treated in a range of 700 ° C. or more and 1200 ° C. or less.
In this way, the bonding strength in the bonded substrate can be sufficiently increased by this heat treatment.
[0019]
In the method for manufacturing the composite semiconductor substrate, the single crystal semiconductor layer is preferably made of single crystal silicon.
In this way, since the single crystal semiconductor layer is made of general single crystal silicon, the composite semiconductor substrate can be manufactured at a lower cost than when other single crystal semiconductor layers are used.
[0020]
Moreover, in the manufacturing method of the said composite semiconductor substrate, it is preferable that the said support substrate is a translucent board | substrate.
In this way, for example, a transmissive liquid crystal device (light valve) can be manufactured from the obtained composite semiconductor substrate.
[0021]
The composite semiconductor substrate of the present invention is obtained by any one of the manufacturing methods described above.
According to this composite semiconductor substrate, slips, dislocations, lattice defects, HF defects, and the like are prevented from being formed in the single crystal semiconductor layer. For example, the single crystal semiconductor layer is formed in a semiconductor element such as a thin film transistor. It will be good and reliable.
[0022]
The electro-optical device according to the present invention includes the composite semiconductor substrate.
According to this electro-optical device, for example, the electro-optical device itself is good and highly reliable by having the above-described good and reliable semiconductor element.
[0023]
The electronic apparatus according to the present invention includes the electro-optical device.
According to this electronic apparatus, the electronic apparatus itself is also good and highly reliable by including the good and highly reliable electro-optical device.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
1 to 3 are process cross-sectional views illustrating a method for manufacturing a composite semiconductor substrate (bonded substrate) having an SOI structure according to Embodiment 1 of the present invention.
[0025]
In this embodiment mode, first, as shown in FIG. 1A, a single crystal silicon substrate (semiconductor substrate) 200 having a thickness of, for example, 750 μm is prepared, and then a first surface 201 and a second surface 202 are prepared. A silicon oxide film (insulating layer) 210 is formed on the entire surface of at least the first surface 201. The silicon oxide film 210 may be thicker than the thickness at which the first surface 201 becomes hydrophilic in the bonding step described later, but is formed to be approximately 200 nm in this example.
[0026]
Next, as shown in FIG. 1B, hydrogen ions are implanted into the single crystal silicon substrate 200 over which the silicon oxide film 210 is formed from the first surface 201 side. As a result, an ion implantation layer having a penetration depth distribution as shown by a broken line in FIG. 1B is formed inside the single crystal silicon substrate 200. As ion implantation conditions at this time, for example, the acceleration energy is 60 to 150 keV, and the dose is 5 × 10. ¹⁶ cm ^-2 -10x10 ¹⁶ cm ^-2 And
[0027]
Next, as shown in FIG. 1C, a support substrate 500 is prepared. Subsequently, a silicon oxide film, NSG (non-doped silicate glass) or the like is formed on the entire surface of the support substrate 500 by sputtering, CVD, or the like. An oxide film (insulating layer) 510 is formed. Next, the surface of the oxide film 510 is polished and flattened by a CMP method or the like. Here, the thickness of the oxide film 510 is, for example, about 400 to 1000 nm, more preferably about 800 nm. The support substrate 500 is made of SiO such as quartz. ₂ In the case of using a substrate containing as a main component, the step of forming the oxide film 510 can be omitted.
[0028]
Here, the oxide films (insulating layers) 210 and 510 are formed to ensure adhesion between the single crystal silicon substrate (semiconductor substrate) 200 and the support substrate 500. As the support substrate 500, a substrate (a transparent substrate) made of a transparent material such as glass or quartz can be used. In that case, the obtained composite semiconductor substrate can be applied to a transmissive electro-optical device such as a transmissive liquid crystal device (light valve).
[0029]
Next, as illustrated in FIG. 1D, the surface 501 of the single crystal silicon substrate 200 on the oxide film 510 side and the surface of the support substrate 500 on the silicon oxide film 210 side are bonded to form oxide films 210 and 510. Then, the single crystal substrate 200 is bonded to the supporting substrate 500 at a room temperature to about 200 ° C. Then, due to the action of OH groups on the substrate surface, the single crystal silicon layer 220 and the supporting substrate 500 are bonded to each other through the insulating layer 550 (oxide films 210 and 510) as shown in FIG. A semiconductor substrate (bonded substrate) 600 is formed.
[0030]
Here, for the single crystal silicon substrate 200 in the composite semiconductor substrate 600 after bonding, the single crystal silicon layer is thinned to, for example, about 200 nm to form the single crystal silicon layer 220 illustrated in FIG. The single crystal silicon layer 220 is formed by separating and cutting the single crystal silicon substrate 200 at the position of the ion implantation layer by heat treatment at a low temperature of, for example, 400 ° C. to 600 ° C. This separation / cutting phenomenon occurs because the bonds of the semiconductor crystal are broken by the ions introduced into the single crystal silicon substrate 200, and becomes more prominent at the peak position of the ion concentration in the ion implantation layer. Therefore, the position where the separation is cut by the heat treatment is the same as the peak position of the ion concentration. Note that since the surface of the single crystal silicon layer 220 exposed by the above-described separation and cutting has irregularities of about several nm, the surface is smoothed by a CMP method or by a hydrogen annealing method in which heat treatment is performed in a hydrogen atmosphere. It is preferable to smooth the surface. Further, the single crystal silicon substrate 200 after being separated in this way can be used as it is for another SOI substrate fabrication.
[0031]
Alternatively, a film of molybdenum, tungsten, or the like may be formed on the lower surface side of the oxide film 510 on the surface of the support substrate 500. Since such a film functions as, for example, a heat conductive film, the temperature distribution of the support substrate 500 can be improved. Therefore, for example, in the step of bonding the support substrate 500 and the single crystal silicon substrate 200, the temperature distribution of the bonding interface can be made uniform by this thermal conductive film, and thus the bonding at this interface can be performed. It can be made uniform and the bonding strength can be improved. Further, when used in a transmissive liquid crystal device or the like, a film of molybdenum, tungsten, or the like can function as a light-blocking layer. In addition to the materials listed above, materials that can be used for such films include refractory metals such as tantalum, cobalt, and titanium, alloys containing them, or polycrystalline silicon, tungsten silicide, molybdenum silicide, and the like. A typical silicide film or the like can be used.
[0032]
Subsequently, a resist layer is formed on the single crystal silicon layer 220, and exposure / development processing is performed to expose the element non-formation region 230 of the single crystal silicon layer 220 as shown in FIG. A resist pattern 610 is formed. Here, the element non-formation region is a region in the single crystal silicon layer 220 where an active element, for example, a switching element, a logic circuit, a MEMS (Micro Electro Mechanical Systems) element, or the like is not formed, and is etched away in a later process. It is an area.
[0033]
However, in this step, as shown in FIG. 2A, the entire portion of the non-element formation region 230 is not exposed, and a portion in contact with the element formation region 240, for example, a boundary with the element formation region 240 has a width of about 1 μm. The portion is covered with the resist pattern 610 without exposing it. This is to provide a margin when the single crystal silicon layer 220 in the non-element formation region 230 is thinned using the resist pattern 610 as a mask as will be described later.
[0034]
After the resist pattern 610 is formed in this way, the exposed element non-formation region 230 is etched and thinned using the resist pattern 610 as a mask as shown in FIG. The etching for thinning may be performed by wet etching or dry etching, but in this example, wet etching using an etching solution such as KOH or TMAH (tetramethylammonium hydroxide) as an etching solution. It shall be done in
[0035]
When wet etching is employed, side etching is expected to occur to some extent. As described above, a margin is provided in the resist pattern 610, and the resist pattern 610 reaches the element non-formation region 230 in the vicinity of the boundary with the element formation region 240. The covering prevents the element formation region 240 from being etched even if side etching occurs.
The single crystal silicon layer 220 is etched by simply thinning it, and the entire thickness is not etched away. Therefore, the thin single crystal silicon layer 220a remains as it is. Therefore, inconveniences such as peeling at the bonding interface are prevented.
[0036]
In the case of this example, the thickness of the single crystal silicon layer 220 is about 200 nm and the thickness of the silicon oxide film 210 is about 200 nm as described above with respect to the degree of thinning, that is, the depth to be thinned by etching. Furthermore, the thickness of the single crystal silicon layer 220a thinned by 50 nm or more and less than 150 nm is set to about 150 nm to 50 nm. Here, such etching for thinning is performed by managing the time based on the etching rate obtained in advance by experiments or the like.
The reason why the depth of thinning is 50 nm or more and the thickness of the thinned single crystal silicon layer 220a is 150 nm or less is that the single crystal silicon layer 220 in the element formation region 240 is subjected to sacrificial oxidation and etching treatment as will be described later. This is because the thickness is reduced to a desired thickness, in this example, about 50 nm.
[0037]
In order to make the single crystal silicon layer 220 having a thickness of 200 nm into a thickness of 50 nm by the sacrificial oxidation and etching process, it is necessary to sacrificate the thickness of 150 nm and further remove it by etching. At this time, if the thickness of the thinned single crystal silicon layer 220a in the element non-formation region 230 is 150 nm or less, the entire thickness is consumed by sacrificial oxidation (thermal oxidation), and therefore by subsequent etching. This is because the sacrificial oxide film (thermal oxide film) can be removed by etching, thereby making it possible to omit, for example, the step of forming a single crystal silicon pattern formed in the element formation region 240.
Note that if the difference in thickness from the non-thinned single crystal silicon layer 220 is less than 50 nm, the function of the thinned single crystal silicon layer 220a as a stress relaxation layer described later may not be sufficiently exhibited.
[0038]
On the other hand, when the thickness of the thinned single crystal silicon layer 220a is less than 50 nm, the thickness of the thinned single crystal silicon layer 220a is 50 nm or more. When the single crystal silicon layer 220 in the region 240 is subjected to sacrificial oxidation and etching to a desired thickness of about 50 nm in this example, not only the oxide layer formed from the thinned single crystal silicon layer 220a but also the lower layer thereof. This is because the entire thickness of the silicon oxide film 210 which is the base layer is etched. That is, when the silicon oxide film 210 is etched to the full thickness in this way, particularly when wet etching is employed as the etching, the etching solution penetrates to the bonding interface and peeling occurs at the bonding interface. Because there is a fear.
[0039]
When the element non-formation region 230 of the single crystal silicon layer 220 is thus thinned to form the thin single crystal silicon layer 220a, the resist pattern 610 is removed as shown in FIG. The semiconductor substrate (bonded substrate) 600 is preferably heat-treated in a temperature range of 700 ° C. or higher and 1200 ° C. or lower to improve the bonding strength. When such heat treatment is performed, hydrogen (H) present at the bonding interface between the oxide films 210 and 510 of the composite semiconductor substrate 600 is volatilized by this heat treatment to cause Si—O—Si bonding, thereby bonding. Interfacial adhesion can be increased.
[0040]
Although it does not specifically limit about this heat processing, For example, it can carry out with a general heating apparatus (baking apparatus). In that case, the temperature in the heating device may be adjusted in advance to 700 ° C. or more and 1200 ° C. or less, and the composite semiconductor substrate (bonded substrate) 600 may be put therein to perform heat treatment. May be set to a temperature lower than 700 ° C., for example, a low temperature of about 200 ° C. to 400 ° C., and the composite semiconductor substrate 600 may be put therein, and then the temperature is raised to 700 ° C. or higher to perform heat treatment. In this way, it is possible to prevent excessive thermal stress from being generated in the composite semiconductor substrate 600 by performing heat treatment from room temperature suddenly at high temperature. In addition, about the heat processing here, it may replace with the heating by the said heating apparatus, and may employ | adopt a laser annealing method.
[0041]
When the heat treatment is performed in this manner, the single crystal silicon substrate 200 (single crystal silicon layer 220) and the support substrate 500 are made of different materials, and therefore usually there is a difference in thermal expansion coefficient between them. Stress is generated. In the present embodiment, since the single crystal silicon layer 220 is partially thinned first, the thin portion 220a can function as a stress relaxation layer. Formation of slips, dislocations, lattice defects, HF defects, and the like in the formation region 240 can be prevented.
[0042]
Next, as described above, the single crystal silicon layer 220 is thermally oxidized (sacrificial oxidation) so as to have a desired thickness (about 50 nm in this example) by the sacrificial oxidation method. As shown in FIG. 4B, the upper portion of the single crystal silicon layer 220 is formed into a thermal oxide film 225 having a thickness of about 300 nm (250 nm to 350 nm). At this time, since the thickness of the thinned single crystal silicon layer 220a is set to about 150 nm to 50 nm, the entire thickness of the thinned single crystal silicon layer 220a is consumed by thermal oxidation as described above. An oxide film 225 is formed.
[0043]
Next, as shown in FIG. 3B, the thermal oxide film 225 formed by this thermal oxidation is removed by etching to form a single crystal silicon layer 220b having a desired thickness.
In the etching of the thermal oxide film 225, dry etching such as reactive ion etching (RIE) is employed in the previous period in order to increase the etching speed and shorten the processing time, and in the latter period, the underlying layer of the thermal oxide film 225 is used. It is preferable to employ wet etching so that a single crystal silicon layer 220 is not damaged. Here, as described above, the thickness of the thinned single crystal silicon layer 220a is the total thickness of the thermal oxide film 225, and the silicon oxide film 210 having a thickness of about 200 nm is present on the base side. Even if wet etching is used for the later etching removal of the thermal oxide film 225, the entire thickness of the silicon oxide film 210 is etched, the etching solution penetrates to the bonding interface, and peeling occurs at the bonding interface. Absent.
[0044]
When the single crystal silicon layer 220b has a desired thickness in this way, in this example, as described above, the single crystal silicon layer 220 in the element non-formation region 230 is not all thinned, and therefore a portion thereof is made of single crystal silicon. Since the layer 220b remains, a resist pattern 620 that covers only the element formation region 240 of the single crystal silicon layer 220b is first formed as shown in FIG. 3C in order to remove the layer 220b. Subsequently, using this as a mask, the single crystal silicon layer 220b in the element non-formation region 230 is removed by etching, and the resist pattern 620 is removed as shown in FIG. 3D, and the single crystal silicon pattern is formed in the element formation region 240. 220c is formed. Here, with respect to the etching of the single crystal silicon layer 220b in the element non-forming region 230, it is preferable to employ wet etching so that the single crystal silicon pattern 220c to be formed is not damaged.
[0045]
When the single crystal silicon layer 220b in the element non-formation region 230 is removed by etching in this way, the single crystal silicon layer 220a in the thinned portion particularly in the heat treatment step functions as a stress relaxation layer, and therefore FIG. Since stress tends to concentrate on the shoulder portion 230a of the non-thinned single crystal silicon layer 220 shown in FIG. 3C, it can be obtained by removing this portion as shown in FIG. The single crystal silicon pattern 220c is a good single crystal silicon layer free from damage due to stress. That is, the single crystal silicon pattern 220c formed in the element formation region 240 is free of slip, dislocation, lattice defect, HF defect, etc. as described above, and is a good single crystal silicon layer free from damage. It has become.
[0046]
As described above, according to the present embodiment, the element non-forming region 230 of the single crystal silicon layer 220 in the composite semiconductor substrate (bonded substrate) 600 is thinned by etching, and then the bonding strength is improved. Since the heat treatment is performed, the bonding strength can be improved by this heat treatment, and in this case, the thinned portion 220a functions as a stress relaxation layer, and thus the obtained single crystal silicon pattern. The formation of slips, dislocations, lattice defects, HF defects, etc. in 220c is prevented.
[0047]
In the above embodiment, as shown in FIG. 2A, the resist pattern 610 is formed with a margin without exposing the entire element non-formation region 230, but the present invention is not limited to this. The resist pattern 610 is formed so as to expose the entire element non-formation region 230 and cover the entire element formation region 240 without taking a margin, and using this as a mask, the single crystal silicon layer 220 is formed. May be etched. At this time, as the etching, either wet etching or dry etching can be employed, but it is preferable to use dry etching with higher patterning accuracy.
[0048]
This eliminates the need for the etching removal step of the single crystal silicon layer 220b in the non-element formation region 230 shown in FIGS. 3C and 3D. Therefore, as described above, the thin film element is not formed. Patterning for forming the single crystal silicon pattern 220c formed in the element formation region 240 is performed by setting the thickness of the single crystal silicon layer 220a in the region 230 to a thickness that can be consumed by the subsequent thermal oxidation. The process can be omitted, and the process can be simplified.
[0049]
In the above-described embodiment, at least a part of the insulating layer 550 flows during heat treatment of at least 1200 ° C. such as PSG (phosphorus silicate glass), BSG (boron silicate glass), and BPSG (boron phosphorus silicate glass). A layer having property or elasticity may be formed. BPSG generally used in semiconductor processes has fluidity at 850 ° C. or higher. Depending on the concentrations of B and P, fluidity can be imparted from 700 ° C. Since the fluid stress layer further relaxes the thermal stress, it is suitable for a composite semiconductor substrate (SOI substrate) having a different thermal expansion coefficient. Note that when PSG, BSG, and BPSG are applied to the fluid layer, a protective layer such as a silicon nitride film is used as the fluid layer so as not to adversely affect the semiconductor element formed in the single crystal silicon pattern 220b. It is preferable to provide in the upper part.
[0050]
[Embodiment 2]
The method described in the first embodiment can be applied to the manufacture of various semiconductor devices. Therefore, in this embodiment, an example in which an active matrix substrate (semiconductor device) of a liquid crystal device (electro-optical device) is configured using the composite semiconductor substrate (bonded substrate) 600 described in Embodiment 1 will be described.
[0051]
(Overall configuration of liquid crystal device)
4 is a plan view of the liquid crystal device as viewed from the side of the counter substrate together with the components formed thereon, and FIG. 5 is a cross-sectional view taken along line HH ′ of FIG. 4 including the counter substrate. . In FIG. 4, a sealing material 52 is provided along the edge on the active matrix substrate 10 of the liquid crystal device 100, and a frame 53 made of a light-shielding material is formed in the inner region. A data line driving circuit 101 and an external input terminal 102 are provided along one side of the active matrix substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 is provided on two sides adjacent to the one side. Are formed along.
[0052]
Needless to say, if the delay of the scanning signal supplied to the scanning line is not a problem, the scanning line driving circuit 104 may be provided on only one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a. For example, the odd-numbered data lines supply an image signal from a data line driving circuit disposed along one side of the image display area 10a, and the even-numbered data lines are on the opposite side of the image display area 10a. An image signal may be supplied from a data line driving circuit arranged along the line. If the data lines are driven in a comb-like shape in this way, the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured. Further, the remaining side of the active matrix substrate 10 is provided with a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display region 10a. In some cases, a precharge circuit or an inspection circuit is provided. Further, at least one corner of the counter substrate 20 is formed with a vertical conductive material 106 for electrical conduction between the active matrix substrate 10 and the counter substrate 20.
[0053]
As shown in FIG. 5, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 4 is fixed to the active matrix substrate 10 by the sealing material 52. The sealing material 52 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the active matrix substrate 10 and the counter substrate 20 around them, and the distance between the substrates is set to a predetermined value. Gap materials such as glass fiber or glass beads are blended.
[0054]
As will be described in detail later, pixel electrodes 9 a are formed in a matrix on the active matrix substrate 10. On the other hand, the counter substrate 20 has a light shielding film 23 called a black matrix or a black stripe in a region facing vertical and horizontal boundary regions of pixel electrodes (described later) formed on the active matrix substrate 10. A counter electrode 21 made of an ITO film is formed on the upper layer side.
[0055]
The liquid crystal device thus formed is used, for example, in a projection type liquid crystal display device (liquid crystal projector) described later. In this case, the three liquid crystal devices 100 are respectively used as RGB light valves, and each liquid crystal device 100 receives light of each color as a projection light through a dichroic mirror for RGB color separation. It will be incident. Therefore, the color filter is not formed in the liquid crystal device 100 of each embodiment described above.
[0056]
However, by forming an RGB color filter together with its protective film in a region facing each pixel electrode 9a in the counter substrate 20, in addition to the projection type liquid crystal display device, a mobile computer, a cellular phone, a liquid crystal television, etc., which will be described later It can be used as a color liquid crystal display device for electronic equipment.
[0057]
Further, by forming a microlens on the counter substrate 20 so as to correspond to each pixel, the light collection efficiency of incident light with respect to the pixel electrode 9a can be increased, so that bright display can be performed. Furthermore, a dichroic filter that produces RGB colors using the interference action of light may be formed by stacking multiple layers of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, brighter color display can be performed.
[0058]
(Configuration and operation of liquid crystal device 100)
Next, the electrical configuration and operation of an active matrix liquid crystal device (electro-optical device) will be described with reference to FIGS.
[0059]
FIG. 6 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels formed in a matrix to form the image display region 10a of the liquid crystal device 100. FIG. FIG. 7 is a plan view of adjacent pixels on an active matrix substrate on which data lines, scanning lines, pixel electrodes and the like are formed. FIG. 8 is an explanatory diagram showing a cross section at a position corresponding to the line AA ′ in FIG. 7 and a cross section in a state where liquid crystal as an electro-optical material is sealed between the active matrix substrate and the counter substrate. In these drawings, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.
[0060]
In FIG. 6, in the image display area 10a of the liquid crystal device 100, a pixel electrode 9a and a pixel switching MIS transistor 30 for controlling the pixel electrode 9a are provided in each of a plurality of pixels formed in a matrix. The data line 6 a that is formed and supplies a pixel signal is electrically connected to the source of the MIS transistor 30. Pixel signals S1, S2,... Sn written to the data line 6a are supplied line-sequentially in this order. Further, the scanning line 3a is electrically connected to the gate of the MIS transistor 30, and the scanning signals G1, G2,... Gm are pulse-sequentially applied to the scanning line 3a in this order at a predetermined timing. It is comprised so that it may apply. The pixel electrode 9a is electrically connected to the drain of the MIS transistor 30, and the pixel signal S1 supplied from the data line 6a is turned on by turning on the MIS transistor 30 as a switching element for a certain period. , S2... Sn are written to each pixel at a predetermined timing. In this way, the pixel signals S1, S2,... Sn at a predetermined level written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode formed on a counter substrate described later.
[0061]
Here, in order to prevent the held pixel signal from leaking, a storage capacitor 70 (capacitor) may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. As a result, a charge retention characteristic is improved, and a liquid crystal device capable of performing display with a high contrast ratio can be realized. As a method of forming the storage capacitor 70, there is either a case where it is formed between the capacitor line 3b, which is a wiring for forming a capacitor, or a case where it is formed between the storage line 70 and the preceding scanning line 3a. Also good.
[0062]
In FIG. 7, on the active matrix substrate 10 of the liquid crystal device 100, a plurality of transparent pixel electrodes 9a (regions surrounded by dotted lines) are formed in a matrix for each pixel, and vertical and horizontal boundary regions of the pixel electrodes 9a are formed. A data line 6a (shown by an alternate long and short dash line), a scanning line 3a (shown by a solid line), and a capacitor line 3b (shown by a solid line) are formed.
As shown in FIG. 8, the liquid crystal device 100 includes an active matrix substrate 10 and a counter substrate 20 disposed to face the active matrix substrate 10.
[0063]
In this embodiment, the base of the active matrix substrate 10 is a bonded substrate (composite semiconductor substrate) 600 described later, and the base of the counter substrate 20 is a transparent substrate 20b such as a quartz substrate or a heat-resistant glass plate. A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is formed on the upper side. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is formed by performing a rubbing process on an organic thin film such as a polyimide thin film. In the counter substrate 20, an alignment film 22 made of a polyimide film is also formed on the upper layer side of the counter electrode 21, and this alignment film 22 is also a film obtained by rubbing the polyimide film.
[0064]
In the image display region 10 a of the active matrix substrate 10, a pixel switching MIS transistor 30 that controls switching of each pixel electrode 9 a is formed at a position adjacent to each pixel electrode 9 a. In the bonded substrate 600, a light shielding film 11a made of a chromium film or the like is formed in a region overlapping the MIS transistor 30 in a planar manner. An interlayer insulating film 12 is formed on the surface side of the light shielding film 11a, and a MIS transistor 30 is formed on the surface side of the interlayer insulating film 12. That is, the interlayer insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the MIS transistor 30 from the light shielding film 11a.
[0065]
As shown in FIGS. 7 and 8, the MIS transistor 30 for pixel switching has an LDD (Lightly Doped Drain) structure, and a channel is formed in the semiconductor layer 1a by an electric field from the scanning line 3a. A channel region 1a ′, a low concentration source region 1b, a low concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e are formed. A gate insulating film 2 for insulating the semiconductor layer 1a and the scanning line 3a is formed on the upper side of the semiconductor layer 1a.
Here, the semiconductor layer 1a is composed of the single crystal silicon layer 220b formed by the method described above.
[0066]
Interlayer insulating films 4 and 7 made of a silicon oxide film are formed on the surface side of the MIS transistor 30 configured as described above. A data line 6 a is formed on the surface of the interlayer insulating film 4, and the data line 6 a is electrically connected to the high concentration source region 1 d through a contact hole formed in the interlayer insulating film 4. A pixel electrode 9 a made of an ITO film is formed on the surface of the interlayer insulating film 7. The pixel electrode 9 a is electrically connected to the high-concentration drain region 1 e through contact holes formed in the interlayer insulating films 4 and 7 and the gate insulating film 2. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a. The alignment film 16 is a film obtained by performing a rubbing process on a polyimide film.
[0067]
Further, the extension portion 1f (lower electrode) extending from the high-concentration drain region 1e has a capacitance in the same layer as the scanning line 3a through an insulating film (dielectric film) formed simultaneously with the gate insulating film 2a. The storage capacitor 70 is configured by the line 3b facing as an upper electrode.
[0068]
The MIS transistor 30 preferably has an LDD structure as described above, but has an offset structure in which impurity ions are not implanted into regions corresponding to the low concentration source region 1b and the low concentration drain region 1c. May be. The MIS transistor 30 is a self-aligned TFT in which impurity ions are implanted at a high concentration using a gate electrode (a part of the scanning line 3a) as a mask to form high concentration source and drain regions in a self-aligning manner. May be. In this embodiment, a single gate structure is employed in which only one gate electrode (scanning line 3a) of the MIS transistor 30 is disposed between the source and drain regions. However, two or more gate electrodes are disposed therebetween. May be. At this time, the same signal is applied to each gate electrode. If the MIS transistor 30 is configured with dual gates (double gates) or more than triple gates in this way, leakage current at the junction between the channel and the source-drain region can be prevented, and the current during OFF can be reduced. I can do it. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.
[0069]
The active matrix substrate 10 and the counter substrate 20 thus configured are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and the sealing material 53 (see FIG. 4 and FIG. 4) is disposed between these substrates. A liquid crystal 50 as an electro-optical material is sealed and sandwiched in a space surrounded by (see FIG. 5). The liquid crystal 50 takes a predetermined alignment state by the alignment film in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal 50 is made of, for example, one or a mixture of several types of nematic liquid crystals.
[0070]
In addition, on the light incident side surface or the light emitting side of the counter substrate 20 and the active matrix substrate 10, the type of the liquid crystal 50 to be used, that is, an operation mode such as a TN (twisted nematic) mode, an STN (super TN) mode, etc. Depending on the normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate and the like are arranged in a predetermined direction.
[0071]
(Configuration of drive circuit)
Referring again to FIG. 4, in the liquid crystal device 100 of the present embodiment, the data line driving circuit 101 and the scanning line driving circuit 104 (peripheral circuit) are formed using the peripheral area of the image display area 10a on the surface side of the active matrix substrate 10. Is formed. The data line driving circuit 101 and the scanning line driving circuit 104 are basically composed of an N channel type MIS transistor and a P channel type MIS transistor shown in FIGS.
[0072]
FIG. 9 is a plan view showing a configuration of a MIS transistor constituting peripheral circuits such as the scanning line driving circuit 104 and the data line driving circuit 101. FIG. 10 is a cross-sectional view of the MIS transistor constituting this peripheral circuit taken along the line BB ′ of FIG. FIG. 10 also shows a pixel switching MIS transistor 30 formed in the image display region 10 a of the active matrix substrate 10.
[0073]
9 and 10, the MIS transistor constituting the peripheral circuit is configured as a complementary MIS transistor composed of a P-channel MIS transistor 80 and an N-channel MIS transistor 90. The semiconductor layer 60 (the outline is indicated by a dotted line) constituting the MIS transistors 80 and 90 for the driving circuit is formed in an island shape via the interlayer insulating film 12 formed on the bonded substrate 600. .
[0074]
In the MIS transistors 80 and 90, a high potential line 71 and a low potential line 72 are electrically connected to the source region of the semiconductor layer 60 through contact holes 63 and 64, respectively. The input wiring 66 is connected to a common gate electrode 65, and the output wiring 67 is electrically connected to the drain region of the semiconductor layer 60 through contact holes 68 and 69, respectively.
[0075]
Since such a peripheral circuit region is also formed through the same process as the image display region 10a, the interlayer insulating films 4 and 7 and the gate insulating film 2 are also formed in the peripheral circuit region. Similarly to the MIS transistor 30 for pixel switching, the MIS transistors 80 and 90 for the drive circuit have an LDD structure, and the high concentration source region 82, 92 and low concentration source regions 83 and 93, and high concentration drain regions 84 and 94 and low concentration drain regions 85 and 95, respectively.
The semiconductor layer 60 is composed of a single crystal silicon layer 220b formed by the above-described method, like the semiconductor layer 1a.
[0076]
(Manufacturing method of active matrix substrate)
The active matrix substrate 10 having such a configuration is manufactured using the composite semiconductor substrate (bonded substrate) 600 manufactured in the first embodiment. However, in this embodiment, as described below, a light shielding film 11a (see FIG. 8) is formed inside the bonded substrate 600.
[0077]
11 to 13 are process cross-sectional views illustrating a method for manufacturing the active matrix substrate 10 of the present embodiment.
In this embodiment, first, the composite semiconductor substrate 600 in the state shown in FIG. 3D, that is, the composite semiconductor substrate 600 shown in FIG. 11A is prepared. Here, in FIG. 11A, for the convenience of explanation, the scale is changed from FIG. 3D, and the dimensions of the main part are also changed. Further, in the composite semiconductor substrate 600 shown in FIG. 11A, the light shielding film 11a is formed in the insulating layer 12 (the insulating layer 500 in FIG. 3D), and further, formed by the method described above. In addition, the semiconductor layer 1a and the semiconductor layer 60 made of the single crystal silicon layer 220b are provided.
[0078]
The semiconductor layer 1a and the semiconductor layer 60 are formed to have different thicknesses by adjusting the degree of sacrificial oxidation. The plurality of single crystal silicon patterns 220b form the semiconductor layer 1a constituting the MIS type transistor 30 for pixel switching and the semiconductor layer 60 constituting the MIS type transistors 80 and 90 for the drive circuit in an island shape. is doing. Here, the semiconductor layer 1a constituting the MIS type transistor 30 for pixel switching is a single crystal silicon layer having a thickness of 100 nm or less, and the semiconductor layer 60 constituting the MIS type transistors 80 and 90 for the drive circuit is It is a single crystal silicon layer having a thickness of about 200 to 500 nm.
[0079]
As shown in FIG. 11B, a gate insulating film 2 made of a silicon oxide film is formed on the surfaces of the semiconductor films 1a and 60 on the composite semiconductor substrate 600 formed in this way, as shown in FIG. 11B. To do. Although not shown, impurity ions are implanted into the extended portion 1f of the semiconductor film 1a through a predetermined resist mask to form a lower electrode for forming the storage capacitor 70 between the capacitor line 3b. .
[0080]
Next, a polycrystalline silicon film and a molybdenum film, a tungsten film, a titanium film, a cobalt film, or these for forming the scanning line 3a, the capacitor line 3b, and the gate electrode 65 on the entire substrate surface by CVD or the like. After forming a conductive film made of a metal silicide film to a thickness of about 350 nm, as shown in FIG. 11C, patterning is performed using a photolithography technique, and scanning lines 3a, capacitor lines 3b, and gate electrodes are formed. 65 is formed.
[0081]
Next, as shown in FIG. 12A, in a state where the semiconductor layer 60 for forming the MIS transistor 80 for the P-channel type drive circuit is covered with a resist mask 301, the MIS transistor for pixel switching. 30 and the semiconductor layer 60 constituting the MIS type transistor 90 for the N-channel type drive circuit with the scanning line 3a and the gate electrode 65 as a mask, about 0.1 × 10 ¹³ / Cm ² ~ About 10 × 10 ¹³ / Cm ² The low concentration source regions 1b and 93 and the low concentration drain regions 1c and 95 are formed in a self-aligned manner with respect to the scanning line 3a by implanting low concentration impurity ions (phosphorus ions) at a dose of. Here, since it is located immediately below the scanning line 3a, the portion where the impurity ions are not introduced becomes the channel regions 1a ′ and 91 that remain in the semiconductor film 1a.
[0082]
Next, as shown in FIG. 12B, the resist is wider than the scanning line 3a and the gate electrode 65 and covers the semiconductor layer 60 for forming the MIS type transistor 80 for the P channel type driving circuit. A mask 302 is formed, and in this state, a high concentration of impurity ions (phosphorus ions) is about 0.1 × 10 × 10. ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² Then, the high concentration source regions 1b and 92 and the drain regions 1d and 94 are formed.
[0083]
Although not shown, a semiconductor for forming a MIS transistor 80 for a P-channel driver circuit using the gate electrode 65 as a mask while covering the N-channel MIS transistors 30 and 90 side. For layer 60, about 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² After implanting boron ions at a dose of 1 nm, the semiconductor layer 60 for forming the MIS type transistor 80 for the P channel type drive circuit is formed in a high concentration with the mask wider than the gate electrode 65 formed. Of impurities (boron ions) of about 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² As shown in FIG. 12C, a lightly doped source region 83, a lightly doped drain region 85, and a channel region 81 are formed, and a heavily doped source region 82 and a drain region 84 are formed. To do.
[0084]
Next, an interlayer insulating film 4 made of a silicon oxide film or the like is formed on the surface side of the scanning line 3a by a CVD method or the like, and then contact holes are formed by using a photolithography technique.
[0085]
Next, as shown in FIG. 13A, an aluminum film, a titanium nitride film, a titanium film, or a metal thereof for forming the data line 6a (source electrode) or the like on the surface side of the interlayer insulating film 4 A conductive film made of an alloy film containing any of the above as a main component is formed to a thickness of about 350 nm by a sputtering method or the like, and then patterned using a photolithography technique to form the data line 6a, high potential line 71, low potential. A line 72, an input wiring 66, and an output wiring 67 are formed. As a result, P-channel and N-channel MIS transistors 80 and 90 are completed in the peripheral circuit region.
[0086]
Next, as shown in FIG. 13B, after an interlayer insulating film 5 made of a silicon nitride film or a silicon oxide film is formed on the surface side of the data line 6a or the like by plasma CVD or the like, a photolithography technique is used. Using this, a contact hole is formed in the interlayer insulating film 5.
Next, as shown in FIGS. 8 and 10, the pixel electrodes 9a are formed in a predetermined pattern, and then the alignment film 16 is formed. As a result, the active matrix substrate 10 is completed.
[0087]
[Application to electronic devices]
Next, a projection type liquid crystal display device will be described with reference to FIGS. 14 and 15 as an example of an electronic apparatus including an electro-optical device.
First, FIG. 14 is a block diagram illustrating a configuration of an electronic apparatus including the liquid crystal device 100 configured similarly to the electro-optical device according to each of the above embodiments.
[0088]
14, the electronic device includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk, a tuning circuit that tunes and outputs an image signal of a television signal, and the like, and a clock generation circuit 1008. The image signal of a predetermined format is processed on the basis of the clock from the display information processing circuit 1002 and output to the display information processing circuit 1002. The display information output circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit, and is input based on a clock signal. A digital signal is sequentially generated from the display information and is output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that the drive circuit 1004 may be formed over an active matrix substrate included in the liquid crystal device 100, and in addition, the display information processing circuit 1002 may be formed over the active matrix substrate.
[0089]
As an electronic apparatus having such a configuration, a projection type liquid crystal display device (liquid crystal projector) described with reference to FIG. 15 can be given.
[0090]
A projection type liquid crystal display device 1100 shown in FIG. 15 prepares three liquid crystal modules including the liquid crystal device 100 in which the driving circuit 1004 is mounted on an active matrix substrate, and each of the RGB light valves 100R, 100G, and 100B. The projector is used as a projector. In this liquid crystal projector 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light corresponding to the three primary colors R, G, and B is emitted by three mirrors 1106 and two dichroic mirrors 1108. The light components are separated into components R, G, and B (light separating means) and led to the corresponding light valves 100R, 100G, and 100B (liquid crystal device 100 / liquid crystal light valve). At this time, since the optical component B has a long optical path, the light component B is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss. Then, the light components R, G, and B corresponding to the three primary colors respectively modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining unit) from three directions and are combined again, and then the projection lens. A color image is projected on a screen 1120 or the like via 1114.
[0091]
The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the specific configuration of the liquid crystal device described as the embodiment is merely an example, and the present invention can be applied to liquid crystal devices having various configurations. Further, for example, the present invention relates to an electro-optical device using various electro-optical elements using electroluminescence (EL), a digital micromirror device (DMD), or fluorescence by plasma emission or electron emission, and the electro-optical device. Needless to say, the present invention can also be applied to an electronic device equipped with the above.
Further, the single crystal semiconductor layer in the present invention is not limited to single crystal silicon, and for example, single crystal germanium can be used.
[Brief description of the drawings]
FIGS. 1A to 1E are process cross-sectional views of a manufacturing method according to the present invention.
2A to 2C are process cross-sectional views of a manufacturing method according to the present invention.
FIGS. 3A to 3D are process cross-sectional views of the manufacturing method according to the present invention. FIGS.
FIG. 4 is a plan view of the liquid crystal device according to the present invention as viewed from the counter substrate side.
5 is a cross-sectional view taken along the line HH ′ of FIG. 4. FIG.
FIG. 6 is an equivalent circuit diagram of various elements and wirings formed in a plurality of pixels.
FIG. 7 is a plan view showing a configuration of each pixel.
8 is a cross-sectional view cut at a position corresponding to the line AA ′ of FIG. 7;
FIG. 9 is a plan view of a circuit formed in the peripheral area of the image display area.
10 is a cross-sectional view of the driver circuit transistor shown in FIG. 9;
11A to 11C are process cross-sectional views of a method for manufacturing a liquid crystal device.
12A to 12C are process cross-sectional views of a method for manufacturing a liquid crystal device.
13A and 13B are process cross-sectional views of a method for manufacturing a liquid crystal device.
FIG. 14 is a block diagram illustrating a circuit configuration of an electronic device.
FIG. 15 is a cross-sectional view of a projection type electro-optical device as an example of an electronic apparatus.
[Explanation of symbols]
100 ... Liquid crystal device (electro-optical device),
200 ... single crystal silicon substrate (semiconductor substrate),
210 ... silicon oxide film (insulating layer),
220, 220b ... single crystal silicon layer (single crystal semiconductor layer),
220a ... thinned single crystal silicon layer,
220c ... single crystal silicon pattern, 225 ... thermal oxide film
230 ... Element non-formation region (predetermined region), 240 ... Element formation region,
500 ... support substrate, 510 ... oxide film (insulating layer), 550 ... insulating layer,
600 ... Composite semiconductor substrate (bonded substrate)

Claims (6)

A method for manufacturing a composite semiconductor substrate, in which a semiconductor substrate having a single crystal semiconductor layer is bonded to a support substrate,
Bonding the semiconductor substrate onto the support substrate to form a bonded substrate;
Thinning the predetermined region of the single crystal semiconductor layer in the bonded substrate by etching;
Heat treating the bonded substrate after thinning the predetermined region;
Equipped with a,
After the step of heat-treating the bonded substrate, further comprising a thermal oxidation step of thermally oxidizing the single crystal semiconductor layer in the bonded substrate;
The thinning of the predetermined region in the single crystal semiconductor layer is performed so that the thickness of the thinned single crystal semiconductor layer in the predetermined region is completely consumed by the thermal oxidation process. A method for producing a composite semiconductor substrate according to item. Between the step of bonding the supporting substrate and the semiconductor substrate to form a bonded substrate and the step of thinning the predetermined region in the bonded substrate by etching, the semiconductor substrate of the bonded substrate is The method of manufacturing a composite semiconductor substrate according to claim 1, further comprising a step of thinning the single crystal semiconductor layer by separating in a thickness direction. The region of the single crystal semiconductor layer other than a region where an element is formed is thinned in the step of thinning the single crystal semiconductor layer in the bonded substrate by etching. 3. A method for producing a composite semiconductor substrate according to 2. The method of manufacturing a composite semiconductor substrate according to claim 1, wherein the heat treatment of the bonded substrate after thinning the predetermined region is performed in a range of 700 ° C. or more and 1200 ° C. or less. . The method for manufacturing a composite semiconductor substrate according to claim 1, wherein the single crystal semiconductor layer is made of single crystal silicon. The method for manufacturing a composite semiconductor substrate according to claim 1, wherein the support substrate is a translucent substrate.

Images