JP2004253458A - Composite semiconductor substrate, method of manufacturing same, electrooptic device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a composite semiconductor substrate and its manufacturing method by which the formation of slips, dislocation, lattice defects, and HF defects in a single-crystal semiconductor layer is prevented by relieving the thermal stress generated in a heat-treating step performed for increasing the lamination strength between substrates, and to provide an electrooptic device and electronic equipment. <P>SOLUTION: The method of manufacturing the composite semiconductor substrate 600 constituted by laminating a semiconductor substrate provided with the single-crystal semiconductor layer 220 upon a supporting substrate includes a step of forming a laminated substrate 600 by laminating the semiconductor substrate provided with the single-crystal semiconductor layer 220 upon the supporting substrate, a step of reducing the thickness of a prescribed area 230 of the single-crystal semiconductor layer 220 in the laminated substrate 600 by etching the area 230, and a step of heat-treating the laminated substrate 600 after the thickness of the prescribed area 230 is reduced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a composite semiconductor substrate having an SOI structure, a composite semiconductor substrate manufactured by the method, an electro-optical device using the composite semiconductor substrate, and an electronic apparatus.
[0002]
[Prior art]
SOI (Silicon On Insulator) technology, which uses a silicon layer provided on an insulator layer for forming a semiconductor device, uses a normal single crystal silicon substrate such as an α-ray resistance, a latch-up characteristic, or a short channel suppression effect. In order to exhibit excellent characteristics that cannot be achieved, the development thereof has been promoted for the purpose of high integration of semiconductor devices and the like.
[0003]
In recent years, an excellent short channel suppression effect has been found by forming a device on an SOI layer thinned to a thickness of 100 nm or less. In addition, the SOI device formed in this manner has high reliability due to its excellent radiation resistance, and can achieve high speed and low power consumption of the element by reducing the parasitic capacitance. It has excellent features such as miniaturization of process rules by being able to manufacture a field effect transistor.
[0004]
As a method for forming such an SOI structure, there is a method for manufacturing an SOI substrate by bonding a single crystal silicon substrate. In this method, which is generally called a bonding method, a single-crystal silicon substrate and a supporting substrate are overlapped with each other via an oxide film and bonded at about room temperature using OH groups on the substrate surface, and then the single-crystal silicon substrate is ground. Or thinning by polishing or etching, followed by a siloxane bond (Si-O-Si) by a heat treatment at about 700 ° C. to 1200 ° C. to increase the bonding strength and form a single-crystal silicon layer on the supporting substrate. is there. According to this method, the single crystal silicon substrate is directly thinned, so that the silicon thin film has excellent crystallinity, and thus a high-performance device can be manufactured.
[0005]
In addition, as an application of this bonding method, hydrogen ions are implanted into a single crystal silicon substrate, bonded to a supporting substrate, and then heat-treated at about 400 to 600 ° C. to form a thin film silicon layer on the single crystal silicon substrate. Separated from the hydrogen implanted region and then increased the bonding strength by heat treatment up to about 1100 ° C., or a single crystal silicon layer was epitaxially grown on a porous silicon substrate and bonded to a support substrate. There is known a method of forming an epitaxial single-crystal silicon thin film on a supporting substrate by removing the silicon substrate and etching the porous silicon layer later.
[0006]
An SOI substrate formed by a bonding method can be used for manufacturing various devices in the same manner as a normal bulk semiconductor substrate (semiconductor integrated circuit). On the other hand, the difference from the conventional bulk substrate is that various materials can be used for the support substrate. That is, as the support substrate, not only a normal silicon substrate but also a quartz substrate or a glass substrate having a light-transmitting property can be used. Therefore, by forming a single-crystal silicon thin film on a light-transmitting substrate, even in a device requiring light transmissivity, for example, an electro-optical device such as a transmissive liquid crystal device, a crystalline silicon thin film is formed on the active matrix substrate. A high-performance transistor element can be formed using a single crystal silicon layer excellent in quality. That is, by forming a MIS transistor for pixel switching for driving a pixel electrode or a MIS transistor for a driving circuit constituting a driving circuit in a peripheral region of an image display region on an SOI layer which is a single crystal silicon layer, fine display can be achieved. Speed and speed can be achieved.
[0007]
Here, in the case where an SOI substrate is used for an electro-optical device such as a transmission type liquid crystal device, since the SOI layer has a different thermal expansion coefficient from that of a light-transmitting substrate such as a quartz substrate which is a supporting substrate, the bonding strength described above is reduced. In a heat treatment step or a thermal oxidation treatment step for raising the temperature, thermal stress occurs due to a difference in thermal expansion coefficient, and as a result, slips, dislocations, lattice defects, HF defects, and the like are formed in the single crystal semiconductor layer (SOI layer). Device characteristics may be affected.
[0008]
As a technique for coping with thermal stress due to such a difference in thermal expansion coefficient, a technique in which a stress relaxation layer is provided between a semiconductor single crystal region and a glass material to reduce substrate warpage or the like is conventionally known ( For example, see Patent Document 1).
Further, in order to prevent thermal stress during bonding from remaining in the single crystal semiconductor layer (single crystal silicon layer), the single crystal silicon thin film is patterned to form an island silicon layer. A technique of performing thermal oxidation treatment on a layer is known (for example, see Patent Document 2).
Further, a technique is known in which a part of a single crystal semiconductor substrate is changed to a porous layer by anodic oxidation, and this porous layer is used as a stress relaxation layer (for example, see Patent Document 3).
[0009]
[Patent Document 1]
JP-A-7-142570 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2000-12864 [Patent Document 3]
Japanese Patent Application Laid-Open No. 2000-106424
[Problems to be solved by the invention]
However, the technique of providing the stress relaxation layer between the semiconductor single crystal region and the glass material cannot remove the formed stress relaxation layer, and the stress relaxation layer is colored and non-transparent. Therefore, there is a problem that, for example, a transmission type liquid crystal device cannot be manufactured from the obtained composite semiconductor substrate.
[0011]
In the technique of performing thermal oxidation treatment on an island-shaped silicon layer, sacrificial oxidation is performed particularly to reduce the thickness of the silicon layer, and thereafter, when the sacrificial oxide layer is removed by wet etching, the wet etching liquid is used for the island-shaped silicon layer. There is a possibility that the insulating layer underlying the silicon layer is dissolved through the space between the layers and reaches the bonding interface with the supporting substrate. When the wet etchant reaches the bonding interface in this way, it causes inconvenience such as peeling off at the bonding interface. For example, a transmission type liquid crystal device (light When a valve is manufactured, display defects occur due to peeling of the bonding interface.
[0012]
In the technique using a porous layer as a stress relaxation layer, as described above, hydrogen ions are implanted in advance to reduce the thickness of the single-crystal silicon layer after bonding, and the thin-film silicon layer is subjected to heat treatment to form a single-crystal silicon substrate. At the time of separation from the hydrogen implantation region, the separation may not be properly performed because the hydrogen ion implantation profiles are different between the single crystal silicon layer and the porous layer. In addition, although the single-crystal silicon substrate separated in this manner is usually used as it is in another SOI substrate as it is, in this technique, the porous layer remains on the single-crystal silicon substrate after the separation. Therefore, it cannot be used directly. In addition, when a silicon oxide layer for bonding is formed, a difference in film quality occurs between a silicon oxide layer formed from a single crystal silicon layer and a silicon oxide layer formed from a porous layer. There is a possibility that the alignment may be uneven.
[0013]
The present invention has been made in view of the above circumstances, the purpose thereof is to reduce the thermal stress generated in a heat treatment step or the like for increasing the bonding strength, slip and dislocation in the single crystal semiconductor layer, lattice defects, HF defects and the like can be prevented from being formed. Further, the present invention can be applied to the manufacture of a transmissive liquid crystal device. In that case, display defects can be prevented, and uneven bonding occurs. It is an object of the present invention to provide a method of manufacturing a composite semiconductor substrate, a composite semiconductor substrate, an electro-optical device, and an electronic apparatus.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a composite semiconductor substrate according to the present invention is a method for manufacturing a composite semiconductor substrate, comprising: bonding a semiconductor substrate having a single crystal semiconductor layer on a support substrate; Bonding the semiconductor substrate to form a bonded substrate, thinning a predetermined region of the single crystal semiconductor layer in the bonded substrate by etching, and bonding the thinned predetermined region to the bonded substrate. And a step of heat-treating.
According to this method for manufacturing a composite semiconductor substrate, a predetermined region of the single crystal semiconductor layer in the bonded substrate is thinned by etching, and then heat treatment is performed. Therefore, the heat treatment can improve the bonding strength. Of course, at this time, stress tends to concentrate on the thinned portion of the single crystal semiconductor layer, so that the thinned portion functions as a stress relieving layer. , A slip, a dislocation, a lattice defect, an HF defect and the like are prevented from being formed in the single crystal semiconductor layer.
In addition, when a predetermined region of the single crystal semiconductor layer is thinned by etching, even when wet etching is employed, the thinned single crystal semiconductor layer remains as it is, so that the etchant may penetrate to the bonding interface. Therefore, inconvenience such as peeling off at the bonding interface is prevented.
[0015]
In the method for manufacturing a composite semiconductor substrate, the step of bonding the support substrate and the semiconductor substrate to form a bonded substrate and the step of thinning the predetermined region of the bonded substrate by etching are performed. It is preferable that the method further includes a step of separating the semiconductor substrate of the bonded substrate in a thickness direction to reduce the thickness of the single crystal semiconductor layer.
In such a case, when the semiconductor substrate in the bonded substrate is separated in the thickness direction to reduce the thickness of the single crystal semiconductor layer, the single crystal semiconductor layer before the thinning has a porous layer or the like. Since the single crystal semiconductor substrate is not provided, the single crystal semiconductor substrate after separation can be used as it is for manufacturing another composite semiconductor substrate (SOI substrate). In the case where an oxide layer for bonding is formed over the semiconductor substrate, the single crystal semiconductor layer is not provided with a porous layer or the like. The occurrence of uneven bonding due to a difference in film quality between the oxide layer and the oxide layer formed from the porous layer is also prevented.
[0016]
Further, the method for manufacturing a composite semiconductor substrate further includes, after the step of heat-treating the bonded substrate, a thermal oxidation step of thermally oxidizing the single-crystal semiconductor layer in the bonded substrate, wherein the single-crystal semiconductor layer It is preferable that the thickness of the predetermined region in is reduced so that the thinned single crystal semiconductor layer in the predetermined region is entirely consumed in the thermal oxidation step.
By doing so, by etching and removing the thermal oxide film formed in the thermal oxidation step, it is possible to directly remove the thinned portion by etching the predetermined region. Therefore, the steps can be simplified, for example, a step of forming a single crystal semiconductor pattern formed in an element formation region can be omitted.
[0017]
In the method for manufacturing a composite semiconductor substrate, in the step of thinning the single crystal semiconductor layer in the bonded substrate by etching, a region of the single crystal semiconductor layer other than a region where an element is formed is thin. It is preferred that the
With this configuration, as described above, stress tends to concentrate on the thinned portion of the single crystal semiconductor layer, and the thinned portion functions as a stress relieving layer. Formation of slip, dislocations, lattice defects, HF defects, and the like in the single crystal semiconductor layer in the region where the is formed.
[0018]
In the method for manufacturing a composite semiconductor substrate, it is preferable that the heat treatment of the bonded substrate after the predetermined region is thinned is performed at a temperature of 700 ° C. or more and 1200 ° C. or less.
By doing so, the bonding strength of the bonded substrate can be sufficiently increased by this heat treatment.
[0019]
In the method for manufacturing a composite semiconductor substrate, the single crystal semiconductor layer is preferably made of single crystal silicon.
With this configuration, the single crystal semiconductor layer is made of general single crystal silicon, so that a composite semiconductor substrate can be manufactured at a lower cost than when another single crystal semiconductor layer is used.
[0020]
In the method for manufacturing a composite semiconductor substrate, the support substrate is preferably a light-transmitting substrate.
In this manner, for example, a transmission-type liquid crystal device (light valve) can be manufactured from the obtained composite semiconductor substrate.
[0021]
A composite semiconductor substrate according to the present invention is obtained by any one of the above manufacturing methods.
According to this composite semiconductor substrate, slip, dislocation, lattice defect, HF defect, and the like are prevented from being formed in the single crystal semiconductor layer. For example, this single crystal semiconductor layer is formed in a semiconductor element such as a thin film transistor. In this case, it is good and reliable.
[0022]
An electro-optical device according to the present invention includes the composite semiconductor substrate.
According to this electro-optical device, for example, by having the above-described good and highly reliable semiconductor element, the electro-optical device itself becomes good and highly reliable.
[0023]
An electronic apparatus according to another aspect of the invention includes the electro-optical device.
According to this electronic device, by providing the above-described good and highly reliable electro-optical device, the electronic device itself is also good and highly reliable.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
1 to 3 are process cross-sectional views illustrating a method for manufacturing a composite semiconductor substrate (laminated substrate) having an SOI structure according to the first embodiment of the present invention.
[0025]
In this embodiment mode, first, as shown in FIG. 1A, a single crystal silicon substrate (semiconductor substrate) 200 having a thickness of, for example, 750 μm is prepared, and then, a first surface 201 and a second surface 202 thereof are provided. A silicon oxide film (insulating layer) 210 is formed on at least the entire surface of the first surface 201. The silicon oxide film 210 may be formed to a thickness of about 200 nm or more in the present embodiment, as long as the first surface 201 has a thickness that is hydrophilic in a bonding step described later.
[0026]
Next, as shown in FIG. 1B, hydrogen ions are implanted into the single crystal silicon substrate 200 on which the silicon oxide film 210 is formed from the first surface 201 side. As a result, an ion implantation layer having a penetration depth distribution as shown by a broken line in FIG. 1B is formed inside the single crystal silicon substrate 200. The ion implantation conditions at this time are, for example, an acceleration energy of 60 to 150 keV and a dose of 5 × 10 ¹⁶ cm ⁻² to 10 × 10 ¹⁶ cm ⁻² .
[0027]
Next, a support substrate 500 is prepared as shown in FIG. 1C, and then a silicon oxide film, NSG (non-doped silicate glass), or the like is formed on the entire surface of the support substrate 500 by a sputtering method, a CVD method, or the like. An oxide film (insulating layer) 510 is formed. Next, the surface of the oxide film 510 is polished and flattened by a CMP method or the like. Here, the thickness of the oxide film 510 is, for example, about 400 to 1000 nm, and more preferably about 800 nm. In the case where a substrate mainly composed of SiO ₂ such as quartz is used as the support substrate 500, the step of forming the oxide film 510 can be omitted.
[0028]
Here, the oxide films (insulating layers) 210 and 510 are formed to secure adhesion between the single crystal silicon substrate (semiconductor substrate) 200 and the support substrate 500. As the support substrate 500, a substrate (light-transmitting substrate) made of a light-transmitting material such as glass or quartz can be used. In that case, the obtained composite semiconductor substrate can be applied to a transmission type electro-optical device, for example, a transmission type liquid crystal device (light valve).
[0029]
Next, as shown in FIG. 1D, the surface 501 of the single crystal silicon substrate 200 on the oxide film 510 side and the surface of the support substrate 500 on the silicon oxide film 210 side are joined to form the oxide films 210 and 510. The single crystal substrate 200 is bonded on the supporting substrate 500 at room temperature to about 200 ° C. Then, the single crystal silicon layer 220 and the supporting substrate 500 are attached to each other through the insulating layer 550 (the oxide films 210 and 510) by the action of the OH group on the substrate surface as shown in FIG. A semiconductor substrate (laminated substrate) 600 is formed.
[0030]
Here, with respect to the single crystal silicon substrate 200 in the bonded composite semiconductor substrate 600, the single crystal silicon layer is thinned to, for example, about 200 nm to obtain a single crystal silicon layer 220 illustrated in FIG. The single-crystal silicon layer 220 is formed by performing a heat treatment at a low temperature of, for example, 400 ° C. to 600 ° C. to separate and cut the single-crystal silicon substrate 200 at the position of the ion-implanted layer. This separation and cutting phenomenon occurs because the bond of the semiconductor crystal is cut by the ions introduced into the single crystal silicon substrate 200, and becomes more prominent at the peak position of the ion concentration in the ion implantation layer. Therefore, the position where the cutting is performed by the heat treatment is the same as the peak position of the ion concentration. Note that since the surface of the single crystal silicon layer 220 exposed by the above separation and cutting has irregularities of about several nm, the surface is smoothed by a CMP method or the surface is subjected to a hydrogen annealing method of performing a heat treatment in a hydrogen atmosphere. Preferably, it is smoothed. Further, the single crystal silicon substrate 200 separated in this manner can be used for another SOI substrate as it is.
[0031]
Further, a film of molybdenum, tungsten, or the like may be formed below the oxide film 510 on the surface of the supporting substrate 500. Since such a film functions as, for example, a heat conductive film, the temperature distribution of the supporting substrate 500 can be improved. Therefore, for example, in the step of bonding the supporting substrate 500 and the single-crystal silicon substrate 200, the temperature distribution of the bonding interface can be made uniform by the heat conductive film, and thus the bonding at this interface can be performed. It can be made uniform and the bonding strength can be improved. Further, when used for a transmissive liquid crystal device or the like, a film of molybdenum, tungsten, or the like can function as a light-blocking layer. Materials that can be used for such a film include, besides those described above, tantalum, cobalt, titanium and other high-melting metals or alloys containing them, or polycrystalline silicon, tungsten silicide, molybdenum silicide, and the like. A typical silicide film or the like can be used.
[0032]
Subsequently, a resist layer is formed on the single crystal silicon layer 220, and further, exposure and development are performed to expose the element non-formation region 230 of the single crystal silicon layer 220 as shown in FIG. A resist pattern 610 is formed. Here, the element non-formation region is a region in the single crystal silicon layer 220 where no active element, for example, a switching element or a logic circuit, an element by MEMS (Micro Electro Mechanical Systems), or the like is not formed, and is etched away in a later step. Area.
[0033]
However, in this step, as shown in FIG. 2A, a portion in contact with the element formation region 240, for example, a width of about 1 μm from a boundary with the element formation region 240 without exposing the entire element non-formation region 230. The portion is covered with the resist pattern 610 without exposing the portion. This is to provide a margin when the thickness of the single crystal silicon layer 220 in the element non-forming region 230 is reduced using the resist pattern 610 as a mask, as described later.
[0034]
After forming the resist pattern 610 in this manner, the exposed element non-formation region 230 is etched and thinned using the resist pattern 610 as a mask as shown in FIG. 2B. The etching for reducing the thickness may be performed by wet etching or dry etching. In this example, wet etching using an etching solution such as KOH or TMAH (tetramethylammonium hydroxide) is used. It is assumed that it is performed.
[0035]
When wet etching is employed, side etching is expected to occur to some extent. However, as described above, a margin is provided in the resist pattern 610, and the resist pattern 610 extends to the element non-forming region 230 near the boundary with the element forming region 240. Since it covers, the element formation region 240 is prevented from being etched even if side etching occurs.
Further, in the etching of the single crystal silicon layer 220, only the thickness is reduced and the entire thickness is not removed by etching. Therefore, the thinned single crystal silicon layer 220a remains as it is. Therefore, inconvenience such as peeling off at the bonding interface is prevented.
[0036]
Further, as to the degree of thinning, that is, the depth of thinning by etching, as described above, in the case of this example where the thickness of the single crystal silicon layer 220 is about 200 nm and the thickness of the silicon oxide film 210 is about 200 nm First, the thickness of the single crystal silicon layer 220a is set to be about 150 nm to about 50 nm. Here, such etching for reducing the thickness is controlled by time based on an etching rate obtained in advance by experiments or the like.
The reason why the thickness of the thinned single crystal silicon layer 220a is set to be equal to or less than 150 nm and the thickness of the thinned single crystal silicon layer 220a is set to be equal to or less than 50 nm is as follows. Is performed to reduce the thickness to a desired thickness, in this example, about 50 nm.
[0037]
In order to make the single-crystal silicon layer 220 having a thickness of 200 nm to a thickness of 50 nm by sacrificial oxidation and etching, it is necessary to sacrificial oxidize a thickness of 150 nm and then remove the same by etching. At this time, if the thickness of the thinned single-crystal silicon layer 220a in the element non-forming region 230 is 150 nm or less, the entire thickness is consumed by sacrificial oxidation (thermal oxidation), and therefore, by subsequent etching, This is because the sacrificial oxide film (thermal oxide film) can be removed by etching, which makes it possible to omit the step of forming a single crystal silicon pattern formed in the element formation region 240, for example.
If the thickness difference between the single crystal silicon layer 220 and the non-thinned single crystal silicon layer 220 is less than 50 nm, the function of the thinned single crystal silicon layer 220a as a stress relaxation layer described later may not be sufficiently exhibited.
[0038]
On the other hand, the reason why the thickness of the thinned single-crystal silicon layer 220a is set to be less than 50 nm and the thickness of the thinned single-crystal silicon layer 220a is set to be less than 50 nm is that the thickness of the single-crystal silicon layer 220a becomes smaller than 50 nm. When the single crystal silicon layer 220 in the region 240 is subjected to sacrificial oxidation and etching treatment to have a desired thickness, in this example, about 50 nm, not only the oxide layer formed from the thinned single crystal silicon layer 220a but also the lower layer. This is because the entire thickness of the silicon oxide film 210 as the underlying layer is etched. That is, if the silicon oxide film 210 is etched to the entire thickness in this manner, particularly when wet etching is employed as an etching, the etchant penetrates to the bonding interface, and separation occurs at the bonding interface. This is because there is a fear.
[0039]
After the element non-forming region 230 of the single crystal silicon layer 220 is thinned in this way to form a thin single crystal silicon layer 220a, the resist pattern 610 is removed as shown in FIG. The semiconductor substrate (bonded substrate) 600 is preferably subjected to a heat treatment in a temperature range of 700 ° C. or more and 1200 ° C. or less to improve the bonding strength. When such heat treatment is performed, hydrogen (H) existing at the bonding interface between the oxide films 210 and 510 of the composite semiconductor substrate 600 is volatilized by this heat treatment to generate a Si—O—Si bond, so that bonding is performed. The adhesion at the interface can be improved.
[0040]
The heat treatment is not particularly limited, but can be performed by, for example, a general heating device (sintering device). In that case, the temperature in the heating device may be adjusted in advance to 700 ° C. or more and 1200 ° C. or less, and the composite semiconductor substrate (bonded substrate) 600 may be placed therein and heat-treated. May be set at a temperature lower than 700 ° C., for example, at a low temperature of about 200 ° C. to 400 ° C., the composite semiconductor substrate 600 may be put here, and then the temperature may be raised to 700 ° C. or higher to perform heat treatment. In this manner, by performing the heat treatment from room temperature to a high temperature immediately, it is possible to prevent the composite semiconductor substrate 600 from generating excessive thermal stress. Note that, for the heat treatment here, a laser annealing method or the like may be adopted instead of the heating by the heating device.
[0041]
When the heat treatment is performed in this manner, the single-crystal silicon substrate 200 (single-crystal silicon layer 220) and the support substrate 500 are made of different materials, and usually have a difference in thermal expansion coefficient between them. Stress occurs. In the present embodiment, since the single crystal silicon layer 220 is partially thinned first, the thinned portion 220a can function as a stress relaxation layer. The formation of a slip, a dislocation, a lattice defect, an HF defect, or the like in the formation region 240 can be prevented.
[0042]
Next, as described above, the single-crystal silicon layer 220 is thermally oxidized (sacrificial oxidation) so that the single-crystal silicon layer 220 has a desired thickness (about 50 nm in this example) by a sacrificial oxidation method. As shown in (), the upper portion of the single crystal silicon layer 220 is formed as a thermal oxide film 225 having a thickness of about 300 nm (250 nm to 350 nm). At this time, since the thickness of the thinned single-crystal silicon layer 220a is about 150 nm to 50 nm, the entire thickness of the thinned single-crystal silicon layer 220a is consumed by thermal oxidation as described above, The oxide film 225 is formed.
[0043]
Next, as shown in FIG. 3B, the thermal oxide film 225 formed by the thermal oxidation is removed by etching to form a single-crystal silicon layer 220b having a desired thickness.
In the etching of the thermal oxide film 225, dry etching such as reactive ion etching (RIE) is employed in the first half to increase the etching speed and shorten the processing time, and in the latter half, the underlying layer of the thermal oxide film 225 is used. It is preferable to use wet etching so as not to damage a single crystal silicon layer 220. Here, as described above, the entire portion of the thinned single-crystal silicon layer 220a is a thermal oxide film 225, and the underlying silicon oxide film 210 has a thickness of about 200 nm. Even when wet etching is used for the later etching removal of the thermal oxide film 225, the fact that the entire thickness of the silicon oxide film 210 is etched, the etchant penetrates to the bonding interface, and the separation occurs at the bonding interface. Absent.
[0044]
When the single-crystal silicon layer 220b has a desired thickness in this manner, in this example, as described above, the single-crystal silicon layer 220 in the element non-forming region 230 is not entirely reduced in thickness, and therefore a part thereof is changed to single-crystal silicon. First, as shown in FIG. 3C, a resist pattern 620 covering only the element formation region 240 of the single crystal silicon layer 220b is formed to remove the layer 220b. Subsequently, using this as a mask, the single crystal silicon layer 220b in the element non-forming region 230 is removed by etching, and the resist pattern 620 is further removed as shown in FIG. 220c is formed. Here, as for the etching of the single crystal silicon layer 220b in the element non-formation region 230, wet etching is preferably employed so that the single crystal silicon pattern 220c to be formed is not damaged.
[0045]
When the single-crystal silicon layer 220b in the element non-forming region 230 is removed by etching in this manner, the single-crystal silicon layer 220a in the thinned portion in the heat treatment step in particular functions as a stress relaxation layer. Since stress tends to concentrate on the shoulder 230a of the non-thinned single-crystal silicon layer 220 shown in FIG. 3C, it can be obtained by removing this portion as shown in FIG. The formed single crystal silicon pattern 220c becomes a good single crystal silicon layer without any damage due to stress. That is, as described above, the single crystal silicon pattern 220c formed in the element formation region 240 has a good single crystal silicon layer in which slips, dislocations, lattice defects, HF defects, and the like are not formed and which is not damaged. It has become.
[0046]
As described above, according to the present embodiment, the element non-formation region 230 of the single crystal silicon layer 220 in the composite semiconductor substrate (bonded substrate) 600 is thinned by etching, and thereafter, for improving the bonding strength. Since the heat treatment is performed, the bonding strength can be improved by the heat treatment, and at this time, the thinned portion 220a functions as a stress relieving layer, and thus the obtained single crystal silicon pattern The formation of slips, dislocations, lattice defects, HF defects, and the like in 220c is prevented.
[0047]
In the above embodiment, as shown in FIG. 2A, the resist pattern 610 is formed with a margin without exposing the entire element non-forming region 230, but the present invention is not limited to this. The resist pattern 610 is formed so as to expose the entire non-element formation region 230 without taking a margin and to cover the entire element formation region 240 without using a margin. May be etched. At this time, as the etching, either wet etching or dry etching can be adopted, but it is preferable to use dry etching with higher patterning accuracy.
[0048]
This eliminates the need for the step of etching and removing the single crystal silicon layer 220b in the element non-forming region 230 shown in FIGS. 3C and 3D. By setting the thickness of the single crystal silicon layer 220a in the region 230 to a thickness that is completely consumed by the subsequent thermal oxidation, patterning for forming the single crystal silicon pattern 220c formed in the element formation region 240 is performed. The steps can be omitted, and the steps can be simplified.
[0049]
Further, in the above embodiment, at least a part of the insulating layer 550 is made to flow during heat treatment of at least 1200 ° C. or less, such as PSG (phosphosilicate glass), BSG (boron silicate glass), or BPSG (boron phosphorus silicate glass). A layer having properties or elasticity may be formed in advance. BPSG commonly used in semiconductor processes has fluidity at 850 ° C. or higher. Depending on the concentration of B and P, fluidity can be provided from 700 ° C. Since the thermal stress is further alleviated by this fluid layer, it is suitable for a composite semiconductor substrate (SOI substrate) having a different coefficient of thermal expansion. Note that when PSG, BSG, or BPSG is applied to the fluid layer, a protective layer such as a silicon nitride film is formed on the fluid layer so as not to adversely affect the semiconductor element formed on the single crystal silicon pattern 220b. It is preferable to provide it on the upper part.
[0050]
[Embodiment 2]
The method described in the first embodiment can be applied to the manufacture of various semiconductor devices. Therefore, in this embodiment, an example in which an active matrix substrate (semiconductor device) of a liquid crystal device (electro-optical device) is formed using the composite semiconductor substrate (bonded substrate) 600 described in Embodiment 1 will be described.
[0051]
(Overall configuration of liquid crystal device)
FIG. 4 is a plan view of the liquid crystal device together with the components formed thereon viewed from the counter substrate side, and FIG. 5 is a cross-sectional view taken along line HH ′ of FIG. 4 including the counter substrate. .
In FIG. 4, a sealing material 52 is provided along an edge of the active matrix substrate 10 of the liquid crystal device 100, and a frame 53 made of a light-shielding material is formed in an inner region thereof. In a region outside the sealing material 52, a data line driving circuit 101 and an external input terminal 102 are provided along one side of the active matrix substrate 10, and a scanning line driving circuit 104 is provided on two sides adjacent to this one side. It is formed along.
[0052]
If the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a. For example, an odd-numbered data line supplies an image signal from a data line driving circuit disposed along one side of the image display area 10a, and an even-numbered data line is connected to the opposite side of the image display area 10a. An image signal may be supplied from a data line driving circuit disposed along the line. If the data lines are driven in a comb-tooth shape as described above, the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the active matrix substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided. Then, a precharge circuit or an inspection circuit may be provided. In at least one of the corners of the opposing substrate 20, an upper / lower conductive material 106 for establishing electric conduction between the active matrix substrate 10 and the opposing substrate 20 is formed.
[0053]
Then, as shown in FIG. 5, the opposing substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 4 is fixed to the active matrix substrate 10 by the sealing material 52. The sealing material 52 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the active matrix substrate 10 and the counter substrate 20 around the periphery thereof. And a gap material such as glass fiber or glass beads.
[0054]
As will be described in detail later, the active matrix substrate 10 has pixel electrodes 9a formed in a matrix. On the other hand, a light-shielding film 23 called a black matrix or a black stripe is formed on the opposing substrate 20 in a region facing a vertical and horizontal boundary region of a pixel electrode (described later) formed on the active matrix substrate 10. A counter electrode 21 made of an ITO film is formed on the upper layer side.
[0055]
The liquid crystal device thus formed is used, for example, in a projection type liquid crystal display device (liquid crystal projector) described later. In this case, three liquid crystal devices 100 are each used as a light valve for RGB, and each of the liquid crystal devices 100 receives light of each color separated through a dichroic mirror for RGB color separation as projection light. Will be incident. Therefore, no color filter is formed in the liquid crystal device 100 of each of the above embodiments.
[0056]
However, by forming an RGB color filter together with its protective film in a region facing each pixel electrode 9a on the opposing substrate 20, in addition to the projection type liquid crystal display device, a mobile computer, a mobile phone, a liquid crystal television, etc., which will be described later. It can be used as a color liquid crystal display device of electronic equipment.
[0057]
Furthermore, by forming microlenses on the opposing substrate 20 so as to correspond to each pixel, the efficiency of condensing incident light on the pixel electrode 9a can be increased, so that bright display can be performed. Furthermore, a dichroic filter that creates RGB colors by utilizing the interference effect of light may be formed by stacking a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color display can be performed.
[0058]
(Configuration and Operation of Liquid Crystal Device 100)
Next, the electrical configuration and operation of an active matrix liquid crystal device (electro-optical device) will be described with reference to FIGS.
[0059]
FIG. 6 is an equivalent circuit diagram of various elements and wiring in a plurality of pixels formed in a matrix to form the image display area 10a of the liquid crystal device 100. FIG. 7 is a plan view of adjacent pixels on an active matrix substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 8 is an explanatory diagram showing a cross section at a position corresponding to line AA ′ in FIG. 7 and a cross section in a state where liquid crystal as an electro-optical material is sealed between the active matrix substrate and the counter substrate. In these drawings, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawings.
[0060]
6, in the image display area 10a of the liquid crystal device 100, each of a plurality of pixels formed in a matrix has a pixel electrode 9a and a MIS transistor 30 for pixel switching for controlling the pixel electrode 9a. A data line 6a formed and supplying a pixel signal is electrically connected to the source of the MIS transistor 30. The pixel signals S1, S2,... Sn to be written to the data line 6a are supplied line-sequentially in this order. A scanning line 3a is electrically connected to the gate of the MIS transistor 30. At predetermined timing, scanning signals G1, G2... Gm are pulsed to the scanning line 3a in a line-sequential order. It is configured to apply. The pixel electrode 9a is electrically connected to the drain of the MIS transistor 30. By turning on the MIS transistor 30 as a switching element for a certain period of time, the pixel signal S1 supplied from the data line 6a is turned on. , S2... Sn are written into each pixel at a predetermined timing. The pixel signals S1, S2,... Sn of a predetermined level written in the liquid crystal through the pixel electrode 9a in this manner are held for a certain period between the pixel electrodes S1, S2,...
[0061]
Here, a storage capacitor 70 (capacitor) may be added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode for the purpose of preventing the held pixel signal from leaking. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the charge retention characteristics are improved, and a liquid crystal device capable of performing display with a high contrast ratio can be realized. The method of forming the storage capacitor 70 may be either the case where the storage capacitor 70 is formed between the capacitor line 3b which is a wiring for forming a capacitor, or the case where the storage capacitor 70 is formed between the storage line 70 and the preceding scanning line 3a. Is also good.
[0062]
In FIG. 7, a plurality of transparent pixel electrodes 9a (regions surrounded by dotted lines) are formed in a matrix on the active matrix substrate 10 of the liquid crystal device 100 for each pixel, and the vertical and horizontal boundary regions of the pixel electrodes 9a are formed. A data line 6a (indicated by a dashed line), a scanning line 3a (indicated by a solid line), and a capacitance line 3b (indicated by a solid line) are formed along.
As shown in FIG. 8, the liquid crystal device 100 includes an active matrix substrate 10 and a counter substrate 20 that is disposed to face the active matrix substrate.
[0063]
In this embodiment, the base of the active matrix substrate 10 is formed of a bonded substrate (composite semiconductor substrate) 600 described later, and the base of the counter substrate 20 is formed of a transparent substrate 20b such as a quartz substrate or a heat-resistant glass plate. A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is formed above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is formed by performing a rubbing process on an organic thin film such as a polyimide thin film. In the counter substrate 20, an alignment film 22 made of a polyimide film is also formed on the upper layer side of the counter electrode 21, and this alignment film 22 is also a film obtained by performing a rubbing process on the polyimide film.
[0064]
In the image display region 10a of the active matrix substrate 10, a MIS transistor 30 for pixel switching for controlling switching of each pixel electrode 9a is formed at a position adjacent to each pixel electrode 9a. Further, inside the bonded substrate 600, a light-shielding film 11a made of a chromium film or the like is formed in a region overlapping with the MIS transistor 30 in a plane. An interlayer insulating film 12 is formed on the surface of the light-shielding film 11a, and an MIS transistor 30 is formed on the surface of the interlayer insulating film 12. That is, the interlayer insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the MIS transistor 30 from the light shielding film 11a.
[0065]
As shown in FIGS. 7 and 8, the MIS transistor 30 for pixel switching has an LDD (Lightly Doped Drain) structure, and a channel is formed in the semiconductor layer 1a by an electric field from the scanning line 3a. A channel region 1a ', a low concentration source region 1b, a low concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e are formed. On the upper layer side of the semiconductor layer 1a, a gate insulating film 2 for insulating the semiconductor layer 1a from the scanning lines 3a is formed.
Here, the semiconductor layer 1a is composed of the single-crystal silicon layer 220b formed by the method described above.
[0066]
On the surface side of the MIS transistor 30 thus configured, interlayer insulating films 4 and 7 made of a silicon oxide film are formed. A data line 6a is formed on the surface of the interlayer insulating film 4, and the data line 6a is electrically connected to the high-concentration source region 1d via a contact hole formed in the interlayer insulating film 4. On the surface of the interlayer insulating film 7, a pixel electrode 9a made of an ITO film is formed. The pixel electrode 9a is electrically connected to the high-concentration drain region 1e via contact holes formed in the interlayer insulating films 4, 7 and the gate insulating film 2. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a. The alignment film 16 is a film obtained by performing a rubbing process on a polyimide film.
[0067]
Further, the capacitance of the same layer as the scanning line 3a is provided to the extension 1f (lower electrode) from the high-concentration drain region 1e via an insulating film (dielectric film) formed simultaneously with the gate insulating film 2a. The storage capacitor 70 is formed by the line 3b facing the upper electrode.
[0068]
The MIS transistor 30 preferably has an LDD structure as described above, but has an offset structure in which impurity ions are not implanted into regions corresponding to the low-concentration source region 1b and the low-concentration drain region 1c. May be. The MIS transistor 30 is a self-aligned TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting high-concentration impurity ions using the gate electrode (part of the scanning line 3a) as a mask. May be. In this embodiment, the MIS transistor 30 has a single gate structure in which only one gate electrode (scanning line 3a) is arranged between the source and drain regions. However, two or more gate electrodes are arranged between these. May be. At this time, the same signal is applied to each gate electrode. When the MIS transistor 30 is formed of a dual gate (double gate) or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current at the time of off can be reduced. I can do it. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced and a stable switching element can be obtained.
[0069]
The active matrix substrate 10 and the opposing substrate 20 thus configured are arranged so that the pixel electrode 9a and the opposing electrode 21 face each other, and the sealing material 53 (see FIGS. A liquid crystal 50 as an electro-optical material is sealed in a space surrounded by (see FIG. 5) and sandwiched. The liquid crystal 50 assumes a predetermined alignment state by the alignment film in a state where no electric field is applied from the pixel electrode 9a. The liquid crystal 50 is composed of, for example, one or a mixture of several types of nematic liquid crystals.
[0070]
The type of liquid crystal 50 to be used, that is, an operation mode such as a TN (twisted nematic) mode, an STN (super TN) mode, or the like, is provided on the light incident side surface or the light emission side of the counter substrate 20 and the active matrix substrate 10. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to the normally white mode / normally black mode.
[0071]
(Configuration of drive circuit)
Referring to FIG. 4 again, in the liquid crystal device 100 of the present embodiment, the data line driving circuit 101 and the scanning line driving circuit 104 (peripheral circuits) are formed by utilizing the peripheral area of the image display area 10 a on the front side of the active matrix substrate 10. Is formed. Such a data line driving circuit 101 and a scanning line driving circuit 104 are basically constituted by an N-channel MIS transistor and a P-channel MIS transistor shown in FIGS.
[0072]
FIG. 9 is a plan view showing a configuration of a MIS transistor which forms a peripheral circuit such as the scanning line driving circuit 104 and the data line driving circuit 101. FIG. 10 is a cross-sectional view of the MIS transistor constituting the peripheral circuit taken along the line BB 'in FIG. FIG. 10 also shows a pixel switching MIS transistor 30 formed in the image display area 10a of the active matrix substrate 10.
[0073]
9 and 10, the MIS transistor constituting the peripheral circuit is configured as a complementary MIS transistor including a P-channel MIS transistor 80 and an N-channel MIS transistor 90. The semiconductor layers 60 (contours are indicated by dotted lines) constituting the MIS transistors 80 and 90 for these drive circuits are formed in an island shape via the interlayer insulating film 12 formed on the bonded substrate 600. .
[0074]
In the MIS transistors 80 and 90, a high potential line 71 and a low potential line 72 are electrically connected to the source region of the semiconductor layer 60 via contact holes 63 and 64, respectively. The input wiring 66 is connected to a common gate electrode 65, and the output wiring 67 is electrically connected to the drain region of the semiconductor layer 60 via contact holes 68 and 69, respectively.
[0075]
Since such a peripheral circuit region is also formed through the same process as that of the image display region 10a, the interlayer insulating films 4, 7 and the gate insulating film 2 are also formed in the peripheral circuit region. The MIS transistors 80 and 90 for the driving circuit also have an LDD structure, like the MIS transistor 30 for pixel switching, and the high concentration source regions 82 and The semiconductor device includes a source region 92 and low-concentration source regions 83 and 93, and a drain region including high-concentration drain regions 84 and 94 and low-concentration drain regions 85 and 95.
Note that, like the semiconductor layer 1a, the semiconductor layer 60 is composed of the single-crystal silicon layer 220b formed by the method described above.
[0076]
(Method of manufacturing active matrix substrate)
The active matrix substrate 10 having such a configuration is manufactured using the composite semiconductor substrate (laminated substrate) 600 manufactured in the first embodiment. However, in the present embodiment, as described below, the light shielding film 11a (see FIG. 8) is formed inside the bonded substrate 600.
[0077]
11 to 13 are process cross-sectional views illustrating a method of manufacturing the active matrix substrate 10 of the present embodiment.
In this embodiment, first, the composite semiconductor substrate 600 in the state shown in FIG. 3D, that is, the composite semiconductor substrate 600 shown in FIG. 11A is prepared. Here, in FIG. 11A, the scale is changed from that in FIG. 3D and the dimensions of the main parts are changed for convenience of explanation. In the composite semiconductor substrate 600 shown in FIG. 11A, the light-shielding film 11a is formed in the insulating layer 12 (the insulating layer 500 in FIG. 3D), and further formed by the above-described method. A semiconductor layer 1a made of the single-crystal silicon layer 220b and the semiconductor layer 60.
[0078]
The semiconductor layer 1a and the semiconductor layer 60 are formed to have different thicknesses by adjusting the respective degrees of sacrificial oxidation. The semiconductor layer 1a forming the MIS transistor 30 for pixel switching and the semiconductor layer 60 forming the MIS transistors 80 and 90 for the drive circuit are formed in an island shape by the plurality of single crystal silicon patterns 220b. are doing. Here, the semiconductor layer 1a constituting the MIS transistor 30 for pixel switching is a single crystal silicon layer having a thickness of 100 nm or less, and the semiconductor layer 60 constituting the MIS transistors 80 and 90 for the driving circuit is The single-crystal silicon layer has a thickness of about 200 to 500 nm.
[0079]
As shown in FIG. 11B, a gate insulating film 2 made of a silicon oxide film is formed on the surfaces of the semiconductor films 1a and 60 by using a thermal oxidation method or the like on the composite semiconductor substrate 600 thus formed. I do. Although not shown, impurity ions are implanted into the extended portion 1f of the semiconductor film 1a through a predetermined resist mask to form a lower electrode for forming the storage capacitor 70 with the capacitor line 3b. .
[0080]
Next, a polycrystalline silicon film, a molybdenum film, a tungsten film, a titanium film, a cobalt film, or a polycrystalline silicon film for forming the scanning lines 3a, the capacitance lines 3b, and the gate electrodes 65 over the entire surface of the substrate by a CVD method or the like. After a conductive film made of a metal silicide film is formed to a thickness of about 350 nm, as shown in FIG. 11C, patterning is performed by using a photolithography technique to form a scanning line 3a, a capacitor line 3b, and a gate electrode. Form 65.
[0081]
Next, as shown in FIG. 12A, with the semiconductor layer 60 for forming the MIS transistor 80 for the P-channel drive circuit covered with the resist mask 301, the MIS transistor for pixel switching is used. The semiconductor layer 1a forming the semiconductor layer 30 and the semiconductor layer 60 forming the MIS transistor 90 for the N-channel type driving circuit are divided into about 0.1 × 10 ¹³ A low-concentration source region 1b, 93 and a low-concentration drain are implanted in a self-aligned manner with respect to the scanning line 3a by implanting low-concentration impurity ions (phosphorous ions) at a dose of about 10 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ^2. Regions 1c and 95 are formed. Here, since it is located immediately below the scanning line 3a, the portion where the impurity ions are not introduced becomes the channel regions 1a 'and 91 as the semiconductor film 1a.
[0082]
Next, as shown in FIG. 12B, a resist wider than the scanning line 3a and the gate electrode 65 and covering the semiconductor layer 60 for forming the MIS transistor 80 for the P-channel drive circuit is formed. A mask 302 is formed, and in this state, high-concentration impurity ions (phosphorous ions) are implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ^{2 to form} a high-concentration source region 1b, 92 and drain regions 1d and 94 are formed.
[0083]
Although not shown, a semiconductor for forming a MIS transistor 80 for a P-channel drive circuit using the gate electrode 65 as a mask in a state of covering the sides of the N-channel MIS transistors 30 and 90. After boron ions are implanted into the layer 60 at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ^2, a mask wider than the gate electrode 65 is formed. The semiconductor layer 60 for forming the MIS transistor 80 for the P-channel drive circuit is doped with a high concentration of impurity (boron ion) from about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm. by implanting at ² dose, as shown in FIG. 12 (C), to form a lightly doped source region 83, a lightly doped drain region 85 and channel region 81, a high concentration A source region 82 and a drain region 84 are formed.
[0084]
Next, an interlayer insulating film 4 made of a silicon oxide film or the like is formed on the surface side of the scanning line 3a by a CVD method or the like, and thereafter, contact holes are respectively formed by using a photolithography technique.
[0085]
Next, as shown in FIG. 13A, an aluminum film, a titanium nitride film, a titanium film, or a metal thereof for forming a data line 6a (source electrode) or the like is formed on the surface of the interlayer insulating film 4. A conductive film made of an alloy film containing any one of the above as a main component is formed to a thickness of about 350 nm by a sputtering method or the like, and then patterned by photolithography to form a data line 6a, a high potential line 71, and a low potential line. The line 72, the input wiring 66, and the output wiring 67 are formed. As a result, in the peripheral circuit region, P-channel and N-channel MIS transistors 80 and 90 are completed.
[0086]
Next, as shown in FIG. 13B, an interlayer insulating film 5 made of a silicon nitride film or a silicon oxide film is formed on the surface side of the data line 6a or the like by a plasma CVD method or the like. Then, a contact hole is formed in the interlayer insulating film 5.
Next, as shown in FIGS. 8 and 10, the pixel electrode 9a is formed in a predetermined pattern, and thereafter, the alignment film 16 is formed. As a result, the active matrix substrate 10 is completed.
[0087]
[Application to electronic equipment]
Next, a projection type liquid crystal display device will be described as an example of an electronic apparatus including the electro-optical device with reference to FIGS.
First, FIG. 14 is a block diagram illustrating a configuration of an electronic apparatus including the liquid crystal device 100 configured similarly to the electro-optical device according to each of the above embodiments.
[0088]
In FIG. 14, the electronic device includes a display information output source 1000, a display information processing circuit 1002, a driving circuit 1004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk, a tuning circuit that tunes and outputs an image signal of a television signal, and the like, and a clock generation circuit 1008. , And processes the image signal in a predetermined format on the basis of the clock signal from the display control circuit 1002. The display information output circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and is input based on a clock signal. Digital signals are sequentially generated from the display information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the driver circuit 1004 may be formed over an active matrix substrate included in the liquid crystal device 100. In addition, the display information processing circuit 1002 may be formed over the active matrix substrate.
[0089]
As an electronic device having such a configuration, a projection type liquid crystal display device (liquid crystal projector) described with reference to FIG. 15 can be given.
[0090]
In the projection type liquid crystal display device 1100 shown in FIG. 15, three liquid crystal modules including the liquid crystal device 100 in which the drive circuit 1004 is mounted on an active matrix substrate are prepared, and RGB light valves 100R, 100G, and 100B are respectively provided. It is configured as a projector used as a projector. In this liquid crystal projector 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light corresponding to the three primary colors of R, G, and B is generated by three mirrors 1106 and two dichroic mirrors 1108. The components are separated into components R, G, and B (light separating means) and guided to corresponding light valves 100R, 100G, and 100B (liquid crystal device 100 / liquid crystal light valve). At this time, since the light component B has a long optical path, the light component B is guided through a relay lens system 1121 including an input lens 1122, a relay lens 1123, and an output lens 1124 in order to prevent light loss. The light components R, G, and B corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are incident on a dichroic prism 1112 (light combining means) from three directions, are combined again, and then are formed into a projection lens. The image is projected as a color image on a screen 1120 or the like via 1114.
[0091]
The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the specific structure of the liquid crystal device described as an embodiment is merely an example, and the present invention can be applied to liquid crystal devices having various other structures. Also, for example, the present invention relates to an electro-optical device using various electro-optical elements using electroluminescence (EL), digital micro-mirror device (DMD), or plasma emission or fluorescence by electron emission, and the electro-optical device. It is needless to say that the present invention can also be applied to an electronic device having.
In addition, the single crystal semiconductor layer in the present invention is not limited to single crystal silicon, and for example, single crystal germanium or the like can be used.
[Brief description of the drawings]
FIGS. 1A to 1E are process cross-sectional views of a manufacturing method according to the present invention.
FIGS. 2A to 2C are process cross-sectional views of a manufacturing method according to the present invention.
FIGS. 3A to 3D are process cross-sectional views of a manufacturing method according to the present invention.
FIG. 4 is a plan view of the liquid crystal device according to the present invention as viewed from the counter substrate side.
FIG. 5 is a sectional view taken along line HH ′ of FIG. 4;
FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like formed in a plurality of pixels.
FIG. 7 is a plan view illustrating a configuration of each pixel.
8 is a cross-sectional view taken along a position corresponding to line AA 'in FIG.
FIG. 9 is a plan view of a circuit formed in a peripheral area of an image display area.
10 is a cross-sectional view of the driving circuit transistor shown in FIG.
FIGS. 11A to 11C are process cross-sectional views of a method for manufacturing a liquid crystal device.
12A to 12C are process cross-sectional views of a method for manufacturing a liquid crystal device.
13A and 13B are process cross-sectional views of a method for manufacturing a liquid crystal device.
FIG. 14 is a block diagram illustrating a circuit configuration of an electronic device.
FIG. 15 is a cross-sectional view of a projection electro-optical device as an example of an electronic apparatus.
[Explanation of symbols]
100: liquid crystal device (electro-optical device),
200: single crystal silicon substrate (semiconductor substrate),
210: silicon oxide film (insulating layer),
220, 220b ... single crystal silicon layer (single crystal semiconductor layer),
220a: a thin single-crystal silicon layer,
220c: single crystal silicon pattern, 225: thermal oxide film 230: element non-formation area (predetermined area), 240: element formation area,
500: support substrate, 510: oxide film (insulating layer), 550: insulating layer,
600: Composite semiconductor substrate (laminated substrate)

Claims (10)

A method for manufacturing a composite semiconductor substrate obtained by attaching a semiconductor substrate having a single crystal semiconductor layer to a supporting substrate,
Bonding the semiconductor substrate on the support substrate to form a bonded substrate;
Thinning a predetermined region of the single crystal semiconductor layer in the bonded substrate by etching,
Heat treating the bonded substrate after reducing the thickness of the predetermined region,
A method for manufacturing a composite semiconductor substrate, comprising: Between the step of bonding the support substrate and the semiconductor substrate to form a bonded substrate, and the step of thinning the predetermined region of the bonded substrate by etching, the semiconductor substrate of the bonded substrate is 2. The method according to claim 1, further comprising a step of reducing the thickness of the single crystal semiconductor layer by separating the single crystal semiconductor layer in a thickness direction. After the step of heat-treating the bonded substrate, further comprising a thermal oxidation step of thermally oxidizing the single crystal semiconductor layer in the bonded substrate,
The thinning of the predetermined region in the single crystal semiconductor layer is performed so that the thickness of the thinned single crystal semiconductor layer in the predetermined region is entirely consumed by the thermal oxidation process. Item 3. The method for manufacturing a composite semiconductor substrate according to Item 1 or 2. In the step of thinning the single crystal semiconductor layer in the bonded substrate by etching, a region other than a region where an element is formed in the single crystal semiconductor layer is thinned. 3. The method for manufacturing a composite semiconductor substrate according to any one of 3. The method for manufacturing a composite semiconductor substrate according to claim 1, wherein the heat treatment of the bonded substrate after the predetermined region is thinned is performed at a temperature of 700 ° C. or more and 1200 ° C. or less. . The method according to claim 1, wherein the single-crystal semiconductor layer is made of single-crystal silicon. The method according to claim 1, wherein the support substrate is a translucent substrate. A composite semiconductor substrate obtained by the manufacturing method according to claim 1. An electro-optical device comprising the composite semiconductor substrate according to claim 8. An electronic apparatus comprising the electro-optical device according to claim 9.

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