JPH05273591A - Liquid crystal image display device and production of semiconductor optical member - Google Patents

Abstract

PURPOSE:To improve image quality by removing the light opaque substrate below a liquid crystal image part so that light can be transmitted to liquid crystal picture element parts. CONSTITUTION:A porous Si base body 18 is fully etched by a selective etching liquid for porous Si and only the porous Si is subjected to electroless wet chemical etching to allow a single crystalline Si layer 19 formed as a thin film to remain on insulating layers 21, 22. The entire part is then coated with an etching preventive film 23 without the region of the rear surface to be formed transparent to light and thereafter, the Si base body 20 or the Si base body 20 and the insulating layers 21, 22 are removed by etching until the insulating surface of the insulating layer 21 or the single crystal plane of the single crystalline Si layer 19 is exposed from the apertures. After the etching preventive film 23 is peeled, the single crystalline Si layer 19 equal to a silicon wafer in the crystallinity is flatly and uniformly formed as a thin layer on the Si base body 20 and insulating layers 21, 22 which are partly formed transparent to light. This single crystalline Si layer is thus formed over the entire area of the wafer to a large area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical member having a light-transmitting portion and a liquid crystal image display device using the member, and in addition to the liquid crystal image display device, an image sensor, a viewfinder, an X-ray exposure mask, a pressure sensor. The present invention relates to a method for manufacturing a semiconductor optical member applied to sensors, micromechanics and the like.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is a bulk S for manufacturing a normal Si integrated circuit.
Much research has been done because devices utilizing SOI technology have numerous advantages that cannot be reached with i substrates. That is, by using the SOI technology ,. Dielectric isolation is easy and high integration is possible. Excellent radiation resistance ,. Stray capacitance is reduced and high speed is possible. The well process can be omitted ,. Latch-up can be prevented ,. Advantages such as a fully depleted field effect transistor can be obtained by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. This content is, for example, Special Issue: “Single-
crystal silicon on non-si
single-crystal insulators ”;
edited by G.E. W. Cullen, Jour
nal of Crystal Growth, vol
ume 63, no 3, pp 429-590 (198)
3). Are summarized in.

[0004] On old days, on a single crystal sapphire substrate
Heteroepitaxy of Si by CVD (chemical vapor deposition)
SOS (silicon on sapphire) formed by seeing
Is known as one of the most mature SOI technologies.
Although successful, the Si layer and underlying sapphire substrate interface
A large number of crystal defects due to the lattice mismatch of the sapphire substrate
Mixing aluminum into the Si layer, and above all
Due to the high cost of the substrate and the delay in increasing the area, its application is wide
Rough is blocked. In relatively recent years, sapphire groups
There is an attempt to realize an SOI structure without using the body.
It has been made. This attempt is roughly divided into the following two. (1) After the surface of the Si single crystal substrate is oxidized, a window is opened to make Si
Partially expose the substrate and use that part as a seed
Epitaxial growth toward SiO₂ Single crystal Si
The technique of forming layers. (2) Use the surface of the Si single crystal substrate itself as the active layer.
Used under the SiO ₂ Technology to form.

As means for realizing the above (1), CVD
Method for directly epitaxially growing single crystal layer Si in the lateral direction, a method for depositing amorphous Si and performing solid phase lateral epitaxial growth by heat treatment, electron beam or laser light on the amorphous or polycrystalline Si layer. Of a single crystal layer on SiO ₂ by melting and recrystallizing by irradiating a focused energy beam such as a laser beam, and a method of scanning the melting region in a band shape by a rod heater (Zone mel).
Ting recrystallization is known. Each of these methods has merits and demerits, but there are still many problems in controllability, productivity, uniformity, and quality, and none of them has been industrially put into practical use. For example, the CVD method requires sacrificial oxidation to obtain a flat thin film, and the solid phase growth method has poor crystallinity. Further, the beam annealing method has problems in processing time by convergent beam scanning, controllability such as beam overlapping and focus adjustment. Of these, Zone Melting R
Although the crystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped, many crystal defects such as sub-grain boundaries still remain, leading to the production of minority carrier devices. Absent. Further, since neither method requires a Si substrate, a good quality single crystal Si layer cannot be obtained on a transparent amorphous insulator substrate such as glass.

In the above method (2) in which the Si substrate is not used as seeds for epitaxial growth, there are the following three types of methods.

[0007]. An oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film to be as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is a method for forming a dielectrically separated Si single crystal region surrounded by a V groove on a thick polycrystalline Si layer. Although this method has good crystallinity, it requires a step of depositing polycrystalline Si to a thickness of several hundreds of μm and a step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer. Therefore, there is a problem in terms of controllability and productivity.

[0008] SIMOX: Sepe
relation by ion implemented o
xygen) is a method of forming a SiO ₂ layer by ion implantation of oxygen into a Si single crystal substrate, and is the most mature method at present because it has good compatibility with the Si process. However, in order to form the SiO ₂ layer,
Oxygen ions need to be implanted at 10 ¹⁸ ions / cm ² or more, the implantation time is long, the productivity cannot be said to be high, and the wafer cost is high. Furthermore, many crystal defects remain, and from an industrial point of view, the quality is not sufficient to produce a minority carrier device.

[0009]. This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method is
Ion implantation of an N-type Si layer on the surface of a Si-type Si single crystal substrate (Imai et al., J. Crystal Growth, v.
63, 547 (1983)), or is formed into an island shape by epitaxial growth and patterning, and only the P-type Si substrate is made porous by an anodization method in a HF solution so as to surround the Si island from the surface. This is a method of dielectrically separating N-type Si islands by accelerated oxidation. This method has a problem that the separated Si region is determined before the device process, which may limit the degree of freedom in device design.

By the way, forming a semiconductor element on a light-transmitting substrate is performed by a contact sensor which is a light receiving element,
It is important in constructing a projection type liquid crystal image display device. Further, in order to further increase the density, resolution, and definition of pixels (pixels) of a sensor or a display device, a high-performance driving element is required. In addition, the number of terminals of the switching element for switching the pixel and its drive circuit and peripheral circuit becomes enormous, and the connection between them after making them separately becomes a density that is no longer possible by mechanical connection. As a result, it is desirable that the semiconductor device and the peripheral drive circuit are formed in the same substrate by the same process, and the mutual connection is performed in a normal integrated circuit. In addition, it should be formed by patterning a conductive thin film, and only then can high-density mounting be possible. Further, from the inevitable industrial demand for higher performance of the product to be produced, it is necessary to produce it by using a single crystal layer having excellent crystallinity even as an element provided on a translucent substrate.

However, on a light-transmissive substrate typified by glass, in general, only a polycrystalline layer is formed, which is amorphous, or at best, reflecting the disorder of the crystal structure, and defects of the defects are formed. It has been difficult to produce a driving element having sufficient performance that is required or will be required in the future with many crystal structures. This is because the crystal structure of the substrate is amorphous, and a simple single crystal layer cannot provide a good-quality single crystal layer. Any of the above-mentioned methods using a Si single crystal substrate is unsuitable for the purpose of obtaining a good quality single crystal layer on a light transmissive substrate.

A transparent substrate represented by glass and Si
Attempt to create a single-crystal thin film Si on a transparent substrate by laminating with a substrate and thinning Si by polishing (Abe, Kuwahara, Nakazato, Uchiyama, Yoshizawa, IEICE technical research report, SDM90-156, 77 (199
0)) is present, but there is no successful case because the difference in thermal expansion coefficient between the two is one digit.

Therefore, a liquid crystal display device provided with an active matrix element, which has been commercialized as a flat panel display or a projection television, has been known as a thin film transistor in which an amorphous or polycrystalline Si semiconductor layer is formed on a glass substrate. (TFT) was used.

FIG. 1 is a schematic diagram for explaining a conventionally used active matrix type liquid crystal display device. 1 is a pixel switch, 5 is a liquid crystal pixel, 6 is a transparent substrate,
Reference numeral 2 is a buffer unit, 3 is a horizontal shift register unit, and 4 is a vertical shift register unit. The luminance signal and the audio signal of the television are compressed into a certain band and sent to the buffer unit 2 which is driven by the horizontal shift register 3 having a driving capability capable of following the frequency. Next, a signal is transferred to the liquid crystal while the pixel switch 1 is ON by the vertical shift register 4.

Considering a high-definition television in consideration of the performance required for each circuit, the frame frequency is 60 Hz, the number of scanning lines is about 1000, the horizontal scanning period is about 30 μsec (effective scanning period 27 μsec), the number of horizontal pixels is about 1500, Then, the television signal is transferred to the buffer section at a frequency of about 45 MHz. Further, the period allowed for signal transfer per scanning line is 1 to 2 μsec. Therefore, as the performance required for each element circuit, the driving capacity of the horizontal shift register is 45 MHz or more. The driving capability of the vertical shift register is 500 kHz or more. The transfer switch, which is driven by the horizontal shift register and transfers the television signal to the buffer, has a drive capacity of 4
5MHz or more. The drive capacity of the pixel switch is 500 kHz or more. Becomes The drive capability referred to here is obtained from a voltage Vm, VT (voltage-transmittance) curve that gives the maximum or minimum transmittance of the liquid crystal when the number N of gradations in the liquid crystal pixel is to be obtained. When the threshold voltage of the liquid crystal is Vt, it means that a voltage of Vm- (Vm-Vt) / N [V] or more is transferred within the above period.

As is apparent from this, the pixel switch,
Also, the vertical shift register may have a relatively small driving capability, but the horizontal shift register and the buffer unit are
High speed drive is required. For this reason, in the current liquid crystal display element, the pixel switch and the vertical shift register are formed of polycrystalline Si or amorphous SiT deposited on the glass substrate.
It is formed monolithically with the liquid crystal by FT, and other peripheral circuits are supported by mounting the IC chip from the outside.

In this case, in order to obtain a bright display image, the amount of light transmitted through the liquid crystal pixel portion must be increased.
On the other hand, in order to mount an IC chip, the glass substrate must have a certain strength or more, and a glass substrate having a large thickness was used. Therefore, sufficiently increasing the amount of transmitted light and using a thick glass substrate has been a cause of increasing the manufacturing cost. According to the knowledge of the present inventors, it has been found that the transparent portion of the substrate under the liquid crystal pixel portion needs to be thin and have high light transmittance and have sufficient mechanical strength.

Moreover, such a configuration is applicable not only to liquid crystal image display devices but also to semiconductor optical members such as contact image sensors, X-ray masks or viewfinders, pressure sensors, and micromechanics. It turned out.

On the other hand, with the polycrystalline silicon TFT,
Attempts have been made to form the peripheral circuits in a monolithic manner, but because the driving capability of each TFT is small,
It is necessary to increase the transistor size and to make complicated circuit arrangements.

[0020]

In order to further increase the density, resolution, and definition of pixels (picture elements) of a display device, a high-performance driving element is required. In addition, the number of terminals of the switching element for switching the pixel and its drive circuit and peripheral circuit becomes enormous, and as described above, mutual connection after the two are separately created is no longer mechanical connection (wire bonding, Bump connection, etc.) makes the density impossible. As a result, the semiconductor element and the peripheral drive circuit undergo the same process in the same substrate,
It is desirable to make them, and the connection between them should be made by patterning a conductive thin film as is done in a usual integrated circuit process, which enables high-density mounting for the first time. It will be. Furthermore, due to the inevitable industrial demand for higher performance of products to be created, it is necessary to use a single crystal layer having the best crystallinity as an element provided on a transparent substrate. ..

Therefore, it is very difficult to produce a driving element having sufficient performance required or expected in the future due to the crystal structure having many defects in amorphous Si and polycrystalline Si.

In order to obtain a high-performance liquid crystal image display device, in addition to the above-mentioned technical problems of the substrate, the present inventors have arranged the switching element of the liquid crystal pixel section and the semiconductor element of the peripheral circuit. I realized that I had to design the structure of and from a new point of view.

[0023]

A first object of the present invention is to provide a liquid crystal image having a high quality single crystal semiconductor layer on the same substrate which can meet the above problems and the above requirements. It is to provide a display device.

A second object of the present invention is a liquid crystal image display device formed on a substrate which is opaque to light in the visible light region, wherein the non-light permeable substrate below the liquid crystal image part is removed. And a liquid crystal image display device capable of transmitting light to the liquid crystal pixel portion.

A third object of the present invention is to provide a liquid crystal image display device having a substrate and a liquid crystal pixel portion formed on the substrate, and a portion of the substrate below the liquid crystal pixel portion is transparent. In the manufacturing method, after the liquid crystal pixel portion is formed on the light-transmissive insulating layer formed on the non-translucent substrate, a part of the substrate below the liquid crystal pixel portion is removed by etching. Another object of the present invention is to provide a method for manufacturing a liquid crystal image display device that allows light to enter the liquid crystal pixel portion.

A fourth object of the present invention is to bond the surface side of the single crystal semiconductor layer formed on the porous first substrate to the insulating surface side on the non-translucent second substrate. A step of removing the first substrate by a treatment including wet etching, and a region where light is incident on the single crystal semiconductor layer from the second substrate side by removing a part of the second substrate. To provide a method for manufacturing a semiconductor optical member having a transparent portion and a non-transparent portion.

Another object of the present invention is a liquid crystal image display device comprising at least two semiconductor elements having an active layer made of a single crystal semiconductor on a substrate having an insulating surface, wherein the at least two semiconductor elements are provided. Is to provide a liquid crystal image display device having active layers having different layer thicknesses.

The liquid crystal image display device of the present invention has a single crystal layer in which an active region of a semiconductor active element is formed and a liquid crystal layer on the surface of a substrate whose surface is formed of a translucent insulating layer. It is preferable that the substrate below the liquid crystal layer is removed from the opposite side of the liquid crystal layer until it reaches the translucent insulating layer so that light can be transmitted to the liquid crystal layer.

In addition, the liquid crystal image display device of the present invention is S
An Si single crystal layer in which an active region of an i semiconductor active element is formed, and a liquid crystal layer are provided on the surface of a Si substrate whose surface is formed of a translucent insulating layer, and the Si substrate below the liquid crystal layer. Is preferably removed from the opposite side of the liquid crystal layer until it reaches the transparent insulating layer so that visible light can pass through the liquid crystal layer.

Another liquid crystal image display device of the present invention is
A Si single crystal layer in which an active region of a Si semiconductor active element is formed, and a liquid crystal layer, the surface of which is composed of a translucent insulating layer.
The liquid crystal, which is on the surface of the substrate and is below the liquid crystal layer, is removed from the opposite side of the liquid crystal layer until it reaches the translucent insulating layer, so that the liquid crystal layer can transmit visible light. In the image display device, the Si single crystal layer is formed on a porous Si semiconductor, and then the surface of the Si substrate is bonded onto the Si single crystal layer, and then the porous semiconductor layer is formed. It is preferably obtained by removing by etching.

As semiconductor active elements, field effect transistors, bipolar transistors, diodes,
An element such as a thyristor is preferably used.

The present invention uses a Si single crystal substrate which is excellent in economy, is uniform and flat over a large area, and has extremely excellent crystallinity. Since the above-mentioned semiconductor elements have reduced stray capacitance, high-speed operation is possible, and elements and circuits with excellent radiation resistance characteristics without latch-up phenomenon are integrated on the same substrate as the liquid crystal image display pixel. A high performance device can be provided.

According to the method for producing a semiconductor substrate of the present invention, the surface of the non-porous single crystal layer on the first porous Si substrate or the surface of the insulating layer formed on the non-porous single crystal layer is A step of bonding to a second Si substrate having an insulating layer on the surface, and a single crystal semiconductor on the bonded insulating layer after removing the porous first Si substrate by a process including at least wet chemical etching. A step of forming a layer and a part of the second Si base or a part of an insulating layer bonded to the second Si base are bonded from a surface side where the single crystal semiconductor layer is not formed. It is preferable to remove the insulating surface of the insulating layer or the single crystal surface of the single crystal semiconductor layer by a process including at least wet chemical etching until the exposed surface.

Further, the method for producing a semiconductor substrate of the present invention uses the surface of the non-porous single crystal layer on the porous first Si substrate or the surface of the insulating layer formed on the non-porous single crystal layer. A step of bonding to a second Si substrate having an insulating layer on the surface, and a single crystal on the bonded insulating layer after removing the porous first Si substrate by a process including at least wet chemical etching A step of forming a semiconductor layer,
Forming an electronic device in the single crystal semiconductor layer,
A part of the second Si substrate or a second S substrate including at least a part immediately below a region where the electronic device is formed.
At least part of the i substrate and the bonded insulating layer is exposed from the surface side where the single crystal semiconductor layer is not formed until the insulating surface of the bonded insulating layer or the single crystal surface of the single crystal semiconductor layer is exposed. And removing by a process including wet chemical etching.

Further, in the liquid crystal image display device of the present invention, the thickness of the substrate which is impermeable to light in the visible light region is about 60.
Since it is as thick as 0 μm, some measures have been taken to remove the lower part of the liquid crystal pixel portion with high accuracy. As will be described later, the angle between the slope and the membrane after the substrate is removed is preferably 55 ° to 90 °, more preferably 90 °. Further, it is preferable that the removal of the substrate is surely completed at the time when it reaches the membrane. However, since the substrate having anisotropic etching characteristics is used as the substrate in the present invention, it is possible to obtain accuracy at an angle of 55 ° or more. Good removal is possible.

The etching method is not particularly limited and a known method can be used, but chemical etching having a large selection ratio is preferable. Among them, wet etching is preferable because of its low cost, and dry etching, particularly RIE (reactive ion etching) is preferable because of its high anisotropy.

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a schematic view schematically showing an example of the manufacturing process of the liquid crystal image display device according to one embodiment of the present invention. In FIG. 1A, the substrate 7 is a non-translucent substrate,
Reference numeral 8 is a translucent insulating layer, and 9 is a semiconductor single crystal layer. This substrate structure is widely known as an SOI structure, and two semiconductor substrates are bonded together via an insulating layer to thin one substrate, which is suitable in that the insulating layer can be freely selected. ing. As shown in FIG. 2B, a pixel switching element, which is a semiconductor active element required for a liquid crystal image display device, is formed on the SOI substrate shown in FIG. 2A by using a known integrated circuit process technology. 10, the drive circuit 11, and the peripheral circuit 12 are created. After that, Figure 2
As shown in (c), the liquid crystal 14 is sealed using the cover glass 15 and the sealing material 13. Needless to say, an alignment film, a counter electrode, a filter, a polarizing plate and the like are required for this liquid crystal portion, but these are known technical matters and therefore omitted here. As it is, since the substrate is not transparent to visible light, it is not used as a projection type display device in which a light source is arranged on the back of the substrate. So, finally in Figure 2
As shown in (d), the non-translucent substrate 7, which is the lower part 16 of the liquid crystal pixel portion, is removed from the back surface up to the translucent insulating layer 8 to be substantially light transmissive, and a projection type liquid crystal image display device is produced. To do. It is also possible to fill the region 16 which is partially removed due to the request for improvement in mechanical strength or reliability with a transparent resin, spin-on glass or the like.

Further, in the liquid crystal image display device of the present invention, Si is formed in the transparent region obtained by removing the non-transparent substrate.
It is preferable to provide at least an N _x insulating layer to reinforce the mechanical strength of the portion and improve the reliability.

Examples of the method for forming the SiN _x insulating layer include sputtering, low pressure CVD, and plasma CVD. From the viewpoint of controllability, the low pressure CVD is preferable. The film structure may be provided in the upper layer film (protective film) of the device, the interlayer insulating film (inter-wiring film), or the base insulating film,
Moreover, you may provide in these multiple parts. Furthermore, SiN
It is also possible to control the strength by the film thickness and patterning of the _x insulating layer.

FIG. 3 is a schematic view schematically showing another example of the manufacturing process of the liquid crystal image display device according to the present invention. In FIG. 3A, the substrate 7 is a non-translucent substrate, 8 is a translucent insulating layer, and 9 is a semiconductor single crystal layer. This substrate structure is widely known as an SOI structure, and two semiconductor substrates are bonded together via an insulating layer to thin one substrate, which is suitable in that the insulating layer can be freely selected. ing. As shown in FIG. 3B, a pixel switching element, which is each semiconductor active element required for a liquid crystal image display device, is formed on the SOI substrate shown in FIG. 10 and the drive circuit 11,
The peripheral circuit 12 is created. After that, as shown in FIG. 3C, the liquid crystal 14 is sealed using the cover glass 15 and the sealing material 13. Needless to say, an alignment film, a counter electrode, a filter, a polarizing plate and the like are required for this liquid crystal portion, but these are well known technical matters and therefore omitted here. As it is, since the substrate is not transparent to visible light, it is not used as a projection type display device in which a light source is arranged on the back of the substrate. Therefore, as shown in FIG. 3D, the non-translucent substrate 7, which is the lower portion 16 of the liquid crystal pixel portion, is removed from the back surface up to the translucent insulating layer 8 to substantially transmit light, and further, the reinforcing layer. As SiN _x from the back surface to the transparent region
The insulating layer 17 is formed, and a projection type liquid crystal image display device is created.

In the display device described above, the layer thickness of the semiconductor active layer of the switching element 10 is set to the drive circuit 1
By making the thickness of the semiconductor active layer of the peripheral circuit 12 including 1 smaller than that of the semiconductor active layer, a high performance device can be obtained.

Now, the porous semiconductor used in the present invention will be described.

Porous Si as a porous semiconductor used in the present invention was discovered by Uhir et al. In 1956 in the course of research on electrolytic polishing of semiconductors (AU).
hril, Bell System. Tech. J. , Vo
35,333 (1956)). Also, Unami et al. Studied the dissolution reaction of Si in anodization, and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T ．Unagi:
J. Electrochem. Soc. , Vol. 12
7, 476 (1980)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + , e ^-, respectively, represent the holes and electrons. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

As described above, holes are required to form porous Si, and P-type Si is more easily transformed into porous Si than N-type Si. However, it is known that N-type Si is also transformed into porous Si if holes are injected (RP Holmstrom and JYC).
hi. Appl. Phys. Lett. Vol. 42,
386 (1983)).

This porous Si layer has a HF solution concentration of 50 to 2 as compared with the density of single crystal Si of 2.33 g / cm ^3.
By changing to 0%, its density is 1.1-0.6g
It can be changed in the range of / cm ³ . According to observation with a transmission electron microscope, pores having an average diameter of about 600 Å are formed in this porous Si layer. Although its density is less than half that of single crystal Si, single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on the upper part of the porous layer.

Generally, when a single crystal of Si is oxidized, its volume is increased by about 2.2 times. However, by controlling the density of porous Si, it is possible to suppress the volume expansion of the single crystal, which causes warpage of the substrate. It is possible to avoid cracks introduced into the surface residual single crystal layer. The volume ratio R of the single crystal Si after being oxidized to the porous Si can be expressed as follows.

R = 2.2 × (A / 2.33) where A is the density of porous Si. If R = 1,
That is, if there is no volume expansion after oxidation, A = 1.06
(G / cm ³ ) and the density of the porous Si layer is 1.06.
If so, volume expansion can be suppressed.

Further, since the porous layer has a large amount of voids formed therein, its density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly enhanced compared to the etching rate of the non-porous Si layer.

The present invention utilizes the properties of the porous Si layer described above, and is characterized in that the non-porous material having excellent crystallinity is formed on the porous first Si substrate. A single crystal Si layer is formed, or an insulating layer is further formed on the non-porous single crystal Si layer, and the surface of the non-porous single crystal Si layer or the surface of the insulating layer having the insulating layer on the surface is formed. Two
The Si substrate is bonded to the surface of the insulating layer, and then the porous first Si substrate is removed by a process including at least wet chemical etching to form a single crystal Si having excellent crystallinity on the bonded insulating layer. Forming a layer, and further forming a part of the second Si substrate or a part of the insulating layer bonded to the second Si substrate on a surface of the second Si substrate on which the single crystal Si layer is not formed. A continuous thin layer (single crystal Si layer) is removed by a process including at least wet chemical etching until the insulating surface of the bonded insulating layer or the Si single crystal surface of the single crystal Si layer is exposed from the (back surface). ) Is left without a support directly below.

Further, according to the present invention, after forming a single crystal Si layer having excellent crystallinity on the insulating layer bonded by the above-mentioned step, an electronic device is formed on this single crystal Si layer, and at least a part of the single crystal Si layer is formed. A part of the second Si substrate or a part of the insulating layer bonded to the second Si substrate, including a portion immediately below the region where the electronic device is formed, is replaced by a single crystal Si layer of the second Si substrate. A continuous thin layer is removed by a process including at least wet chemical etching until the insulating surface of the bonded insulating layer or the Si single crystal surface of the single crystal Si layer is exposed from the surface not formed (back surface). (Single crystal Si
Layer) is left without a support directly below, and at least just under a desired region of the single crystal Si layer in which the electronic device is formed can transmit light, and the non-translucent substrate is partially changed to a transmission type. is there.

According to the present invention, after the single crystal Si layer is formed on the non-translucent insulating substrate, the non-transparent substrate portion is removed only in a necessary region, so that the non-translucent substrate is formed on the non-transparent substrate. It becomes possible to partially irradiate light only on a necessary area of the formed single crystal Si layer, and easily, without using a translucent substrate typified by glass, productivity, uniformity, controllability, It is possible to create a light-transmissive SOI structure having a Si layer which is excellent in economic efficiency and has a crystallinity as excellent as that of a single crystal wafer.

First, an etching solution that can be preferably used in the present invention will be described.

4 to 11 show hydrofluoric acid, a mixed solution of hydrofluoric acid and alcohol, a mixed solution of hydrofluoric acid and hydrogen peroxide, and hydrofluoric acid for porous Si and non-porous Si respectively. Mixture of alcohol and hydrogen peroxide, buffered hydrofluoric acid, buffered hydrofluoric acid and alcohol, buffered hydrofluoric acid and hydrogen peroxide, and buffered hydrofluoric acid and alcohol. The etching characteristics by a mixed solution with hydrogen oxide water are shown respectively.

Porous Si was produced by anodizing single crystal Si, and the conditions are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure is also possible.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 hour: 2.4 (hour) Porous Si thickness: 300 (μm) Porosity: 56 (%) In FIG. 4, porous Si and non-porous single crystal Si are infiltrated in hydrofluoric acid, Etched porous Si when stirred
And shows the etching time dependence of the thickness of single crystal Si.

The porous Si prepared under the above conditions was immersed in 49% hydrofluoric acid (white circles) at room temperature and stirred. Later, the reduction in the thickness of the porous Si was measured. Porous Si
Is rapidly etched, 90 μm in about 40 minutes, and even 205 μm after 80 minutes have a high degree of surface property and are uniformly etched. The etching rate depends on the solution concentration and the temperature.

Further, 500 μm thick single crystal Si was infiltrated with 49% hydrofluoric acid (black circles) at room temperature and stirred. later,
The reduction in thickness of the single crystal Si was measured. Single crystal Si is
Even after 80 minutes, only less than 60Å was etched.

FIG. 5 shows the thickness of the etched porous Si and the single crystal Si when the porous Si and the non-porous single crystal Si were soaked in a mixed solution of hydrofluoric acid and alcohol without stirring. Shows the etching time dependence of.

The porous Si prepared under the above conditions was mixed at room temperature with a mixed solution of 49% hydrofluoric acid and alcohol (10:
1) (white circle) was infiltrated without stirring. Later, the reduction in the thickness of the porous Si was measured. Porous Si is rapidly etched, and 85 μm in about 40 minutes, and 80
After a lapse of minutes, it has a high surface property of 195 μm,
Etched uniformly. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, it is possible to instantly remove the bubbles of the reaction product gas from the etching from the etching surface without stirring, and to uniformly and efficiently etch the porous Si.

Further, 500 μm thick single crystal Si was mixed at room temperature with a mixed solution of 49% hydrofluoric acid and alcohol (10: 1).
(Black circle) was infiltrated without stirring. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 Å or less even after 80 minutes.

In FIG. 6, porous Si and non-porous single crystal Si are soaked in a mixed solution of hydrofluoric acid and hydrogen peroxide solution and stirred to obtain the etched porous Si and single crystal Si. The dependence of the etching time on the thickness is shown.

The porous Si prepared under the above conditions was immersed in a mixed solution (1: 5) of 49% hydrofluoric acid and 30% hydrogen peroxide solution (white circle) at room temperature and stirred. Later, the reduction in the thickness of the porous Si was measured. Porous Si is rapidly etched and has a high surface property of 112 μm in about 40 minutes and 256 μm in 80 minutes, and is evenly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with the case where no hydrogen peroxide solution is added. , Its reaction rate can be controlled.

Further, 500 μm thick single crystal Si was immersed in a mixed solution (1: 5) of 49% hydrofluoric acid and 30% hydrogen peroxide solution (black circle) at room temperature and stirred. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 Å or less even after 80 minutes.

FIG. 7 shows etched porous Si obtained by immersing porous Si and non-porous single crystal Si in a mixed solution of hydrofluoric acid, alcohol and hydrogen peroxide solution without stirring. The etching time dependence of the thickness of single crystal Si is shown.

The porous Si prepared under the above conditions was infiltrated at room temperature into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (white circle) without stirring. Later, the reduction in the thickness of the porous Si was measured. Porous Si is rapidly etched, and has a thickness of 106 μm in about 40 minutes and 244 μm in 80 minutes.
Also has a high degree of surface properties and is uniformly etched.
The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, the bubbles of the reaction product gas due to etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

Further, in particular, by adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with the case of no addition, and the ratio of hydrogen peroxide solution can be changed. Can control the reaction rate.

Further, 500 μm thick single crystal Si was infiltrated at room temperature into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (black circle) without stirring. Later, the decrease in the thickness of the single crystal Si was measured. The single crystal Si was etched only 60 Å or less even after 80 minutes. FIG. 8 shows the etching time dependence of the thickness of etched porous Si and single crystal Si when porous Si and non-porous single crystal Si were soaked in buffered hydrofluoric acid and stirred.

The porous Si prepared under the above conditions was buffered with hydrofluoric acid (4.5% HF + 36% NH 3) at room temperature.
₄ F + H ₂ O) (white circle) was infiltrated and stirred. Later, the reduction in the thickness of the porous Si was measured. Porous Si was rapidly etched, and 70 μm in about 40 minutes.
After 0 minutes, it has a high surface property of 140 μm and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

Further, 500 μm thick single crystal Si was buffered with hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O) (black circle) was infiltrated and stirred. Later, the decrease in the thickness of the single crystal Si was measured. Single crystal Si is 12
Even after 0 minutes, less than 100Å was etched.

FIG. 9 shows etched porous Si and single crystal Si when porous Si and non-porous single crystal Si are soaked in a mixed solution of buffered hydrofluoric acid and alcohol without stirring. Shows the etching time dependence of the thickness of.

The porous Si prepared under the above conditions was buffered with hydrofluoric acid (4.5% HF + 36% NH 3) at room temperature.
₄ F + H ₂ O) and alcohol mixture (10: 1)
(White circle) was infiltrated without stirring. Later, the reduction in the thickness of the porous Si was measured. Porous Si is rapidly etched and has a high surface property of 67 μm in about 40 minutes and 112 μm after 120 minutes, and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, the bubbles of the reaction product gas due to etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

In addition, 500 μm thick single crystal Si was buffered with hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
It was infiltrated into a mixed solution (10: 1) of F + H ₂ O) and alcohol (black circle) without stirring. Later, the single crystal S
The decrease in thickness of i was measured. The single crystal Si was etched only 100 Å or less even after 120 minutes.

In FIG. 10, porous Si and non-porous single crystal Si are soaked in a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution, and the porous Si and single crystal are etched when they are stirred. The etching time dependence of the thickness of Si is shown.

The porous Si prepared under the above conditions was buffered with hydrofluoric acid (4.5% HF + 36% NH 3) at room temperature.
₄ F + H ₂ O) and 30% hydrogen peroxide solution (1 :)
5) (white circle) was infiltrated and stirred. Later, the porous Si
The decrease in thickness was measured. Porous Si is rapidly etched and has a high surface property of 88 μm in about 40 minutes and 147 μm in 120 minutes, and is evenly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with no addition, and by changing the ratio of hydrogen peroxide solution. , Its reaction rate can be controlled.

Further, 500 μm-thick single crystal Si was buffered with hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O) and 30% hydrogen peroxide solution (1 :)
5) (black circle) was infiltrated and stirred. Later, the single crystal Si
The decrease in thickness was measured. The single crystal Si was etched only 100 Å or less even after 120 minutes.

FIG. 11 shows that the porous Si and the non-porous single crystal Si etched into the mixed solution of buffered hydrofluoric acid, alcohol and hydrogen peroxide solution without being stirred are the porous materials etched. The etching time dependence of the thickness of Si and single crystal Si is shown.

The porous Si prepared under the above conditions was buffered with hydrofluoric acid (4.5% HF + 36% NH 3) at room temperature.
₄ F + H ₂ O), alcohol and a 30% hydrogen peroxide solution (10: 6: 50) (white circles) were infiltrated without stirring. Later, the reduction in the thickness of the porous Si was measured. Porous Si is rapidly etched, 83 μm in about 40 minutes, and 140 μm in 120 minutes.
It has a high degree of surface property and is uniformly etched. The etching rate depends on the solution concentration and the temperature.

In particular, by adding alcohol, the bubbles of the reaction product gas due to etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

Further, in particular, by adding hydrogen peroxide water, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with the case where no hydrogen peroxide water is added. Can control the reaction rate.

Further, 500 μm thick single crystal Si was buffered with hydrofluoric acid (4.5% HF + 36% NH ₄₎ at room temperature.
F + H ₂ O), alcohol and a 30% aqueous hydrogen peroxide solution (10: 6: 50) (black circles) were infiltrated without stirring. Later, the decrease in the thickness of the single crystal Si was measured. Single crystal Si is 100Å even after 120 minutes
Only less than was etched.

When the porous Si and single crystal Si after etching with the above-described etching solution were washed with water and the surfaces thereof were microanalyzed by secondary ions, no impurities were detected.

The solution concentration of the hydrogen peroxide solution is 30% here, but it is set at a concentration that does not impair the effect of adding the hydrogen peroxide solution and is practically acceptable in the manufacturing process and the like.

The conditions of solution concentration and temperature are set within a range in which the effect of hydrofluoric acid, buffered hydrofluoric acid and the above-mentioned hydrogen peroxide solution or the above-mentioned alcohol is exhibited, and the etching rate is practically acceptable in the manufacturing process and the like.

In the present application, the case of the above-mentioned solution concentration and room temperature was taken up as an example, but the present invention is not limited to such conditions.

The HF concentration is set in the range of preferably 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The HF concentration in the buffered hydrofluoric acid is set within the range of preferably 1 to 95%, more preferably 1 to 85%, still more preferably 1 to 70% with respect to the etching solution. The NH ₄ F concentration in the acid is set within the range of preferably 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The H ₂ O ₂ concentration was
It is preferably 1 to 95%, more preferably 5 to 90%, still more preferably 10 to 80%, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% or less, more preferably 60% or less, still more preferably 40% or less with respect to the etching solution, and is set within a range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

As the alcohol used in the present invention, in addition to ethyl alcohol, isopropyl alcohol or the like which can be practically used in the manufacturing process and which is desired to have the above alcohol addition effect can be used.

Next, a method for epitaxially growing a single crystal after making the substrate porous will be described.

As shown in FIG. 12 (a), first, a Si single crystal substrate is prepared and anodized (An) using a HF solution.
The whole is made into a porous single-crystal Si substrate 18 by an oxidation method. Epitaxial growth is performed on the surface of the porous substrate by various growth methods to form the thin film single crystal layer 19.

As shown in FIG. 12B, another S
An i substrate 20 is prepared, an insulating layer 21 is formed on the surface thereof, and then an Si substrate having the insulating layer 21 on the surface is attached to the surface of the insulating layer 22 formed on the single crystal Si layer on the porous Si substrate. Put on. In this attaching step, the cleaned surfaces are brought into close contact with each other and then heated in an oxidizing atmosphere or a nitrogen atmosphere. The insulating layer 22 is the single crystal layer 19 which is the final active layer.
Is formed to reduce the interface state of
The insulating layer 22 is not always necessary for applications such as micromechanics in which the interface state is not a problem.

As shown in FIG. 12C, the entire porous Si substrate 18 is electrolessly wet-chemically etched only on the porous Si substrate by the selective etching liquid for the porous Si to form the insulating layers 21 and 22 on the insulating layers 21 and 22. The thin-film single crystal Si layer 19 is left and formed. By this step, the single crystal Si layer 19 having the crystallinity equivalent to that of the Si wafer is flattened and uniformly thinned on the Si substrate 20 via the insulating layers 21 and 22.
A large area is formed over the entire wafer.

Next, as shown in FIG. 12D, the etching prevention film 23 is formed on the entire surface except for the back surface region which is made transparent.
Then, the Si substrate 20 or the Si substrate 20 and the insulating layers 21 and 22 are removed by etching until the insulating surface of the insulating layer 21 or the single crystal surface of the single crystal Si layer 19 is exposed from the opening. FIG. 12 shows an example in which only the Si substrate 20 is removed by etching.

As shown in FIG. 12 (e), after the etching prevention film 23 is peeled off, a part of the transparent film S becomes transparent.
A single crystal Si layer 19 having a crystallinity equivalent to that of a silicon wafer is flatly and uniformly thinned on the i substrate 20 and the insulating layers 21 and 22 and is formed in a large area over the entire wafer.

A thin layer (Mem) on the surface of the translucent region
Brane) (single crystal Si layer, or single crystal Si layer and insulating layer) does not have a support immediately below.

A method for forming an electronic device on the single crystal semiconductor layer before the above-mentioned substrate is made transparent will be described.

First, as shown in FIG. 13A, a Si single crystal substrate is prepared and anodized (An) by using an HF solution.
The whole is made into a porous single-crystal Si substrate 18 by an oxidation method. Epitaxial growth is performed on the surface of the porous substrate by various growth methods to form the thin film single crystal layer 19.

As shown in FIG. 13 (b), another S
An i substrate 20 is prepared, an insulating layer 21 is formed on the surface thereof, and then an Si substrate having the insulating layer 21 on the surface is attached to the surface of the insulating layer 22 formed on the single crystal Si layer on the porous Si substrate. Put on. In this attaching step, the cleaned surfaces are brought into close contact with each other and then heated in an oxidizing atmosphere or a nitrogen atmosphere. The insulating layer 22 is the single crystal layer 19 which is the final active layer.
Is formed to reduce the interface state of
The insulating layer 22 is not always necessary for applications such as micromechanics in which the interface state is not a problem.

As shown in FIG. 13 (c), the entire porous Si substrate 18 is electroless wet-chemically etched only on the porous Si substrate by the selective etching liquid for the porous Si to form the insulating layers 21 and 22 on it. The thin-film single crystal Si layer 19 is left and formed. By this step, the single crystal Si layer 19 having the crystallinity equivalent to that of the silicon wafer is flattened and uniformly thinned on the Si substrate 20 via the insulating layers 21 and 22, and the entire area of the wafer is large. Formed in.

Here, as shown in FIG. 13D, an electronic device such as a transistor, a diode, a capacitor, a resistor, or an integrated circuit 24 thereof is formed on the single crystal Si layer 19.
To form.

Next, as shown in FIG. 13E, the etching prevention film 23 is formed on the entire surface except for the back surface region which is made transparent.
Then, the Si substrate 20 or the Si substrate 20 and the insulating layers 21 and 22 are removed by etching until the insulating surface of the insulating layer 21 or the single crystal surface of the single crystal Si layer 19 is exposed from the opening. The region to be translucent contained at least one electronic device. In FIG. 13, S
An example is shown in which only the i substrate 20 is removed by etching.

As shown in FIG. 13F, after the etching prevention film 23 is peeled off, a part of the film S becomes transparent.
The electronic device 24 is formed in the i-base 20 and the single crystal Si layer 19 on the insulating layers 21 and 22, and is transparent.

There is no support immediately below the thin layer (Membrane) (single crystal Si layer or single crystal Si layer and insulating layer) in which the electronic device is incorporated on the surface of the light-transmitting region. ..

Next, a method for forming a single crystal layer before making it porous and then selectively making only the substrate porous by anodization will be described.

First, as shown in FIG. 14A, a low impurity concentration layer 32 is formed by epitaxial growth by various thin film growth methods. Alternatively, the P-type Si single crystal substrate 31
An N-type single crystal layer 32 is formed by ion-implanting protons on the surface of.

Next, as shown in FIG. 14B, a P type S
The i single crystal base 31 is transformed from the back surface into a porous single crystal Si base 33 by an anodization method using an HF solution.

As shown in FIG. 14C, another S
An i substrate 34 is prepared, an insulating layer 35 is formed on the surface thereof, and then an Si substrate having the insulating layer 35 on the surface is attached to the surface of the insulating layer 36 formed on the single crystal Si layer on the porous Si substrate. wear. In this attaching step, the cleaned surfaces are brought into close contact with each other and then heated in an oxidizing atmosphere or a nitrogen atmosphere. The insulating layer 36 is the single crystal layer 32 which is the final active layer.
Is formed to reduce the interface state of
The insulating layer 36 is not always necessary for applications such as micromechanics in which the interface state is not a problem.

As shown in FIG. 14 (d), the entire porous Si substrate 33 is electroless wet-chemically etched only on the porous Si substrate by the selective etching solution for the porous Si to form the insulating layers 35 and 36. The thin-film single crystal Si layer 32 is left and formed. By this step, the single crystal Si layer 32 having the crystallinity equivalent to that of the silicon wafer is flattened and uniformly thinned on the Si substrate 34 via the insulating layers 35 and 36, and the whole area of the wafer is made large. It is formed.

Next, as shown in FIG. 14E, the etching prevention film 37 is entirely formed except for the back surface region which is made transparent.
Then, the Si substrate 34 or the Si substrate 34 and the insulating layers 35 and 36 are removed by etching until the insulating surface of the insulating layer 35 or the single crystal surface of the single crystal Si layer 32 is exposed from the opening. FIG. 14 shows an example in which only the Si substrate 34 is removed by etching.

As shown in FIG. 14F, after the etching prevention film 37 is peeled off, a part of the transparent film S becomes transparent.
A single crystal Si layer 32 having crystallinity equivalent to that of a silicon wafer is flatly and uniformly thinned on the i substrate 34 and the insulating layers 35 and 36, and is formed in a large area over the entire wafer.

A thin layer (Mem) on the surface of the translucent region
Brane) (single crystal Si layer, or single crystal Si layer and insulating layer) does not have a support immediately below.

Next, a method for forming an electronic device on the single crystal semiconductor layer before making the substrate transparent will be described.

First, as shown in FIG. 15A, a low impurity concentration 42 is formed by epitaxial growth by various thin film growth methods. Alternatively, protons are ion-implanted into the surface of the P-type Si single crystal substrate 41 to form the N-type single crystal layer 42.

Next, as shown in FIG. 15B, a P type S
The i single crystal substrate 41 is transformed from the back surface into a porous single crystal Si substrate 43 by an anodization method using an HF solution.

As shown in FIG. 15C, another S
An i substrate 44 is prepared, an insulating layer 45 is formed on the surface thereof, and then an Si substrate having the insulating layer 45 on the surface is attached to the surface of the insulating layer 46 formed on the single crystal Si layer on the porous Si substrate. wear. In this attaching step, the cleaned surfaces are brought into close contact with each other and then heated in an oxidizing atmosphere or a nitrogen atmosphere. The insulating layer 46 is the single crystal layer 42 which is the final active layer.
Is formed to reduce the interface state of
The insulating layer 46 is not always necessary for applications such as micromechanics in which the interface state is not a problem.

As shown in FIG. 15D, the porous Si substrate 43 is entirely electroless wet-chemically etched on only the porous Si by the selective etching liquid for the porous Si, so that the insulating layers 45 and 46 are formed. The thin-film single crystal Si layer 42 is left and formed. By this step, the single crystal Si layer 42 having the crystallinity equivalent to that of the silicon wafer is flattened and uniformly thinned on the Si substrate 44 via the insulating layers 45 and 46, and the whole area of the wafer is made large. It is formed.

Here, as shown in FIG. 15E, an electronic device such as a transistor, a diode, a capacitor, a resistor, or an integrated circuit 47 thereof is formed on the single crystal Si layer 42.
To form.

Next, as shown in FIG. 15F, the etching prevention film 48 is formed on the entire surface except for the back surface region which is made transparent.
Then, the Si substrate 44 or the Si substrate 44 and the insulating layers 45 and 46 are removed by etching until the insulating surface of the insulating layer 45 or the single crystal surface of the single crystal Si layer 42 is exposed from the opening. The region to be translucent contained at least one electronic device. In FIG. 15, S
An example is shown in which only the i substrate 44 is removed by etching.

As shown in FIG. 15 (g), after the etching prevention film 48 is peeled off, S is partially translucent.
The electronic device 47 is formed in the i-base 44 and the single crystal Si layer 42 on the insulating layers 45 and 46, and is also transparent.

There is no support immediately below the thin layer (Membrane) (single crystal Si layer or single crystal Si layer and insulating layer) in which the electronic device is incorporated on the surface of the light-transmitting region. ..

Next, another method for producing a semiconductor substrate will be described.

First, a Si single crystal substrate is prepared, and H
It is made porous by the anodization method using the F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate changes to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be made. This porous layer is for the reasons described above.
It is easily formed on a P-type Si substrate.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The conditions for making single crystal Si porous by anodization are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 hour: 2.4 (hour) Porous Si thickness: 300 (μm) Porosity: 56 (%) Si is epitaxially grown on the porous Si substrate thus formed to form a single crystal Si thin film. To form.
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after the surface of the single crystal Si thin film is oxidized, a substrate which will eventually form a substrate is prepared,
The oxide film on the surface of the single crystal Si and the above substrate are bonded together. Alternatively, after the surface of a newly prepared single crystal Si substrate is oxidized, it is attached to the single crystal Si layer on the porous Si substrate. The reason for providing this oxide film between the substrate and the single crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher than that of the glass interface. This is because the level can be made lower and the characteristics of the electronic device can be remarkably improved. However, in the present invention, since a semiconductor or a conductor is used for the substrate for controlling the back surface potential, the above oxide film is used. An isolating layer is required. Further, a single crystal S obtained by etching away the porous Si substrate by selective etching described later.
Only the i thin film may be attached to a new substrate. The bonding is so close that it cannot be easily peeled off by van der Waals force simply by contacting each surface at room temperature after cleaning.
C., preferably 600 to 900.degree. C., and heat-treated in a nitrogen atmosphere to complete bonding.

Further, a Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the above-mentioned two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed. Apiezon wax may be used instead of the Si ₃ N ₄ layer. Then, the porous Si substrate is entirely removed by a method such as etching to obtain a semiconductor substrate having a thin film single crystal Si layer.

A selective etching method for electroless wet etching only this porous Si substrate will be described.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, a buffered material such as hydrofluoric acid, ammonium fluoride (NH ₄ F) or hydrogen fluoride (HF) can be used. Hydrofluoric acid, a mixed solution of hydrofluoric acid containing hydrogen peroxide or buffered hydrofluoric acid, and hydrofluoric acid containing alcohol or a mixed solution of buffered hydrofluoric acid are preferably used. Etching is performed by moistening the substrate bonded to these solutions. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with the case of no addition, and the reaction rate can be increased by changing the ratio of hydrogen peroxide solution. Can be controlled. Further, by adding alcohol, it is possible to instantaneously remove the bubbles of the reaction product gas due to etching from the etching surface without stirring, and it is possible to uniformly and efficiently etch the porous Si.

The HF concentration in the buffered hydrofluoric acid is preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight, based on the etching solution.
The NH ₄ F concentration in the buffered hydrofluoric acid is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 5% by weight with respect to the etching solution.
It is set in the range of ~ 80% by weight.

The HF concentration is preferably set in the range of 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration is
The amount is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, further preferably 5 to 60 ° C.

As the alcohol used in this step, in addition to ethyl alcohol, isopropyl alcohol or the like which can be practically used in the manufacturing process and which is desired to have the above-mentioned alcohol addition effect can be used.

The thus obtained semiconductor substrate has a single crystal Si layer equivalent to that of an ordinary Si wafer, which is flat and uniformly thinned to have a large area over the entire substrate.

In the present invention, a liquid crystal display device is constructed by forming a circuit by a usual method using the substrate on which the single crystal Si layer is formed as described above.

In the present invention, the potential of the back electrode to be controlled is the off region of the parasitic transistor in which the supporting substrate is the gate electrode and the base insulating layer is the gate insulating film, and as shown in FIG. In the case where both and the NMOS transistor are used together, a portion where the off regions of both parasitic transistors overlap is adopted. Also,
The electrodes can be taken out by any means as long as they do not hinder the function of the display device.However, when using a semiconductor as the substrate and taking it out from the back surface of the substrate, it is possible to control by wiring through a metal electrode such as aluminum. Will be easier. Alternatively, the substrate may be taken out from the upper side as described later. In this way, when taken out from the upper side, wiring to the package side is easy, the size is reduced, and the assembly yield is improved.

The conductor substrate that can be used in the present invention is preferably a metal having a high melting point of 900 ° C. or higher because it is heat-treated and bonded when the single crystal Si thin film is formed. When a semiconductor substrate is used, a P-type or n-type Si substrate which is commonly used can be used.

In the present invention, the substrate of the image display portion is removed by etching from the back surface to make it transparent. Etching is S
It is desirable to use an etching solution that allows a sufficient ratio of i to the etching rate of the base insulating layer (10: 1 or more).
For example, when the most general SiO ₂ is used for the insulating layer, KOH or ethylenediamine aqueous solution is used as the etching solution. KHO is an aqueous solution of 10 to 70%, the liquid temperature is 50 to 120 ° C., preferably KOH 20 to 50%,
The liquid temperature is 70 to 110 ° C. At this time, the Si etch rate is 1 to 10 μm / min. Further, the ethylenediamine aqueous solution is, to be exact, a mixed liquid of ethylene, pyrocaracol and water, and its composition is, for example, 10: 1: 1.
It is 0. The liquid temperature is 80 to 150 ° C, and the etch rate is 0.
5 to 5 μm / min can be realized. For more precise control of the etching rate, it is preferable to add 5 to 20% of pyrazine. FIG. 17 shows the etched state. As shown in FIG. 17, the peripheral drive circuit portion is protected by an etching resistant layer and the substrate is removed by etching to leave the substrate of the peripheral drive portion. FIG. 17
1000 is an etching resistant layer, 1001 is a back electrode 1002 is a substrate, 1003 is a silicon oxide layer, 100
4 is an etching stopper, 1005 is a silicon oxide layer,
Reference numeral 1006 is a semiconductor layer for forming a device.

The hollow portion may be left as it is if it has sufficient strength, but may be filled with a light-transmissive filler for reinforcement. As the filler, a Si-based resin which is generally most often used is exemplified.

In the liquid crystal display device of the present invention, by controlling the potential of the substrate of the peripheral drive circuit, the leak current due to the operation of the parasitic MOS transistor is reduced and the channel potential of the semiconductor device used in the drive circuit is stabilized. .. Further, since the active layer is made of a single crystal Si thin film, the semiconductor device can be operated 5 to 100 times faster than when it is made of a polycrystalline TFT. Further, by etching from the back surface, the substrate of the image display unit is removed to make only the image display unit transparent, and the rigidity is maintained by the remaining substrate.

Further, in the present invention, when a low power consumption CMOS inverter is used for the driving circuit and a PMOS transistor having a high withstand voltage without backside leakage is used for the switching element, the liquid crystal display device with reduced power consumption has a PMOS transistor for both. If a transistor is used, an inexpensive liquid crystal display device can be provided, and if an NMOS transistor is used for the drive circuit and a PMOS transistor is used for the switching element, there can be provided an inexpensive liquid crystal display device without backside leakage.

The present invention will be described below with reference to specific examples.

[0154]

【Example】

(Example 1) P-type (100) having a thickness of 300 μm
Anodizing single crystal Si substrate in HF solution,
A porous Si substrate was formed.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 hour: 2.4 (hour) Porous Si thickness: 300 (μm) Porosity: 56 (%) By the low pressure CVD method on the P-type (100) porous Si substrate thus obtained, Si epitaxial layer 1.0 μm
Was grown to a layer thickness of. The deposition conditions are as follows.

Source gas: SiH ₄ carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, a 1000 Å oxide layer is formed on the surface of this epitaxial layer. , The other Si substrate on which a 5000 Å oxide layer and a 1000 Å nitride layer were formed on the oxidized surface was superposed and heated in a nitrogen atmosphere at 800 ° C. for 0.5 hours to thereby form two Si substrates. Bonded firmly.

After that, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was carried out in the 6:50) without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and the single crystal Si is used as an etch stop material.
The porous Si substrate was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is 50 Å or less even after 65 minutes, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more. The etching amount (tens of liters) in the porous layer was practically negligible. At this point, the porous Si substrate having a thickness of 200 μm was removed, and 1.0 μ was formed on the SiO _2.
A single crystal Si layer having a thickness of m could be formed. When SiH ₂ Cl was used as the source gas, it was necessary to raise the growth temperature by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate was maintained.

By forming field effect transistors on the single crystal Si thin film and connecting them to each other, a complementary element,
And an integrated circuit thereof were formed, and a pixel switching element and a driving peripheral circuit necessary for a liquid crystal image display device were formed. A known MOS integrated circuit manufacturing technique was used for the manufacturing method of each transistor.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

Thereafter, the Si substrate side is covered with a hydrofluoric acid resistant rubber except under the liquid crystal pixel portion, and the Si substrate is partially removed up to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Furthermore, a transparent resin was filled in the removed recesses to improve reliability, and a projection type liquid crystal image display device by light transmission was completed.

(Example 2) P having a thickness of 200 μm
A Si epitaxial layer was grown to a thickness of 5 μm on a mold (100) Si substrate by an atmospheric pressure CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl _{2
1000 SCCM H 2 230 l / min} . Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min. The Si substrate thus obtained was subjected to anodization in an HF solution to form a porous layer.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hours) Porous Si thickness: 200 (μm) Porosity: 56 (%) As described above, in this anodization, P-type (100) Si was used.
Only the substrate was made porous and there was no change in the Si epitaxial layer.

Then, 10 is formed on the surface of the epitaxial layer.
Oxidation layer of 00Å is formed, and 50
Another Si substrate on which an oxide layer of 00 Å and a nitride film of 500 Å are formed and an insulating layer is arranged is superposed and heated in a nitrogen atmosphere at 800 ° C. for 0.5 hours to form two Si substrates. Bonded firmly.

After that, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
Selective etching was carried out in 6:50) without stirring. After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is 50 Å or less even after 65 minutes, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, The etching amount (tens of liters) in the non-porous layer was practically negligible. Such places, Si substrate made porous having a thickness of 200μm is removed, on the SiO ₂ 5
A single crystal Si layer having a thickness of μm could be formed. As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that new crystal defects were not introduced into the Si layer and good crystallinity was maintained. Bipolar and field effect transistors are formed in the single crystal Si thin film and connected to each other to form a complementary element and its integrated circuit, and a pixel switching element and a driving peripheral circuit necessary for a liquid crystal image display device are formed. did. As a method of manufacturing each transistor, known MOS and Bi-CMOS integrated circuit manufacturing technology was used.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

After that, the Si substrate side is covered with a hydrofluoric acid resistant rubber except under the liquid crystal pixel portion, and the Si substrate is partially removed up to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Furthermore, to improve reliability, the removed recess was filled with spin-on glass, and a projection type liquid crystal image display device by light transmission was completed.

(Example 3) P having a thickness of 200 μm
Type (100) by ion implantation of protons into the surface of the Si substrate, H ⁺ implantation amount was 1μm formed an N-type Si layer is 5 × 1
It was 0 ¹⁵ (ions / cm ² ). 50% on this board
Anodization was performed in the HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. The entire P-type (100) Si substrate having a thickness of 200 μm was made porous in 24 minutes. In this anodization, P-type (100) S
Only the i substrate was made porous, and there was no change in the N-type Si layer.

Next, 1000 Å is applied to the surface of the N-type Si layer.
Oxide layer is formed, and 5000 Å on the oxidized surface
The other Si substrate having the oxynitride layer formed thereon was superposed and heated in a nitrogen atmosphere at 800 ° C. for 0.5 hours to firmly bond the two Si substrates.

After that, a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide solution (10: 6:
In 50), selective etching was performed without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is 50 Å or less even after 65 minutes, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more. The etching amount (tens of liters) in the porous layer was practically negligible. Then, the porous Si substrate having a thickness of 200 μm was removed, and 1.0 μ was formed on the SiO _2.
A single crystal Si layer having a thickness of m could be formed. As a result of cross-sectional observation with a transmission electron microscope, it was confirmed that new crystal defects were not introduced into the Si layer and good crystallinity was maintained.

Bipolar and field effect transistors are formed in the single crystal Si thin film and connected to each other to form a complementary element and its integrated circuit, and a pixel switching element and a driving periphery necessary for a liquid crystal image display device are formed. Formed a circuit. As a method of manufacturing each transistor, known MOS and Bi-CMOS integrated circuit manufacturing technology was used.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

Thereafter, the back side of the Si substrate was covered with apiezon wax except under the liquid crystal pixel portion, and the Si substrate was partially removed up to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Further, a clear mold was filled in the removed recesses to improve reliability, and a projection type liquid crystal image display device by light transmission was completed.

(Example 4) P having a thickness of 500 μm
A mold (100) single crystal Si substrate was anodized in a 50% HF solution. Current density at this time is 10mA
Was / cm ² . The P-type (100) porous Si having a porous layer having a thickness of 20 μm formed on the surface in 10 minutes
An Si epitaxial layer was grown on the substrate at a low temperature to a thickness of 0.5 μm by the low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂
(0.6 l / min) H ₂ (100 l / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer was thermally oxidized to 50 nm. Another Si substrate having an oxide layer of 0.8 μm on its surface is superposed on the thermal oxide film, and 900 ° C. in a nitrogen atmosphere,
The two substrates were firmly bonded together by heating for 1.5 hours.

After that, the Si substrate was removed from the back surface by grinding to a thickness of 490 μm to expose the porous layer.

Then, a liquid mixture of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5) was applied to the bonded substrates.
The selective etching was carried out in 0) without stirring. 1
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si layer was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and even after 15 minutes, the etching rate was 40%.
It was only about Å, the selectivity to the etching rate of the porous layer reached more than 10 5 and the etching amount (tens of Å) in the non-porous layer was practically negligible. After removing the Si ₃ N ₄ layer, single-crystal Si having a thickness of 0.5 μm is formed on the Si substrate having the insulating layer on the surface.
A layer could be formed.

Further, the same effect can be obtained by coating with apiezon wax or electron wax instead of the Si ₃ N ₄ layer, and only the porous Si layer can be completely removed.

By forming field effect transistors on the single crystal Si thin film and connecting them to each other, complementary elements,
And an integrated circuit thereof were formed, and a pixel switching element and a driving peripheral circuit necessary for a liquid crystal image display device were formed. A known MOS integrated circuit manufacturing technique was used for the manufacturing method of each transistor.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

Thereafter, the back side of the Si substrate was covered with apiezon wax except under the liquid crystal pixel portion, and the Si substrate was partially removed up to the insulating layer using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. Further, a clear mold was filled in the removed recesses to improve reliability, and a projection type liquid crystal image display device by light transmission was completed.

As described in detail above, the liquid crystal image display device of the present invention is excellent in economic efficiency and is uniform and flat over a large area.
Since the Si single crystal substrate with extremely excellent crystallinity is used and the semiconductor active element is formed on the Si single crystal layer with extremely few defects, the stray capacitance of the semiconductor element is reduced and high speed operation is possible. Thus, it is possible to provide a high-performance device in which elements and circuits having an excellent radiation resistance characteristic without a latch-up phenomenon are integrated on the same substrate as a liquid crystal image display pixel.

Further, the liquid crystal image display device according to the present invention is
By selectively removing the porous substrate or porous layer,
High performance is obtained by forming a high quality single crystal layer formed on a non-transparent substrate. Further, by adopting the Si substrate as the amorphous substrate, it can be a starting material having excellent thermal, mechanical, chemical or physical compatibility with the conventional silicon integrated circuit process.

In general, when a light source having a considerably high light intensity is used in a projection type liquid crystal image display device, when a peripheral circuit portion is exposed to light, a photoexcitation current may be induced in the semiconductor layer, which may cause malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Example 5 P having a thickness of 200 μm
A mold (100) single crystal Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hour) Porous Si thickness: 200 (μm) Porosity: 56 (%) MBE (Molecular Beam Epitaxy: Molecular Beam) on the P-type (100) porous Si substrate. Epit
axy) method to form a Si epitaxial layer of 0.5 μm
It was grown at a low temperature. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ^-9 Torr Growth rate: 0.1 nm / sec Next, a 100 nm oxide layer is formed on the surface of this epitaxial layer, and a 500 nm oxide layer is formed on the oxidized surface. The other Si substrate having the oxide layer formed thereon was overlaid and heated in an oxygen atmosphere at 800 ° C. for 0.5 hours, whereby both Si substrates were firmly bonded.

Thereafter, the bonded substrates were mixed with each other by a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide solution (10:
Selective etching at 6:50) without stirring. 6
After 5 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes, 50Å.
The etching rate of the porous layer is less than the above, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (tens of liters) in the non-porous layer is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single crystal Si layer having a thickness of 0.5 μm could be formed on SiO ₂ .

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

After this, the entire substrate is coated with Si ₃ N ₄ ,
Only Si ₃ N ₄ on the back surface of the region to be transparent is etched and removed. This substrate was first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a Si substrate of 10 μm. Then, etching was performed with a solution of hydrofluoric nitric acid (1: 3: 8) for 10 minutes, so that only the opening of Si ₃ N ₄ was etched and SiO ₂ was exposed. After removing Si ₃ N ₄ , an SOI base material having a Si layer in which a part of the base material became transparent and the crystallinity was as excellent as that of a Si wafer could be produced.

Example 6 P having a thickness of 200 μm
A mold (100) single crystal Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%) Si epitaxial layer formed on the P-type (100) porous Si substrate by plasma CVD method. Was grown at a low temperature of 0.5 μm. The deposition conditions are as follows.

Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 2.5 nm / sec Next, a 100 nm oxide layer is formed on the surface of this epitaxial layer, The other Si substrate having a 500 nm oxide layer formed on the oxidized surface was superposed on the oxidized surface and heated in an oxygen atmosphere at 900 ° C. for 0.5 hour to firmly bond the two Si substrates.

After that, the bonded substrates are selectively etched with stirring with a mixed solution (1: 5) of 49% hydrofluoric acid and 30% hydrogen peroxide. After 62 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a material for the stop, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 62 minutes, 50Å.
The etching rate of the porous layer is less than the above, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (tens of liters) in the non-porous layer is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ .

After this, the entire substrate is coated with Si ₃ N ₄ ,
Only Si ₃ N ₄ on the back surface of the region to be transparent is etched and removed. This substrate was first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a Si substrate of 10 μm. Then, etching was performed with a solution of hydrofluoric nitric acid (1: 3: 8) for 10 minutes, so that only the opening of Si ₃ N ₄ was etched and SiO ₂ was exposed. After removing Si ₃ N ₄ , an SOI base material having a Si layer in which a part of the base material became transparent and the crystallinity was as excellent as that of a Si wafer could be prepared.

Example 7 P having a thickness of 200 μm
A mold (100) single crystal Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hours) Porous Si thickness: 200 (μm) Porosity: 56 (%) Si epitaxial on the P-type (100) porous Si substrate by a bias sputtering method. The layer was low temperature grown to 0.5 μm. The deposition conditions are as follows.

RF frequency: 100 MHz High frequency power: 600 W Temperature: 300 ° C. Ar pressure: 8 × 10 ⁻³ Torr Growth time: 60 minutes Target DC bias: −200 V Substrate DC bias: +5 V Next, 100 nm on the surface of this epitaxial layer. On the surface of SiO ₂ (300
nm) / Si ₃ N ₄ (100 nm) is formed on the other Si substrate, and 900 ° C. in a nitrogen atmosphere,
By heating for 0.5 hour, both Si substrates were firmly bonded.

Then, the bonded substrates are selectively etched with a mixed solution of 49% hydrofluoric acid and alcohol (10: 1) without stirring. After 82 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 50Å even after 82 minutes.
The etching rate of the porous layer is less than the above, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (tens of liters) in the non-porous layer is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single crystal Si layer having a thickness of 0.5 μm was formed on SiO ₂ / Si ₃ N ₄ .

After that, the entire substrate is covered with Si ₃ N ₄ as an etching prevention film to form Si on the back surface of the region to be light-transmitting.
Only ₃ N ₄ is removed by etching. The substrate was first etched with a solution of fluorinated nitric acid (84:16) for 19 minutes to obtain 10
The Si substrate is left by μm. Next, hydrofluoric nitric acid (1: 3:
8) When the solution was etched for 10 minutes, only the openings of Si ₃ N ₄ were etched and Si ₃ N ₄ was exposed. Si
After removing ₃ N ₄ , a part of the substrate becomes transparent, and the crystallinity is as excellent as that of a Si wafer.
The base material could be created.

(Embodiment 8) N having a thickness of 200 μm
A mold (100) single crystal Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hours) Porous Si thickness: 200 (μm) Porosity: 56 (%) Si epitaxial growth on the N-type (100) porous Si substrate by liquid phase epitaxy The layers were cold grown at 5 μm. The growth conditions are as follows.

Solvent: Sn Temperature: 900 ° C. Growth atmosphere: H ₂ Growth time: 50 minutes Next, a 100 nm oxide layer is formed on the surface of this epitaxial layer, and a 500 nm oxide layer is formed on the oxidized surface. By stacking the other Si substrate thus prepared and heating it in a nitrogen atmosphere at 1000 ° C. for 0.5 hour,
Both Si substrates were firmly bonded.

After that, the bonded substrates are selectively etched with 49% hydrofluoric acid while stirring. After 78 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si layer remains.
The porous Si substrate was selectively etched and completely removed using as a material for the etch stop.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 50Å even after 78 minutes.
The etching rate of the porous layer is less than the above, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (tens of liters) in the non-porous layer is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single crystal Si layer having a thickness of 5 μm could be formed on SiO ₂ .

After that, the entire substrate is covered with SiO ₂ as an etching prevention film to form SiO ₂ on the back surface of the region to be made transparent.
Only ₂ is etched away. When this substrate was etched with ethylenediamine (17 ml) + water (8 ml) + pyrocatechol (3 g) for 4 hours, only the SiO ₂ openings were etched and the SiO ₂ layer immediately below the Si layer was exposed. After removing the SiO _{2 of the} etching prevention film,
An SOI substrate having a Si layer having a crystallinity in which a part of the substrate is made transparent is as excellent as that of a Si wafer can be prepared.

Example 9 P having a thickness of 200 μm
A mold (100) single crystal Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hour) Thickness of porous Si: 200 (μm) Porosity: 56 (%) Si epitaxial layer formed on the P-type (100) porous Si substrate by a low pressure CVD method. Were grown to 1 μm. The deposition conditions are as follows.

Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, a 100 nm oxide layer is formed on the surface of this epitaxial layer. By superimposing another Si substrate having a 500 nm oxide layer formed on the oxidized surface and heating it at 1000 ° C. for 0.5 hours in a nitrogen atmosphere,
Both Si substrates were firmly bonded.

After that, the bonded substrates were mixed with buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O), alcohol and 30% hydrogen peroxide solution (10: 6:
Selective etching is performed in 50) without stirring. 205
After a minute, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 205 minutes.
It is about 0 Å or less, the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (several tens of Å) in the non-porous layer is a practically negligible reduction in film thickness. That is, a porous S having a thickness of 200 μm
The i substrate was removed, and a single crystal Si layer having a thickness of 1 μm could be formed on SiO ₂ .

When SiH ₂ Cl ₂ was used as the source gas, the growth temperature had to be raised by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate was maintained.

A MOSFET was formed on the single crystal Si layer. Since a known integrated circuit manufacturing technique is used for the method of manufacturing the MOSFET, description thereof will be omitted here.

After that, the entire substrate is covered with SiO ₂ as an etching prevention film to form SiO ₂ on the back surface of the region to be made transparent.
Only ₂ is etched away. This substrate is 6MKO
After etching with H for 200 minutes, only the SiO ₂ opening was etched and the SiO ₂ layer immediately below the Si layer was exposed. After removing the SiO _{2 of the} etching preventive film, an SOI substrate having a Si layer having a crystallinity in which a part of the substrate was made transparent and a crystallinity as excellent as that of a Si wafer could be prepared.

Example 10 A Si epitaxial layer was grown to a thickness of 1 μm on a P-type (100) Si substrate having a thickness of 200 μm by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl _{2
1000 SCCM H 2 230 l / min} . Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min. This substrate was subjected to anodization in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time was 8.4 μm / mi.
n. And a P-type (100) with a thickness of 200 μm
The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, 10 is formed on the surface of this epitaxial layer.
An oxide layer of 0 nm is formed, and 50 nm is formed on the oxidized surface.
The other Si substrate having a 0 nm oxide layer formed thereon was overlaid and heated in a nitrogen atmosphere at 900 ° C. for 0.5 hour, whereby both Si substrates were firmly bonded.

After that, the bonded substrate was mixed with buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O) in 3%.
Selective etching is performed with stirring in a mixed solution (1: 5) with 0% hydrogen peroxide solution. After 191 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 191 minutes.
It is about 0 Å or less, the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (several tens of Å) in the non-porous layer is a practically negligible reduction in film thickness. That is, a porous S having a thickness of 200 μm
The i substrate was removed, and a single crystal Si layer having a thickness of 1.0 μm could be formed on SiO ₂ .

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

After this, the entire substrate is coated with Si ₃ N ₄ ,
Only Si ₃ N ₄ on the back surface of the region to be transparent is etched and removed. This substrate was first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a Si substrate of 10 μm. Then, etching was performed with a solution of hydrofluoric nitric acid (1: 3: 8) for 10 minutes, so that only the opening of Si ₃ N ₄ was etched and SiO ₂ was exposed. After removing Si ₃ N ₄ , an SOI base material having a Si layer in which a part of the base material became transparent and the crystallinity was as excellent as that of a Si wafer could be prepared.

(Example 11) Si was formed on a P-type (100) Si substrate having a thickness of 200 μm by an atmospheric pressure CVD method.
The epitaxial layer was grown to 5 μm. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl _{2
1000 SCCM H 2 230 l / min} . Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min. The Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 1.6 (hours) Porous Si thickness: 200 (μm) Porosity: 56 (%) As described above, in this anodization, P-type (100) Si was used.
Only the substrate was made porous and there was no change in the Si epitaxial layer.

Next, 10 is formed on the surface of this epitaxial layer.
An oxide layer of 0 nm is formed, and 50 nm is formed on the oxidized surface.
The other Si substrate having a 0 nm oxide layer formed thereon was overlaid and heated in an oxygen atmosphere at 900 ° C. for 0.5 hour, whereby both Si substrates were firmly bonded.

After that, the bonded substrates are selectively etched with a mixed solution of 49% hydrofluoric acid and alcohol (10: 1) without stirring. After 275 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is etched.
As a material for the stop, the porous Si substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 275 minutes.
It is about 0 Å or less, the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (several tens of Å) in the non-porous layer is a practically negligible reduction in film thickness. That is, a porous S having a thickness of 200 μm
The i substrate was removed, and a single crystal Si layer having a thickness of 5 μm could be formed on SiO ₂ .

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

After this, the entire substrate is coated with Si ₃ N ₄ ,
Only Si ₃ N ₄ on the back surface of the region to be transparent is etched and removed. This substrate was first etched with a fluorinated nitric acid (84:16) solution for 19 minutes, leaving a Si substrate of 10 μm. Then, etching was performed with a solution of hydrofluoric nitric acid (1: 3: 8) for 10 minutes, so that only the opening of Si ₃ N ₄ was etched and SiO ₂ was exposed. After removing Si ₃ N ₄ , an SOI base material having a Si layer in which a part of the base material became transparent and the crystallinity was as excellent as that of a Si wafer could be prepared.

Example 12 An N-type Si layer of 1 μm was formed on the surface of a P-type (100) Si substrate having a thickness of 200 μm by broton ion implantation. H ⁺ injection amount is 5
It was × 10 ¹⁵ (ions / cm ² ). 5 on this base
Anodization was performed in a 0% HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. And 200μ
The total thickness of the P-type (100) Si substrate having a thickness of m is 24
Porosified in minutes. As described above, in this anodization, only the P-type (100) Si substrate is made porous and the N-type S is formed.
There was no change in the i layer.

Next, 100 nm is formed on the surface of the N-type Si layer.
Forming an oxide layer of SiO _{2 on the} oxidized surface
The other Si substrate on which (200 nm) / Si ₃ N ₄ (100 nm) was formed is overlaid, and the mixture is placed in an oxygen atmosphere at 80
By heating at 0 ° C. for 0.5 hour, both Si substrates were firmly bonded.

After that, the bonded substrates are selectively etched with buffered hydrofluoric acid (36% NH ₄ F + 4.5% HF + H ₂ O) with stirring. After 258 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 258 minutes.
It is about 0 Å or less, the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (several tens of Å) in the non-porous layer is a practically negligible reduction in film thickness. That is, a porous S having a thickness of 200 μm
i substrate was removed and 1.0 μ on SiO ₂ / Si ₃ N ₄
A single crystal Si layer having a thickness of m could be formed.

[0246] As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

After that, the entire substrate is used as an etching prevention film.
Si₃ N_Four Si on the back surface of the area covered with
₃ N_Four Only etch away. First of all,
Etching for 19 minutes with hydrofluoric nitric acid (84:16) solution,
The Si substrate is left by μm. Next, hydrofluoric nitric acid (1: 3:
8) Etching with a solution for 10 minutes results in Si₃ N_Four Opening
Part is etched, Si₃ N_Four Was exposed. Eh
Si of anti-ching film₃ N _Four After removing the
The crystallinity of which the part became transparent was as good as that of a Si wafer.
An SOI substrate having a Si layer could be created.

Example 13 A P-type (100) single crystal Si substrate having a thickness of 500 μm was anodized in a 50% HF solution. Current density at this time is 10m
It was A / cm ² . A porous layer having a thickness of 20 μm was formed on the surface in 10 minutes. A Si epitaxial layer was grown at a low temperature of 0.5 μm on the P-type (100) porous Si substrate by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂
(0.6 l / min) H ₂ (100 l / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer was thermally oxidized to 50 nm. An Si substrate having an oxide layer of 800 nm on the surface is superposed on the thermal oxide film, and the temperature is 900 ° C. in an oxygen atmosphere.
Both substrates were firmly bonded by heating for 5 hours.

After that, 490 μm from the back surface of the Si substrate
It was removed by grinding to expose the porous layer.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

After that, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
Selective etching is performed in 0) without stirring. After 15 minutes, only the single crystal Si layer remains without being etched, and the single crystal Si is used as an etch stop material to form porous Si.
The layer was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and even after 15 minutes, the etching rate was 40%.
It is only about Å, the selectivity to the etching rate of the porous layer reaches more than 10 5 and the etching amount (several Å) in the non-porous layer is a practically negligible reduction in film thickness. Si
After removing the ₃ N ₄ layer, Si having an insulating layer on the surface
A single crystal Si layer having a thickness of 0.5 μm could be formed on the substrate.

The same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si layer can be eliminated.

After that, the entire surface of the substrate is covered with SiO ₂ as an etching preventing film to form SiO ₂ on the back surface of the region to be made transparent.
Only ₂ is etched away. When this substrate was etched with ethylenediamine (17 ml) + water (8 ml) + pyrocatechol (3 g) for 4 hours, only the SiO ₂ openings were etched and the SiO ₂ layer immediately below the Si layer was exposed. After removing the SiO _{2 of the} etching prevention film,
An SOI substrate having a Si layer having a crystallinity in which a part of the substrate is made transparent is as excellent as that of a Si wafer can be prepared.

Example 14 A Si epitaxial layer was grown to a thickness of 1 μm on a P-type (100) Si substrate having a thickness of 200 μm by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl _{2
1000 SCCM H 2 230 l / min} . Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min. This substrate was subjected to anodization in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time was 8.4 μm / mi.
n. And a P-type (100) with a thickness of 200 μm
The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, the surface of this epitaxial layer is covered with 80
Superimposing a Si substrate having a 0 nm oxide layer on the surface,
By heating at 1100 ° C. for 0.5 hour in a nitrogen atmosphere, both Si substrates were firmly bonded.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

After that, the bonded substrates are selectively etched with stirring with a mixed solution of 49% hydrofluoric acid and hydrogen peroxide solution (1: 5). After 62 minutes, only the single crystal Si layer was left unetched, and the porous Si substrate was selectively etched and completely removed using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 50Å even after 62 minutes.
The etching rate of the porous layer is weak, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount (tens of Å) in the non-porous layer is a film thickness reduction that can be practically ignored. That is, the porous Si substrate having a thickness of 200 μm was removed, and after removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1 μm could be formed on the insulating substrate.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

A MOSFET was formed on the single crystal Si layer. Since a known integrated circuit manufacturing technique is used for the method of manufacturing the MOSFET, description thereof will be omitted here.

After that, the entire surface of the substrate is covered with SiO ₂ as an etching preventive film to form SiO ₂ on the back surface of the region to be made transparent.
Only ₂ is etched away. This substrate is 6MKO
After etching with H for 200 minutes, only the SiO ₂ opening was etched and the SiO ₂ layer immediately below the Si layer was exposed. After removing the SiO _{2 of the} etching preventive film, an SOI substrate having a Si layer having a crystallinity in which a part of the substrate was made transparent and a crystallinity as excellent as that of a Si wafer could be prepared.

As described in detail above, according to the present invention, the non-translucent insulator substrate (the insulating layer is formed on the Si substrate by removing the porous Si substrate by a step including at least wet chemical etching). A single crystal semiconductor layer is formed on the surface of the insulating substrate, and a part of the insulator substrate is exposed from the surface (back surface) where the single crystal semiconductor layer is not formed to the insulating layer or the single crystal semiconductor layer near the surface. Until that time, it can be removed by a process including at least wet chemical etching, and a continuous thin layer can be left without a support right underneath, so that the non-translucent substrate can be partially made translucent.

Further, according to the present invention, before changing the light-transmitting property, after forming an electronic device in at least a portion which becomes the light-transmitting property, the light-transmitting property can be changed by the above method.

According to the present invention, after the single crystal Si layer is formed on the non-translucent insulating substrate, the non-translucent substrate portion is removed only in the necessary region, whereby the translucency can be changed. Si layer that can be easily formed without using a light-transmitting substrate represented by glass and is excellent in productivity, uniformity, controllability, and economical efficiency, and has excellent crystallinity as a single crystal wafer. It is possible to make a base material having a light-transmitting SOI structure.

The transparent SOI substrate according to the present invention is
It can be used as a viewfinder, a contact sensor, or a translucent substrate for a liquid crystal display, and can be further applied to an X-ray mask, a pressure sensor, micromechanics, and the like.

(Embodiment 15) FIG. 18 is a schematic process drawing of this embodiment.

P type (100) having a thickness of 300 μm
Anodizing single crystal Si substrate in HF solution,
A porous Si substrate was formed.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) P-type (100) porous Si substrate 101 thus obtained
The Si epitaxial layer 102 is formed on the upper surface by low pressure CVD.
Were grown to a layer thickness of 1.0 μm. The deposition conditions are as follows.

Source gas: SiH ₄ carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, 1000 Å on the surface of this epitaxial layer 102.
An oxide layer 103 is formed on the surface of
The other Si substrate 107 having the 00 Å oxide layer 104 and the 1000 Å nitride layer 105 formed thereon is superposed and heated in a nitrogen atmosphere at 800 ° C. for 0.5 hours to firmly bond the two Si substrates. It was

After that, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was carried out in the 6:50) without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and the single crystal Si is used as an etch stop material.
The porous Si substrate 101 was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is 50 Å or less even after 65 minutes, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or less. The etching amount (tens of liters) in the porous layer 101 was practically negligible. At such a place, the Si substrate 101 made porous having a thickness of 200 μm is removed and S
Single crystal Si with a thickness of 1.0 μm on iO ₂ 103
The layer 102 could be formed. SiH ₂ C as source gas
When 1 is used, it is necessary to increase the growth rate by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate is
Maintained.

A field effect transistor is formed in the single crystal Si thin film 102 and connected to each other to form a complementary element and its integrated circuit, and a pixel switching element and a driving peripheral circuit necessary for a liquid crystal image display device are formed. Formed.
For the manufacturing method of each transistor, known MOS
Integrated circuit manufacturing technology was used.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

After that, the Si substrate 107 under the liquid crystal pixel section
Was removed by the following method.

A 30 wt% KOH aqueous solution was heated to about 110 ° C., and etching was advanced in the (100) direction of Si using SiN as a mask. The etch rate shows anisotropy with respect to the crystal plane and is about 300 μm with respect to the (100) plane.
/ H. The shape after etching is shown in FIG. 19. It can be seen that the angle formed by the slope after etching is 55 °, indicating high anisotropy. Further, when the insulating layer 104 is reached, the etching is substantially finished. That is, the lateral side etch rate is very small. With this method, the Si substrate 107 under the liquid crystal pixel portion can be removed with high accuracy.

Finally, spin-on glass was filled in the recessed portion for improving reliability, and a projection type liquid crystal image display device by light transmission was completed.

(Example 16) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate 107 was removed by the following method.

75 ml of ethylenediamine, 1 catechol
A mixed solution prepared by mixing 2 g, 24 ml of water and 0.45 g of pyrazine was heated to about 115 ° C., and etching was performed using SiN as a mask. This method has a very high selection ratio to SiO ₂ of 1000 or more, and SiO ₂ can be used as a membrane and an etching resistant mask.

(Embodiment 17) The removal of the Si substrate 107 is R
A liquid crystal image display device was completed in the same manner as in Example 15 except that the operation was performed in IE. It was possible to etch almost perpendicularly to the mask pattern.

(Example 18) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate 107 was removed by the following method.

About 100 parts of a 1: 1 aqueous solution of hydrazine and water.
Anisotropic etching was performed by heating to ℃ and using SiO ₂ as a mask. The etching rate is 2 μm / min.

Example 19 An Al substrate having an Al ₂ O ₃ (ruby) film on its surface was used as a substrate impermeable to light in the visible light region, and Al was formed by plasma etching with a Cl-based gas. A liquid crystal image display device was completed in the same manner as in Example 15 except that was removed.

According to the present invention, a substrate having anisotropic etching characteristics can be freely selected. Therefore, by selecting a ruby film or the like as the substrate as in this embodiment, a clean liquid crystal surface can be obtained.

(Example 20) A liquid crystal image display device was completed in the same manner as in Example 15 except that the Si substrate was removed in the form of an apple as shown in FIG.

According to the present invention, since accurate etching is possible, various patterns can be made visible by a backlight as in this embodiment.

As described in detail above, the liquid crystal image display device of the present invention is excellent in economic efficiency and is uniform and flat over a large area.
Since the Si single crystal substrate with extremely excellent crystallinity is used and the semiconductor active element is formed on the Si single crystal layer with extremely few defects, the stray capacitance of the semiconductor element is reduced and high speed operation is possible. Thus, it is possible to provide a high-performance device in which elements and circuits having an excellent radiation resistance characteristic without a latch-up phenomenon are integrated on the same substrate as a liquid crystal image display pixel.

Furthermore, the liquid crystal image display device according to the present invention is
By selectively removing the porous substrate or the porous layer by anisotropic etching, a high-quality single crystal layer formed on the non-transparent substrate can be formed, resulting in high performance. Further, by adopting the Si substrate as the non-transparent electrode, it can be a starting material having excellent thermal, mechanical, chemical or physical compatibility with the conventional silicon integrated circuit process.

In general, when a light source having a considerably high light intensity is used in a projection type liquid crystal image display device, when a peripheral circuit portion is exposed to light, a photoexcitation current may be induced in the semiconductor layer, which may cause malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Further, since the liquid crystal image display device of the present invention uses the substrate having the anisotropic etching property as the non-translucent substrate, the lower part of the liquid crystal pixel portion can be removed with high precision.

(Embodiment 21) FIG. 21 shows an outline of the manufacturing process of this embodiment.

P-type (100) with a thickness of 300 μm
Anodizing single crystal Si substrate in HF solution,
A porous Si substrate was formed.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH
= 1: 1: 1 Time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) P-type (100) porous Si substrate 101 thus obtained
The Si epitaxial layer 102 is formed on the upper surface by low pressure CVD.
Were grown to a layer thickness of 1.0 μm. The deposition conditions are as follows.

Source gas: SiH ₄ carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, 1000 Å on the surface of this epitaxial layer 102.
Oxide layer 103 is formed, and 5000 Å is formed on the oxide film surface.
Oxide layer 104, 1000 Å nitride layer 105, and 2000 Å or more SiH _x insulating layer 106 formed on the other Si substrate 107 as a reinforcing material are stacked and heated in a nitrogen atmosphere at 800 ° C. for 0.5 hours. Thus, the two Si substrates were firmly bonded together.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
The selective etching was carried out in the 6:50) without stirring.
After 65 minutes, only the non-porous Si layer remains without being etched, and the single crystal Si is used as an etch stop material.
The porous Si substrate 101 was selectively etched and completely removed. The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, the etching amount is 50 Å or less even after 65 minutes, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or less. The etching amount (tens of liters) in the porous layer 101 was practically negligible. At such a place, the Si substrate 101 made porous having a thickness of 200 μm is removed and S
Single crystal Si with a thickness of 1.0 μm on iO ₂ 103
The layer 102 could be formed. SiH ₂ C as source gas
When 1 is used, it is necessary to raise the growth temperature by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate is
Maintained.

Field effect transistors are formed in the single crystal Si thin film 102 and connected to each other to form complementary elements and integrated circuits thereof, and pixel switching elements and driving peripheral circuits necessary for a liquid crystal image display device are formed. Formed.
For the manufacturing method of each transistor, known MOS
Integrated circuit manufacturing technology was used.

After forming a black matrix and a color filter on the cover glass, a common electrode was formed and an alignment treatment was performed. After aligning the active matrix substrate and printing a sealant, both were assembled and liquid crystal was injected. A well-known liquid crystal display device manufacturing technique is applied to the various steps relating to the liquid crystal.

Thereafter, the Si substrate 107 side is covered with a hydrofluoric acid resistant rubber except under the liquid crystal pixel portion, and the Si substrate 107 is partially covered up to the insulating layer 104 by using a mixed solution of hydrofluoric acid, acetic acid and nitric acid. After removal, a projection type liquid crystal image display device by light transmission was completed.

As in the present embodiment, a substrate formed by bonding a substrate having an insulating film formed on a Si substrate and a Si substrate made porous, and then epitaxially growing Si on the porous Si is Since there is no restriction on the base insulating film of the crystal film, the thickness can be set to several μm, and a SiN film or the like can be used.

By providing a light-transmitting film for improving the film strength between the non-light-transmitting substrate and the single crystal TFT at the time of manufacturing the SOI substrate, there is no manufacturing constraint in forming the TFT. Therefore, it becomes possible to provide a manufacturing method having a degree of freedom. Furthermore, since the reinforcing layer is formed before removing the non-translucent layer, damage at the time of removing the non-translucent layer can be avoided.

Example 22 A SiN _x insulating layer is formed as shown in FIG.
As described above, the Si layer 110 of 5000 Å is left under the insulating film by selective etching (N / P ⁺ ) of Si, and the Si layer 110 is thermally oxidized at about 800 to 1000 ° C.
After making 10 transparent, a CV is formed on the thermal oxide film 110.
A liquid crystal image display device was produced in the same manner as in Example 21 except that the SiN _x insulating layer 111 was formed by the D method. According to this embodiment, the strength can be improved by the two-layer reinforcing film.

Further, by forming a transparent thin film conductive film such as ITO on the SiN _x insulating layer, the back surface potential can be controlled.

(Embodiment 23) As shown in FIG. 23, SiTFT
As an interlayer insulating film of Lp-SiN15 having high film strength
A liquid crystal image display device was prepared in the same manner as in Example 1 except that 6 was used. Problems when the Lp-SiN film is used as an interlayer insulating film are adhesion to a metal film, H ₂ protection effect, and the like.

Regarding the adhesion to the metal film, the problem can be solved by forming a sandwich structure with a film such as SiO ₂ or BPSG. Regarding the H ₂ protection effect,
Vth (threshold voltage) can be controlled by controlling the impurity concentration of the MOS channel portion in advance.

(Example 24) As shown in FIG. 24, O ⁺ was ion-implanted at about 1 × 10 ¹⁸ cm ^{-2 at} 200 kev, and this was heat-treated at about 1300 ° C.
A SiO ₂ layer 202 is formed in 01.

On the substrate 201 formed as described above, SiO ₂ 204 / SiN was formed by the thermal oxidation method and the LP-CVD method.
two-layered film of _x 205 is formed on the front and back. Then, the back surface is patterned and the window of the panel portion is opened.

Then, Si is etched by KOH or the like. The Lp-SiN film serves as a KOH mask material. S
In the etching of i, all or part of the etching is performed. Then, by thermally oxidizing this, only the back surface of the panel portion is thermally oxidized.

After that, the rear surface side is further reinforced by using the thermal oxidation and the CVD method in the process of peeling the surface SiN film and forming the TFT. In particular, the Lp-SiN film 207 used for the LOCOS oxidation method is a tensile film having an internal stress of about 10 ¹⁰ dyn / cm ² and is optimal as a back surface reinforcing film. 209 is a gate electrode, and 210 is a source and drain of a MOS transistor.

When the non-translucent substrate 201 is etched from the back surface, the film strength of the translucent region is determined only by the insulating film 202 and the Si layer 203 on the upper surface of the non-translucent substrate. The degree of freedom in the film structure is narrow. However, according to this embodiment, the film strength of the back surface can be improved without being restricted by the TFT.

(Example 25) A liquid crystal image display device was prepared in the same manner as in Example 21 except that the SiN _x insulating layer 251 was patterned so as to become smaller from the central portion of the light transmitting region toward the peripheral portion as shown in FIG. Created.

According to this embodiment, it is possible to adjust the strength of the light transmitting area, and it is possible to reinforce the strength of the central portion of the light transmitting area having particularly weak strength.

As described in detail above, the liquid crystal image display device of the present invention has excellent economical efficiency and is uniform and flat over a large area.
Since the Si single crystal substrate with extremely excellent crystallinity is used and the semiconductor active element is formed on the Si single crystal layer with extremely few defects, the stray capacitance of the semiconductor element is reduced and high speed operation is possible. Thus, it is possible to provide a high-performance device in which elements and circuits having an excellent radiation resistance characteristic without a latch-up phenomenon are integrated on the same substrate as a liquid crystal image display pixel.

Furthermore, the liquid crystal image display device according to the present invention is
By selectively removing the porous substrate or porous layer,
High performance is obtained by forming a high quality single crystal layer formed on a non-transparent substrate. In addition, by adopting the Si substrate as the non-transparent substrate, it can be a starting material having excellent thermal, mechanical, chemical or physical compatibility with the conventional silicon integrated circuit process.

In general, when a light source with a considerably high light intensity is used in a projection type liquid crystal image display device, when a peripheral circuit portion is exposed to light, a photoexcitation current may be induced in the semiconductor layer, which may cause malfunction. In the device according to the present invention, since the peripheral circuit portion is shielded from light, such a problem can be avoided.

Further, in the liquid crystal image display device of the present invention, since the SiN _x insulating layer is provided in the light-transmitting region where the non-light-transmitting substrate is removed, the strength of the region is reinforced and the reliability is improved. ..

(Twenty-sixth Embodiment) FIG. 26 shows a C circuit for a peripheral drive circuit.
PM for switching elements of MOS inverters and pixel electrodes
An example of a conventional liquid crystal display device using an OS transistor will be shown. This drawing is a cross-sectional view of only the substrate on which a semiconductor device such as a transistor is incorporated. In the figure, 61 is a support substrate, 62
Is a base insulating layer, 63 is an element isolation oxide film, and 64 is an NMOS
The source region of the transistor, 65 is the drain region of the NMOS transistor, 66 is the drain region of the PMOS transistor, 67 is the source region of the PMOS transistor,
68 is a gate oxide film, 69 is a gate electrode, and 70 is NMO.
A channel region of the S transistor, 71 a channel region of the PMOS transistor, 72 an N-type electric field relaxation region, 73
Is a P-type electric field relaxation region, 74 is an Al (wiring) electrode, 75 is an NMOS transistor, 76 and 77 are PMOS transistors, 78 is a storage capacitor portion, 79 is a CMOS inverter,
Reference numerals 80 and 81 are interlayer insulating films, 82 is a common electrode, and 83 is a pixel electrode. Reference numeral 84 is a back surface filling material, and 85 is a back surface electrode.

The substrate configured as described above and the other substrate provided with the common electrode are arranged so as to face each other with a spacer interposed therebetween, and liquid crystal is sealed to form a panel.

In the liquid crystal display device, it is an essential condition that light can pass through the image display portion in both the reflection type and the transmission type. Therefore, conventionally, a single quartz plate is used. On the other hand, although Si is generally well known as an active layer of a transistor, it is extremely difficult to manufacture single crystal Si most desirable as an active layer, and it has practically been impossible to form it on quartz. Therefore, when forming a transistor in a pixel display part and when integrating with a peripheral drive circuit, polycrystalline Si which can be formed on quartz has been used.

However, there is a limit to the use of polycrystalline Si in order to make the screen more fine and drive at higher speed in response to the demand for higher quality images, and the structure of the liquid crystal display device having the semiconductor device using single crystal Si is limited. Was desired.

Therefore, in this embodiment, a semiconductor or a conductor is used as a substrate, a single crystal Si thin film is formed through an insulating layer, and
Only the image display section is made transparent by removing the substrate, and the substrate of the peripheral drive circuit section is provided with the control means of the back surface potential to control the substrate potential, thereby enhancing the performance of the semiconductor device and realizing high speed. It is a liquid crystal display device.

That is, an active matrix type liquid crystal display device having a semiconductor active element in which an active layer is formed of a single crystal Si thin film formed on a semiconductor or conductor substrate via an insulating layer, wherein the image display section is It has transparency by removing the substrate and removing only the insulating layer or by removing it and then filling it with a transparent filler, and the peripheral drive circuit section is left with the substrate and has a back surface potential control means. It is characterized by.

The single crystal Si thin film according to this example is the same as the conventional S
IMOX (Separation by Implant)
ed Oxygen) method or a method using a porous Si substrate. The polycrystalline Si thin film obtained by the latter manufacturing method has almost no defects and is an ideal semiconductor as an active layer of a transistor.

In this embodiment, a CMOS inverter with low power consumption is used for the peripheral driving circuit, a PMOS transistor having a high withstand voltage without backside leakage for switching pixel electrodes, a P-type Si substrate is used for the substrate, and an aluminum is used for the backside of the substrate. A metal electrode is provided to control the substrate potential. A Si-based resin is used for the translucent filling material 84.

In this example, an 8000Å Si oxide film was used as the underlying insulating layer, and a 30% aqueous solution of KOH was used for etching Si, and an etching rate of 4 μm / min was obtained at 100 ° C. As the etching resistant film at this time, LP-
CVD (Low Pressure Chemical
50 deposited at Vapor Deposition)
A 00Å Si nitride film was used. The thickness of this film is preferably thicker, but if it is 6000 to 8000 Å or more, cracks easily occur in the film, and the etching resistance is deteriorated. Therefore, about 1000 to 6000Å is desirable.

FIG. 27 shows the wiring state of the back electrode. In the figure, 90 is a counter substrate provided with a common electrode, which is arranged so as to face the substrate with an adhesive 91 and holds a liquid crystal 92. Further, 93 is a pad on the drive circuit portion such as a CMOS inverter, and is connected to the package 95 side by a bonding wire 94, while the back surface electrode 85 is fixed to the package 95 via a paste conductive material, and is bonded by a bonding wire 96. It is connected to the package 95 side and the potential is controlled. The thickness of the Si support substrate is 55
It is 0 μm, which is sufficient to maintain the strength of the entire chip.

FIG. 28 shows another form adopted to realize this embodiment. FIG. 28 shows a structure in which a back surface electrode is provided on the upper surface of the device region, 501 is a separation layer for separating the elements, and 502 is a back surface electrode. In this method, after forming the device, the opening 503 penetrating the interlayer insulating film 63 and the base insulating film 62 is provided when processing the contact hole. In order to improve the ohmic property of the contact, boron is ion-implanted at 1 × 10 ¹⁵ cm ⁻² , a low resistance p-type diffusion layer 504 is formed, and then Al is deposited to obtain the structure of FIG.

With this structure, the film thickness (T _BOX ) of the underlying insulating layer was set to 8000Å, V _SS = 0 V, V _DD = 14 V, and the back surface potential was set to 2 to 5 V, and it was possible to drive well. Then, 64 gradations in which the light transmittance of the display unit is 90% or more, 4
Realized a liquid crystal display device with 0,000 pixels.

In the liquid crystal display device of this embodiment, the single crystal Si thin film is used for the active layer of the semiconductor device, so that the semiconductor device used for the entire device is 5 to 10 times larger than the conventional polycrystalline TFT.
It is possible to drive 0 times faster, and by controlling the back surface potential, the leakage current of the parasitic element of the semiconductor device used for the peripheral drive circuit can be sufficiently reduced to improve the circuit performance. The high-definition liquid crystal display device capable of displaying high-quality images with tens of thousands of pixels or more, and by removing only the substrate of the image display unit, the display unit is made transparent even in the circuit using single crystal Si. It is a liquid crystal display device that secures sufficient strength.

(Twenty-Seventh Embodiment) It is conceivable to provide an image display region and peripheral circuits on the same substrate in order to eliminate the need for the above bonding.

FIG. 29 is a schematic sectional view in the case where a liquid crystal pixel portion and a peripheral circuit are provided on the same substrate.

As shown in FIG. 29, the same substrate insulating layer 506
An image display area 507 including a pixel TFT and a pixel electrode
And a peripheral circuit 508 for driving the same, and are connected to each other by a data line and a gate line, and the semiconductor substrate is etched by an etching solution such as KOH to transmit light in the image display region. The device is made transparent, and the peripheral circuit region has device characteristics (for example, MOS
The amount of leak current of (1) is affected by the potential of the back surface of the peripheral circuit. Therefore, the structure can be realized by leaving the semiconductor or conductor substrate 509 on the back surface so that a predetermined potential can be applied.

However, when the transparent substrate region and the conductor substrate region are formed in the same substrate, a region 510 in which the substrate film thickness is changed naturally occurs, and as shown in FIG. 29, part of the peripheral circuit formation region is formed. If the transition region extends to the transition region, the film thickness of the transition region of the conductor substrate is not constant, so the electric field is applied differently, causing variations in device characteristics in the peripheral circuits. If it reaches the area, there is a problem that it has a bad influence such as defective pixels with incomplete transparency.

In this embodiment, there is a portion which is a semiconductor or a conductor substrate with an insulating layer in between and a portion which is composed of an insulating layer only. The image display area is provided only in the layer, and the connection between them is made of the same wiring material as that used in the peripheral circuit and the image display area, and the transition area of the semiconductor or conductor substrate thickness. The image display device is characterized in that the wiring region is wider than that of the image display device.

That is, in this embodiment, since the peripheral circuit and the image display area do not exist on the transition area, the peripheral circuit is not adversely affected.

Here, the fact that the wiring area is wider than the transition area means that the wiring area is preferably set to the transition area +0.3 mm or more. This is a value in consideration of the alignment margin of the position where the transition region is formed, and even if the alignment shift occurs, the transition region does not overlap the regions 507 and 508.

FIG. 30 is a sectional view of the essential parts of the image display device of the present invention, and FIG. 31 is a plan view. The plan view is common to each embodiment described later. 509 is a semiconductor or conductor substrate, 506 is an insulating layer, 508 is a peripheral circuit formation region, 507 is an image display region, and 511 is a separation region for electrically insulating 508 and 507. Reference numeral 510 is a transition region of the substrate film thickness.

Peripheral circuit formation area 508 and image display area 5
07 is formed in the semiconductor region on the insulating layer by a semiconductor device manufacturing process. These are electrically isolated by an element isolation region 511 formed by, for example, a LOCOS process, a trench isolation process, a PN junction isolation process, or the like. The wiring member 512 includes the peripheral circuit formation area 508 and the image display area 5.
07, and the wiring members are made of Al, Ti, T
Metals such as a, Mo, Cu and W, TiSi ₂ , TaSi
_In addition to silicide such as ₂ , WSi ₂ and MoSi ₂ , porous Si and ITO are used after a desired pattern is formed by a photolithography process after depositing a film by a CVD method, a sputtering method, an evaporation method or the like.

These wiring members 512 are usually formed with a film thickness of several thousand Å and a width of about 1 to 100 μm.

The peripheral circuit 508 is formed on the semiconductor or conductor substrate excluding the transition region 510, and the image display region 5 is formed.
07 is formed on the transparent substrate excluding the transition region, both regions are electrically insulated, and desired terminals are connected by the wiring member 512, thereby providing a peripheral circuit with less characteristic variation and an image display with less image defects. The region and the region can be formed on the same substrate, and a high-resolution image display device capable of fine patterning at low cost can be realized.

(Embodiment 28) FIG. 32 is a sectional view showing the principal part of another embodiment of the image display device of the present invention.

The embodiment shown in FIG. 32 has two layers of wiring members (51
3, 514), and the case of the multiple wiring provided in Example 27.
In addition to the effect shown in, there is a strong advantage in disconnection. The transition region of the film thickness resulting from etching generally has a width of several hundred μm. For example, if wiring is formed in a transition region having a width of 500 μm with a pitch of 10 μm, a length of 500 μm and a width of 7 μm
Since the regions 508 and 507 must be connected by a long and narrow wire, disconnection of the wire is a serious problem. If the multi-wiring structure is adopted, the redundancy is increased, and it becomes stronger against disconnection. There are various possible combinations in the case of multiple wiring, for example, 51
3 is Al, 514 is polycrystalline Si, 513 is ITO, 51
4 is Al or the like. It is also possible to provide three or more wiring members.

(Example 29) FIG. 33 shows a case where single crystal Si is used for the wiring member, and FIG. 33 (a) shows single crystal Si5.
16 shows the surface, and FIG. 33 (b) shows the case where the single crystal Si 516 is embedded. The single crystal Si 516 is electrically insulated from the isolation region 511.

By using a single crystal wiring, a wiring having a low resistance of several tens Ω / □ can be formed without impairing the flatness of the substrate surface. Therefore, for example, when the present invention is applied to a liquid crystal display device, it is caused by a step. The alignment disorder of the liquid crystal can be reduced.

(Embodiment 30) FIG. 34 shows a peripheral circuit 508.
The image display unit 507 and the image display unit 507 have a completely separated structure.

In the present embodiment, the peripheral circuit 508 and the image display unit 507 are completely separated from each other so that they are insulated, and the capacitive coupling between them is also small, so that the cross in the image display unit 507 is reduced. Problems such as talk and malfunction of the peripheral circuit 508 are reduced.

(Embodiment 31) This embodiment shown in FIG. 35 is an example of a liquid crystal display device produced by a general semiconductor manufacturing process. Peripheral circuit 508 and image display area 507
Are formed in the semiconductor layer on the insulating layer, and both are LOC
It is insulated by the OS insulating film 517. The wiring member 512 is formed on the LOCOS 517, and the peripheral circuit 508 and the image display area 50 are formed through the contact holes.
7 and 7 are connected to each other. A semiconductor substrate 509 is provided under the peripheral circuit with a region where the LOCOS 517 is provided as a boundary, and the potential of the semiconductor substrate 509 is set to a desired value V _Ref to suppress variations in device characteristics. Reference numeral 515 denotes the wiring 512 and the area 5
08 and 507 are insulating films for preventing a short circuit at an unnecessary place.

The above description has been made by taking the display device using the TFT as an example, but the present invention is not limited to the TFT, and an active matrix liquid crystal display device using a diode or an MIM element and a driving circuit are built-in. It goes without saying that similar effects can be obtained in the simple matrix type liquid crystal display device.

The image display portion and the peripheral circuits can be connected at low cost by fine patterning. Further, since the peripheral circuit is surely formed on the semiconductor or the conductor substrate, variations in device characteristics of the peripheral circuit are reduced. It is possible to reduce the area of the image defect in which the transparency is incomplete.

(Embodiment 32) Next, an active matrix type liquid crystal display device which utilizes the characteristics of a CMOS inverter, is used in a peripheral drive circuit, and uses a PMOS transistor as a switching element will be described.

FIG. 36A shows an equivalent circuit of each pixel of the liquid crystal display device. 520 is a gate electrode, 521 is a storage capacitor, and 522 is a liquid crystal capacitor. In the conventional liquid crystal display device, the active layer of the transistor is a polycrystalline Si thin film.

At present, as described above, it is general to form a circuit by combining a plurality of types of semiconductor devices even in one display device, for example. However, the characteristics of semiconductor devices are different, and by forming a plurality of types of semiconductor devices on the same substrate, it is not possible to set the optimum conditions for each device, leaving the problems of each device unsolvable. It will also be used.

FIG. 36 (b) shows the SIMOX (Separa)
(ion by Implanted Oxigen)
NMOS transistors 523 and P formed using the substrate
An equivalent circuit of a CMOS inverter having a MOS transistor 524 is shown. On the substrate side of the CMOS inverter,
A parasitic MOS transistor having a support substrate as a gate electrode and an insulating layer between the support substrate and an active layer as a gate insulating layer is generated. In the case of a conventional CMOS inverter, this parasitic MOS
It is difficult to increase the absolute value of the threshold voltage of the transistor, and even if V _back is set to any value, the parasitic N
The MOS or PMOS transistor operates and leak current flows. FIG. 36C shows the input / output characteristics of this CMOS transistor. As shown in this figure, V _back
= In the vicinity of 0V, due to the leakage current of the PMOS transistor even if V _in is close to the V _DD in order to parasitic PMOS transistor is in operation, the output is not completely drop to V _SS. On the other hand V _back = in the vicinity of 3V, V _in order to parasitic NMOS transistor is operating even if close to the V _SS NM
The output is completely V due to the leakage current of the OS transistor.
_It doesn't reach _DD .

Although the CMOS inverter has the above-mentioned problems, an NMOS transistor formed on a thin film single crystal alone has, for example, a "kink" which causes a step difference in static characteristics.
A phenomenon is seen, and in order to alleviate it, it is necessary to provide a passage for the generated holes to escape.

In the PMOS transistor, the driving speed is limited by the parasitic capacitance between the source / drain and the channel region.

As described above, the characteristics of the semiconductor active elements are different from each other, and the characteristics and conditions to be obtained are different depending on the purpose of incorporating the semiconductor active elements, and when a plurality of semiconductor active elements are formed on the same substrate, those characteristics are required. In some cases, the above conditions may contradict each other, and a method for obtaining more desired properties has been desired.

As a result of earnest studies to solve the above problems, the present inventors have noticed that the characteristics of each semiconductor active element can be controlled to some extent by the film thickness of its active layer, and have achieved this embodiment. I arrived. For example, in order to improve the input / output characteristics of the above-mentioned CMOS inverter, the active layer is thicker than the conventional one, the active layer is thin in order to design a fully depleted type by giving priority to high-speed driving, and the “kink” of the NMOS transistor. To prevent this, it is effective to design a thick active layer, and to impart a withstand voltage, thicker active layers of the NMOS and PMOS transistors.

In view of the above point of view, in the present embodiment, in order to bring out more excellent characteristics in a semiconductor device using a plurality of semiconductor active elements, means for controlling the film thickness of the active layer according to the desired characteristics. Was taken.

That is, in this embodiment, in a semiconductor device having a plurality of semiconductor active elements having an active layer formed of a single crystal semiconductor thin film formed on an insulating layer, the thickness of the active layer of the semiconductor active element is at least 2. The present invention provides a semiconductor device characterized by the existence of various types. In the present invention, the plurality of semiconductor active devices include not only the use of a plurality of types of devices but also the use of a plurality of the same devices.

Further, the present embodiment is an active matrix type liquid crystal display device using the above-mentioned means and using a CMOS inverter in the peripheral driving circuit and a PMOS or NMOS transistor in the switching element of the pixel. The present invention provides a liquid crystal display device characterized in that the film thickness of the active layer is thicker than the film thickness of the active layer of the switching element.

A method of forming different active layers according to this embodiment will be described.

The active layer is made of a single crystal semiconductor thin film,
For convenience of description, Si which is usually most often used will be described. The method for forming the single crystal Si thin film includes epitaxially growing the single crystal Si thin film on the porous Si base, and then bonding the substrates to remove the porous Si base by etching, or the porous Si base before the bonding. It is preferable to remove it by etching and then bond it to the substrate. The single crystal Si thin film thus obtained has almost no defects and can be driven at high speed. However, although not particularly limited to this in the present invention, for example, a single crystal Si thin film obtained by SIMOX has many impurities and is not suitable for use.

The single crystal Si layer according to this example is a porous Si obtained by making a single crystal Si substrate porous as in the above-described examples.
It is formed using a substrate.

Next, a method of changing the thickness of the active layer will be described.

Two methods are shown in FIG. First, a support substrate 525 having a single crystal Si layer 527 on a base insulating layer 526 is prepared, and the surface is thermally oxidized by 100 to 500 Å to form a pad SiO ₂ layer 528. After depositing a SiN layer 529 of 1000 to 3000 Å by LP-CVD, patterning is performed to obtain FIG. 37 (a). Next, using chlorine-based gas, the portion of the single crystal Si from which the SiO ₂ layer 528 and the SiN layer 529 have been removed is etched from the surface. For example, when the original thickness of the Si layer 527 is set to 10000Å, 2000 to 6000Å is etched. As a result, FIG. 37 (b) is obtained. After this, the SiO ₂ layer 528, Si
When the N layer 529 is sequentially removed, a thick single crystal Si layer A and a thin single crystal Si layer B are obtained. Further, after preparing (a), heat treatment is performed in an atmosphere of oxygen or water vapor at 900 to 1200 ° C., whereby only the portion not covered with the SiN layer 529 can be oxidized (c). Original Si
When the thickness of the layer 527 is 10,000 Å, select SiO ₂
Oxidize until the layer is 6000-15000Å. After that, unnecessary portions including this selective SiO ₂ layer are etched to obtain single crystal Si layers having different thicknesses (b).

Thus, the semiconductor active element is formed by changing the film thickness of the single crystal Si according to the design conditions.

In the present embodiment, in the case of a semiconductor device having a plurality of semiconductor active elements, each active layer is changed to a desired state, and as a result, active layers having different film thicknesses are present in the same device. The characteristics of each element are improved and the performance of the entire device is improved.

More specifically, the film thickness is set according to the purpose of the device. For example, when high breakdown voltage and high voltage are required, it is effective to set the film thickness thick. This is effective not only for improving the performance of each transistor, but also for suppressing the operation of a parasitic element (for example, a parasitic PMOS transistor) by increasing the film thickness. A thin film is desirable when high speed is required at a relatively low voltage.
The thin film is effective not only for improving the performance of each transistor, but also for improving the characteristics of the entire circuit mainly due to the effect of reducing the parasitic capacitance.

The optimum value of the film thickness of the active layer according to the present embodiment varies depending on the target device. For example, in the case of an NMOS transistor, the generation of hot carriers is more prominent than that of a PMOS transistor, and thus the breakdown voltage is likely to decrease. Therefore, in a circuit that requires high breakdown voltage and high voltage, the NMOS
The optimum value of the active layer of the transistor is thicker than that of the PMOS transistor.

FIG. 38 shows a sectional view of an embodiment of the liquid crystal display device of the present invention. The basic configuration is the same as that of the liquid crystal display device shown in FIG. 26 described above, and duplicate description will be omitted. In this embodiment, the active layer of the CMOS inverter 59 used in the peripheral drive circuit has a large thickness, and the thickness is 8000 to 100.
00Å, while PMO used for switching pixel electrodes
The active layer of the S transistor 57 is 2000 to 6000 Å. In addition, P in the CMOS inverter of the drive circuit
Junction separation is performed between the active layers of the MOS transistor and the NMOS transistor. In this embodiment, since the active layer is formed by the above-described method for manufacturing the single crystal Si thin film, the Si substrate is used as the supporting substrate 61,
Although the display portion requiring transparency is formed as a hollow portion 84 by etching, the single crystal Si thin film can be formed on a transparent substrate such as glass, so that it can be a whole glass substrate.

FIG. 39 (a) shows an equivalent circuit diagram of this embodiment. Reference numeral 300 is a horizontal shift register for driving the signal line 310, 301 to 303 are red (R), green (G), and blue (B) video signal lines, respectively, and 304 is a MOS transfer signal to a buffer capacitor. Transistor, 30
5 is a buffer capacity for temporarily storing the signal of each signal line,
Reference numeral 306 is a MOS transistor switch for transferring the signal stored in the buffer capacitance to the pixel portion, 307 is a liquid crystal capacitance, 308 is a vertical shift register for driving the gate line 69, 309 is a display portion, and FIG. As shown in b), the display portion 309 is a hollow portion 84 in which the supporting substrate is removed, and the peripheral portion where the drive circuit is formed is S.
The remaining opaque portion 312 of the i substrate.

PM used in the drive circuit in this embodiment
Since the OS and the sources and drains 64 to 67 of the NMOS transistors 55 and 56 are separated from the underlying oxide film 12 by several thousand Å or more, even if the inversion layer due to the supporting substrate potential is formed on the upper surface of the underlying oxide film 12, the source No current flows between the drain and the drain. Therefore, the operation of the parasitic MOS transistor does not need to be a problem, and its input / output characteristics are V _DD
= 8V, V _SS = -6V, and underlying insulating film thickness = 5000Å, the ideal curve shown in FIG. 36 (c) is shown.

As described above, the distance from the bottom surface of the source / drain to the top surface of the base oxide film due to the inoperability of the MOS transistor having the base oxide film as the gate oxide film varies mainly depending on the impurity concentration of the channel region. , 2000
It is preferable to set it to about 10000Å. Even if this distance is not provided, the operation can be controlled by increasing the absolute value of the threshold value of the parasitic MOS transistor.

In this embodiment, the parasitic transistor can be sufficiently turned off even with a relatively thin base insulating film of 5000 Å, so that high voltage driving can be easily performed.
In this embodiment, V _DD −V _SS = 14V is possible, so
It has become possible to apply a voltage of ± 5 V or more to the liquid crystal used for liquid crystal display. As a result, a liquid crystal panel with 100,000 pixels or more could be realized with high gradation of 64 gradations or more.

In this embodiment, the PMOS transistor is used as the switching element in the pixel portion, but the same structure can be obtained by using the NMOS transistor.

(Embodiment 33) Next, as another embodiment, S
FIG. 40 shows an LSI realized by a CMOS circuit formed on an OI (Silicon on Insulator).
It shows in (a). In the figure, 411 is a support substrate, 412 is a base insulating layer, 413 is an element isolation oxide film, 414 is an NMOS source region, 415 is an NMOS drain region, 416 is PM.
OS drain region, 417 is PMOS source region, 41
8 is a gate oxide film, 419 is a gate electrode, and 420 is NM
OS channel region, 421 is PMOS channel region, 4
24 to 427 are electrodes, and 440 is an interlayer insulating film. In this embodiment, the active layer thickness of the NMOS transistor is 40.
00 to 10000Å, the active layer thickness of the PMOS transistor is 500 to 3000Å.

As shown in the figure, the source 414 and the drain 415 of the NMOS transistor do not reach the base insulating layer. The static characteristics of the NMOS and PMOS transistors are shown in FIGS. 40 (b) and 40 (c). In this way, normal NMOS
You can't see the "kink" seen in transistors,
Since the leak current on the back surface is not flowing, the support substrate 411
The Si potential of can be freely set in the range of 0 to + 7V.

When a CMOS ring oscillator and a shift register were constructed using the NMOS and PMOS transistors of this example, the operation of the ring oscillator and the shift register was confirmed in the gate length range of 0.2 to 3.0 μm. Since the withstand voltage of the NMOS transistor was improved, it was possible to drive 7 V even with a gate length of 0.5 μm.

When this embodiment is applied, for example, a normal CM
In the OS inverter, PMOS transistor and NMOS
In order to make the current driving capability of the transistors uniform and to make the on / off characteristics equal, and to improve the degree of freedom in circuit design,
Although the areas of the transistor and the NMOS transistor are changed, the area of the NMOS transistor can be reduced by changing the film thickness of the active layer to improve the integration degree of the entire device.

(Embodiment 34) FIG. 41 shows still another embodiment. This embodiment is a high withstand voltage MOS FET of 10 V or more.
And a fully-depleted high-speed CMOS logic integrated semiconductor device. In the figure, 611 is a support substrate, 612 is a base insulating layer, 613 is an element isolation oxide film, 614 is an NMOS source region, 615 is an NMOS drain region, and 616 is PM.
OS drain region, 617 is PMOS source region, 61
8 is a gate oxide film, 619 is a gate electrode, and 620 is NM
OS channel region, 621 is PMOS channel region, 6
24 is a high voltage NMOS source and drain electrode, and 62
Reference numeral 5 is an electrode of the PMOS and NMOS transistors on the CMOS logic side, 640 is an interlayer insulating film, 643 is a high breakdown voltage NM.
An OS drain electric field relaxation region, 644 is a high breakdown voltage NMOS source region, and 645 is an NMOS drain region.

The high breakdown voltage NMOS FET of this example showed a breakdown voltage of 15 V or higher, as shown in FIG. 42, without the holes generated near the drain degrading the breakdown voltage.
This is because the thickness of the active layer was increased to secure an escape route for the holes. On the other hand, the NMOS transistor in the logic portion has a thin active layer and a breakdown voltage of 8V, but has a small drain and source capacitance, and the channel portion is completely depleted, so that the same circuit formed on the bulk is formed. It was found that the operation speed was improved about twice as much as the above.

(Embodiment 35) FIG. 43 shows a cross section of the main part of a high-speed Bi-CMOS SRAM (static random access memory using a bipolar transistor CMOS inverter) of still another embodiment.

First, the SRAM will be briefly described. FIG. 44 shows an overall configuration diagram of a static RAM equipped with a logic circuit in this embodiment. Clock shaping circuit 7 described later
The clock input from 05 is divided into six by the first-stage clock driver A701, and drives the next-stage clock driver B703. The first-stage clock driver A 701 is formed on a gate array 704 having 1000 gates together with a part of the clock driver B 703, a logic circuit (for example, a flip-flop 702) and the like. The SRA surrounds the gate array 704.
The M macro cells are arranged in a 512 word × 18 bit configuration, and the input / output circuit 706 surrounds the periphery of the M macro cells.

Next, details of the SRAM macro cell are shown in FIG.
5 shows. One macro cell has 64 word lines (horizontal lines) and 9-bit data lines (2 per cell).
Memole cells 811 arranged in an array on the existing vertical line), 64 word line drivers 1 to 64: 809, 810 for driving the word lines, a decoder 802 for selecting a word line, and a word line. An address latch 801 for temporarily storing a code to be selected, a current switch 803 for writing data in the selected memory cell 811, a sense amplifier 808 for reading the data written in each memory cell 811, A large number of portions surrounded by broken lines are repeated on the chip as an array 1 of 804 including an output buffer 807 for amplifying data and a discharge circuit 806 for erasing memory cell data. However, it is shown in the figure that the word line driver is common between the arrays.

Details of the clock shaping circuit in FIG. 44 are shown in FIG.
6 shows. The clock shaping circuit is a circuit for eliminating delays in rising and falling of the input signals P1 and N1 and obtaining a pulse signal closer to an ideal form as outputs P0 and N0, and a buffer 902 that differentially amplifies the input signals. , A shaping circuit 903 configured by differential amplification, and a delay circuit 901. V _CC indicates a high voltage side power source and V _EE indicates a low voltage side power source.

In this embodiment, the word driver, the current switch, the discharge circuit and the pulse shaping circuit are composed of bipolar transistors, and the other circuit parts are composed of CMOS inverters.

Next, the CMOS inverter and bipolar transistor shown in FIG. 43 will be described. In FIG. 43, 711 is a supporting substrate, 712 is a base insulating layer, 713 is an element isolation oxide film, 714 is an NMOS source region, and 715 is N.
MOS drain region, 716 is PMOS drain region,
717 is a PMOS source region, 718 is a gate oxide film,
719 is a gate electrode, 720 is an NMOS channel region,
721 is a PMOS channel region, 724 is an NMOS source electrode, 725 is an NMOS drain electrode, and 726 is PM.
OS drain electrode, 727 is PMOS source electrode, 73
0 is an NPN bipolar transistor, 731 is an NMOS
Transistor, 732 is PMOS transistor, 740
Is a collector buried layer, 741 is a collector extraction layer, 742
Is an intrinsic collector region, 743 is a p-type base region, 744
Is an n ⁺ type emitter region, 745 is an emitter region, 746
Is a collector region, 747 is a base region, 748 is an emitter electrode, and 750 is an interlayer insulating film.

In this embodiment, the thickness of the active layer is set to 1.0 μm in order to make the collector buried layer resistance sufficiently low.
The MOS transistor side is a full depletion type in order to reduce the junction capacitance, and the active layer thickness is 500 to 3000 Å.

In this embodiment, the collector substrate capacitance is almost 0.
It was set to fF. Further, by using the SOI MOS, the power consumption was able to be suppressed to 1/10 although the speed was deteriorated by about 10% as compared with the logic having the bipolar structure.

As specifically mentioned in the present embodiment, the semiconductor active element has different characteristics and conditions required depending on its application, and in order to satisfy different requirements on the same substrate, the semiconductor active layer is required. The constitution of the present invention is a very simple and effective means by which the required characteristics can be sufficiently obtained by changing the film thickness of. According to the present invention, a semiconductor device having higher performance than the conventional one can be obtained without increasing the cost.

[0393]

As described above, according to the present invention, an excellent driving element which solves the conventional problems can be obtained, and an excellent liquid crystal image display device having high image quality can be provided.

[Brief description of drawings]

FIG. 1 is a schematic view of a conventional active matrix type liquid crystal display device.

FIG. 2 is a schematic diagram for explaining a manufacturing process of a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining a manufacturing process of a liquid crystal display device according to another embodiment of the present invention.

FIG. 4 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 5 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 6 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 7 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 8 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 9 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 10 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 11 is a graph showing etching characteristics of porous silicon and non-porous silicon.

FIG. 12 is a schematic view for explaining the manufacturing process of the semiconductor optical member according to the embodiment of the present invention.

FIG. 13 is a schematic diagram for explaining a manufacturing process of a semiconductor optical member according to another embodiment of the present invention.

FIG. 14 is a schematic diagram for explaining a manufacturing process of a semiconductor optical member according to another embodiment of the present invention.

FIG. 15 is a schematic diagram for explaining a manufacturing process of a semiconductor optical member according to another embodiment of the present invention.

FIG. 16 is a schematic diagram showing the relationship between the thickness of a base insulating layer and the operating voltage of CMOS.

FIG. 17 is a schematic diagram for explaining a method for manufacturing a semiconductor substrate portion of a liquid crystal display device of the present invention.

FIG. 18 is a schematic diagram for explaining a manufacturing process of a semiconductor substrate for a liquid crystal display device according to an embodiment of the present invention.

FIG. 19 is a schematic view for explaining a state of a semiconductor substrate of a liquid crystal display device according to an embodiment of the present invention, which is located below a liquid crystal pixel portion.

FIG. 20 is a schematic view for explaining a state of a semiconductor substrate of a liquid crystal display device according to an embodiment of the present invention, which is located below a liquid crystal pixel portion.

FIG. 21 is a schematic diagram for explaining a manufacturing process for a semiconductor substrate for a liquid crystal display device according to a twenty-first embodiment of the present invention.

FIG. 22 is a schematic cross-sectional view showing a semiconductor substrate for a liquid crystal display device according to Example 22 of the present invention.

FIG. 23 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Example 23 of the present invention.

FIG. 24 is a schematic diagram for explaining a manufacturing process for a liquid crystal display device according to a twenty-fourth embodiment of the present invention.

FIG. 25 is a schematic bottom view showing a part of a liquid crystal display device according to Example 25 of the present invention.

FIG. 26 is a schematic sectional view showing a liquid crystal display device according to Example 26 of the present invention.

FIG. 27 is a schematic cross-sectional view showing the structure of the back electrode of the liquid crystal display device according to the embodiment of the present invention.

FIG. 28 is a schematic cross-sectional view showing the structure of a back electrode of a liquid crystal display device according to another embodiment of the present invention.

FIG. 29 is a schematic view for explaining a part of the liquid crystal display device according to the embodiment of the present invention.

FIG. 30 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Embodiment 27 of the present invention.

FIG. 31 is a schematic plan view of a liquid crystal display device according to an embodiment of the present invention.

FIG. 32 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Example 28 of the present invention.

FIG. 33 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Embodiment 29 of the present invention.

FIG. 34 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Example 30 of the present invention.

FIG. 35 is a schematic cross-sectional view showing a part of a liquid crystal display device according to Example 31 of the present invention.

FIG. 36 is a schematic diagram for explaining the operation of the MOS transistor.

FIG. 37 is a schematic diagram for explaining a method for forming a semiconductor layer according to an embodiment of the present invention.

FIG. 38 is a schematic cross-sectional view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 39 is a schematic diagram for explaining a circuit configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 40 is a schematic diagram for explaining a CMOS transistor used in the present invention.

FIG. 41 is a schematic cross-sectional view of a CMOS circuit according to Example 34 of the present invention.

FIG. 42 is a graph showing characteristics of a MOS transistor used in the present invention.

FIG. 43 is a schematic cross-sectional view of the SRAM according to the embodiment 35 of the present invention.

FIG. 44 is a schematic diagram for explaining the structure of the circuit block of the SRAM according to the thirty-fifth embodiment of the present invention.

45 is a circuit configuration diagram of the SRAM shown in FIG. 44.

FIG. 46 is a circuit configuration diagram of a clock shaping circuit used in the present invention.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical indication location H01L 27/12 A 29/784 (31) Priority claim number Japanese Patent Application No. 4-40490 (32) Priority date 4 (1992) January 31 (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-40448 (32) Priority Day 4 (1992) January 31 (33) Priority Claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-40453 (32) Priority date Hei 4 (1992) January 31 (33) Priority claiming country Japan (JP) (31) Priority claim Number Japanese Patent Application No. 4-40449 (32) Priority Date 4 (1992) January 31 (33) Country of priority claim Japan (JP) (72) Inventor Junichi Hoshi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Akira Ishizaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Innovator Tetsunobu Mitsuchi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Co., Ltd. (72) Inventor Shigetoshi Sugawa 3 Shimomaruko, Ota-ku, Tokyo No. 30-2 Canon Inc. (72) Inventor Shunsuke Inoue 3-30-2 Shimomaruko, Ota-ku, Tokyo No. 30 Canon Inc. (72) Toru Koizumi 3-30-2 Shimomaruko, Ota-ku, Tokyo No. Canon Inc. (72) Inventor Takanori Watanabe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Mamoru Miyawaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (37)

[Claims] 1. A liquid crystal image display device formed on a substrate that is opaque to light in the visible light region, wherein a portion of the substrate below the liquid crystal pixel portion is removed, and the liquid crystal pixel portion is removed. A liquid crystal image display device characterized by allowing light to pass through. 2. The liquid crystal image display device according to claim 1, wherein a single crystal semiconductor layer in which an active region of a semiconductor element is formed is provided on the non-translucent substrate. 3. The single crystal semiconductor layer and the substrate are made of Si.
3. The liquid crystal image display device according to claim 2, comprising: 4. A silicon nitride film is provided on the lower surface of the liquid crystal pixel portion.
4. The liquid crystal image display device according to any one of 3 above. 5. The lower surface of the liquid crystal pixel portion is formed of a layer made of silicon oxide, and a silicon nitride film is provided on the surface. The liquid crystal image display device according to item 1. 6. The liquid crystal image display device according to claim 1, wherein a transparent member is provided on a surface below the liquid crystal pixel portion. 7. The liquid crystal image display device according to claim 2, wherein the substrate is provided with potential setting means for setting a potential of the single crystal semiconductor layer. 8. The liquid crystal pixel section side of the substrate includes a layer thickness change area in which the substrate layer thickness is changed, and the liquid crystal pixel section and a peripheral circuit are provided on the layer thickness change area. A wiring for connecting the two is provided.
4. The liquid crystal image display device according to any one of 3 to 3. 9. A method of manufacturing a liquid crystal image display device, comprising: a substrate; and a liquid crystal pixel portion formed on the substrate, wherein a portion of the substrate below the liquid crystal pixel portion is translucent. After forming the liquid crystal pixel portion on the translucent insulating layer formed on the light-transmissive substrate, a part of the substrate below the liquid crystal pixel portion is removed by etching to form the liquid crystal pixel portion. A method of manufacturing a liquid crystal image display device, characterized in that light can enter. 10. The manufacturing method according to claim 9, wherein the liquid crystal pixel portion is formed after forming a semiconductor element on the translucent insulating layer. 11. The method according to claim 10, wherein the semiconductor element is formed after transferring a semiconductor layer formed on another substrate onto the substrate. 12. The manufacturing method according to claim 10, wherein the semiconductor element has an active layer made of Si. 13. The manufacturing method according to claim 9, wherein the etching is wet etching. 14. The manufacturing method according to claim 14, wherein the etching is dry etching. 15. The manufacturing method according to claim 9, wherein the etching is anisotropic etching. 16. A step of bonding a surface side of a single crystal semiconductor layer formed on a porous first substrate to an insulating surface side of a non-translucent second substrate, and the first step. A step of removing the substrate by a process including wet etching; and a part of the second substrate is removed to form a region where light enters from the second substrate side in the single crystal semiconductor layer. And a method for manufacturing a semiconductor optical member having a light-transmitting portion and a non-light-transmitting portion. 17. The manufacturing method according to claim 16, wherein the first base, the single crystal semiconductor layer, and the second base are each made of Si. 18. The method according to claim 16, wherein a part of the second substrate is removed after forming a semiconductor element using the single crystal semiconductor layer. 19. The manufacturing method according to claim 16, wherein the semiconductor optical member is a liquid crystal image display device. 20. The manufacturing method according to claim 16, wherein the second base includes a non-translucent substrate and a translucent insulating layer. 21. A liquid crystal image display device comprising at least two semiconductor elements each having an active layer made of a single crystal semiconductor on a substrate having an insulating surface, wherein each of the plurality of semiconductor elements has an active layer having a different layer thickness. A liquid crystal image display device comprising: 22. A semiconductor element having an active layer having a first layer thickness is used as a switching element for pixel selection,
22. The liquid crystal image display device according to claim 21, wherein the peripheral circuit is composed of another semiconductor element having an active layer having a layer thickness larger than the first layer thickness. 23. The liquid crystal image display device according to claim 22, wherein the peripheral circuit further includes a semiconductor element having active layers having different layer thicknesses. 24. The liquid crystal image display device according to claim 22, wherein the switching element is a MOS transistor, and the peripheral circuit includes a CMOS inverter. 25. A surface of an insulating layer formed on the surface of a non-porous single crystal layer on a porous first Si substrate or an insulating layer surface formed on the non-porous single crystal layer, Si
A step of adhering to the substrate, a step of removing the porous first Si substrate by a process including at least wet chemical etching to form a single crystal semiconductor layer on the adhered insulating layer, and the single crystal A step of forming an electronic device in a semiconductor layer, and a part of the second Si substrate or an insulating layer bonded to the second Si substrate, including at least a portion immediately below a region in which the electronic device is formed Is partially removed by a process including at least wet chemical etching until the insulating surface of the insulating layer or the single crystal surface of the single crystal semiconductor layer exposed from the surface side where the single crystal semiconductor layer is not formed is exposed. A method of manufacturing a semiconductor optical member, comprising: 26. The method of manufacturing a semiconductor optical member according to claim 25, wherein the first Si substrate is made porous by anodization. 27. The method for manufacturing a semiconductor optical member according to claim 26, wherein the anodization is performed in a solution containing HF. 28. A Si single crystal layer in which an active region of a Si semiconductor active element is formed, and a liquid crystal layer are provided on the surface of a Si substrate whose surface is formed of a translucent insulating layer, and the liquid crystal layer. The lower Si substrate is removed by anisotropic etching from the opposite side of the liquid crystal layer until the transparent insulating layer is reached, and visible light can be transmitted through the liquid crystal layer. apparatus. 29. A Si single crystal layer having an active region of a Si semiconductor active element and a liquid crystal layer are provided on the surface of a Si substrate having a surface formed of a translucent insulating layer. The lower Si substrate is a liquid crystal image display device in which visible light can be transmitted to the liquid crystal layer by being removed from a side opposite to the liquid crystal layer until reaching the transparent insulating layer.
The single crystal layer is formed on the porous Si semiconductor and then the S
A liquid crystal image display device, which is obtained by laminating the surface of the Si substrate on an i single crystal layer and then removing the porous semiconductor layer by anisotropic etching. 30. The liquid crystal image display device according to claim 28, wherein the etching is chemical etching. 31. The liquid crystal image display device according to claim 28, wherein the etching is wet etching. 32. The liquid crystal image display device according to claim 28, wherein the etching is dry etching. 33. The liquid crystal image display device according to claim 28, wherein the substrate removal portion has a transparent layer. 34. A Si single crystal layer in which an active region of a Si semiconductor active element is formed, and a liquid crystal layer are provided on the surface of a Si substrate whose surface is composed of a translucent insulating layer. The lower Si substrate is removed from the opposite side of the liquid crystal layer until it reaches the transparent insulating layer, allows visible light to pass through the liquid crystal layer, and has at least a SiN _x insulating layer in the transparent region. A liquid crystal image display device characterized by being provided. 35. A liquid crystal layer comprising a Si single crystal layer in which an active region of a Si semiconductor active element is formed and a liquid crystal layer on the surface of a Si substrate whose surface is composed of a translucent insulating layer. The lower Si substrate is removed from the opposite side of the liquid crystal layer until it reaches the transparent insulating layer, allows visible light to pass through the liquid crystal layer, and has at least a SiN _x insulating layer in the transparent region. In the liquid crystal image display device provided, the Si single crystal layer is formed on a porous Si semiconductor, and then the surface of the Si substrate is bonded onto the Si single crystal layer, A liquid crystal image display device, which is obtained by removing a porous semiconductor layer by etching. 36. An active matrix type liquid crystal display device having a semiconductor active element in which an active layer is formed of a single crystal Si thin film formed on a semiconductor or conductor substrate via an insulating layer, wherein an image display section is provided. By removing the substrate and removing only the insulating layer, or by removing the substrate and then filling it with a transparent filler, the substrate has transparency, and the peripheral drive circuit section is left with the substrate and has a back surface potential control means. A liquid crystal display device characterized by the above. 37. A semiconductor or a conductive substrate is provided with a portion which is a semiconductor or a conductive substrate with an insulating layer interposed therebetween, and a portion which is a semiconductor or a conductive substrate is provided above the peripheral circuit or the insulating layer only. The image display area is provided in the area, and the connection between the two is made with the same wiring material as that used in the peripheral circuit and the image display area, and the wiring is more than the transition area of the semiconductor or conductor substrate thickness. An image display device having a wide area.