JP3526986B2 - Semiconductor circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to a semiconductor circuit including a thin film transistor and a method for manufacturing the semiconductor circuit. The semiconductor circuit according to the present invention,
It can be manufactured either on an insulating substrate such as glass or on a semiconductor substrate such as single crystal silicon. In particular, the invention disclosed in this specification relates to a matrix circuit which is required to have a low off-current and a small variation in the off-current for each element, such as a monolithic active matrix circuit used for a liquid crystal display or the like. It is effective in a semiconductor circuit having a peripheral circuit that requires high-speed operation for driving the same and small variation in on-current.

[0002]

2. Description of the Related Art In recent years, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (hereinafter referred to as TFTs)
Is called) is being enthusiastically studied. For example, in a liquid crystal display device having a matrix structure, a TFT is formed on a transparent insulating substrate and used as a switching element of a pixel or a driver element of a driving circuit.

TFTs are classified as amorphous silicon TFTs or crystalline silicon TFTs depending on the material and crystalline state of the thin film semiconductor used. In general, an amorphous semiconductor has a low electric field mobility, and therefore cannot be used for a TFT that requires high-speed operation. Therefore, recently, crystalline silicon T has been used to fabricate higher performance circuits.
Research and development of FT is underway.

A crystalline semiconductor has a larger electric field mobility than an amorphous semiconductor and can operate at high speed. With crystalline silicon, not only the NMOS TFT but also the PMO
Since the S TFT can be obtained similarly, it is possible to form a CMOS circuit. For example, a CMOS circuit forming a peripheral circuit (driver or the like) in an active matrix type liquid crystal display device can be formed of TFTs.
As a method for obtaining a crystalline silicon film, a method of thermally annealing amorphous silicon at a high temperature of about 600 ° C. or higher for a long time, or a method of irradiating strong light such as laser light (optical annealing method) is known. Has been.

FIG. 1A shows a block diagram of a typical monolithic active matrix circuit used in a liquid crystal display. A column decoder / driver 1 and a row decoder / driver 2 are provided on the glass substrate 7 to form peripheral circuits. Further, in the matrix region 3, pixels 4 composed of switching transistors and capacitors are arranged in a matrix. The peripheral circuit and the matrix circuit are connected by the same number of wirings 5 and 6 as the number of rows and columns.

In the active matrix circuit shown in FIG. 1A, the TFT used in the peripheral circuit is required to operate at high speed. Therefore, it is required that the current at the time of selection (ON current) is large and the dispersion of the ON current value is small for each element. On the other hand, T used in the matrix circuit
The FT is required to have a characteristic that the charge accumulated in the capacitor is retained for a long time. That is, it is required that the off-current (leakage current) at the time of non-selection (the state in which the reverse bias voltage is applied to the gate electrode) be sufficiently small and that the value of this off-current be small for each element. . On the contrary, the on-current does not need to be so large. Specifically, the off current is required to be 1 pA or less, and its dispersion is required to be within one digit. As described above, the TFTs in the peripheral circuit region and the matrix circuit are required to have characteristics that are physically contradictory to each other. However, it is possible to form TFTs satisfying the respective characteristics on the same substrate by the same process. It has been demanded.

[0007]

However, in general, all TFTs manufactured by the same process show similar characteristics. For example, a TFT using crystalline silicon crystallized by thermal annealing (thermal annealing) shows the same characteristics as the TFT in the matrix region and the TFT in the peripheral circuit region. That is, the obtained TFT can satisfy only the characteristics of low off current or high on current.
This also applies to the case where silicon crystallized by irradiation with intense light such as laser light is used. As described above, the T having a low off-current characteristic suitable for the matrix circuit.
FT and TF having high on-current characteristics suitable for peripheral circuits
It is difficult to fabricate T and T on the same substrate.

An object of the invention disclosed in the present specification is to solve the above problems and to provide a TFT having a low off-current characteristic suitable for a matrix circuit suitable for a peripheral circuit and a TFT having a high on-current characteristic. It is to provide a semiconductor circuit in which the above are integrated on the same substrate. Another object of the present invention is to provide a technique for manufacturing a TFT having a low off-current characteristic and a TFT having a high on-current characteristic on the same substrate by using the same process. .

[0009]

In order to solve the above-mentioned problems, the structure of the semiconductor circuit according to the present invention is a monolithic active matrix circuit, in which the active region of the thin film transistor of the peripheral circuit contains a catalytic element, The concentration of the catalytic element in the active region of the thin film transistor of the matrix circuit is lower than that in the active region of the thin film transistor of the peripheral driving circuit, and the thin film transistor of the matrix circuit has a pair of high concentration impurity regions forming a source region and a drain region. And a pair of low-concentration impurity regions formed between the source region and the drain region and the channel formation region.

According to the results of the research conducted by the present inventor, crystallization of silicon is promoted and the crystallization temperature is lowered by adding a trace amount of a metal element to a silicon film in a substantially amorphous state. It has been clarified that the crystallization time can be shortened. Fe, C as the catalyst material
o, Ni, Rh, Pd, Os, Ir, Pt, Cu, Au
One or more kinds of elements selected from can be used.

To obtain a crystalline silicon film containing a catalytic element, specifically, a film, particles, clusters, etc. having a catalytic element are brought into close contact with amorphous silicon, or an amorphous silicon film is formed by a method such as an ion implantation method. These catalytic elements are introduced therein. Next, this is heated typically at a temperature of 450 to 580 ° C. for about 4 to 8 hours. By doing so, a crystalline silicon film can be obtained.

More interestingly, it has been revealed that the crystallization of silicon proceeds as the catalytic element diffuses. Therefore, the region in the vicinity where the catalyst element is added is crystallized by the diffusion of the catalyst element. That is, as the catalytic element diffuses, crystallization proceeds in the lateral direction. Such a crystallization method is called horizontal growth. On the other hand, a crystallization method that does not particularly intend to grow crystals in the lateral direction is called vertical growth. Since the crystalline silicon thus obtained has crystal orientation, it exhibits electrically extremely preferable characteristics.

In addition to the above-mentioned thermal annealing, crystallization can be similarly performed by irradiating laser light or intense light equivalent thereto. The energy density of laser light or strong light equivalent thereto depends on the wavelength of the light source to be irradiated, the pulse width, the temperature of the amorphous silicon (or crystalline silicon) film, and the like.

Observation with a TEM (transmission electron microscope) has confirmed that the silicon film crystallized by thermal annealing has an uncrystallized portion. But,
Laser light is applied to a silicon film that has been crystallized by irradiation with intense light such as laser light, or a silicon film that has been crystallized to some extent by thermal annealing.
It has been found that the above-mentioned uncrystallized portion hardly exists and the crystallinity is extremely good.

By doing so, the degree of crystallization can be improved. Further, the barrier of the crystal grain boundary, which cannot be removed only by thermal annealing, is weakened, and the amorphous component remaining in the grain boundary can be crystallized. Further, when such a method is adopted, complete crystallization can be achieved by subsequent laser irradiation even if the degree of crystallization due to thermal annealing is low.

The TFT obtained by using the silicon film crystallized by using the catalytic element in this way can have a large on-current and a small variation in the on-current. That is, it can be a device suitable for a peripheral circuit of an active matrix circuit.
However, a TFT obtained by using a silicon film crystallized by using a catalytic element has a large variation in off current. This is a fatal drawback for use in matrix circuits. This variation in the off-current is presumed to be derived from the catalytic element, but the fact is not clear.

However, this does not mean that the catalytic element is not practical. Because the catalyst element can be added selectively, a silicon film crystallized using the catalyst element and a silicon film crystallized without the catalyst element are formed on the same substrate. It is possible. Therefore, by using the silicon film crystallized using the catalytic element, the TFT of the peripheral circuit can be
Can have a high mobility, and by using a crystallized silicon film without using a catalytic element, the TFT of the pixel matrix circuit has a low mobility but a low off-current characteristic. Can be one.

Although the silicon is crystallized by using the catalytic element, the catalytic element is not preferable for silicon. Therefore, it is desirable that the concentration of the catalytic element be as low as possible. (In this respect, a method of introducing a catalytic element using a solution is advantageous.) Also, by irradiating a coating having a catalytic element with laser light or strong light equivalent thereto, the catalytic element necessary for crystallization can be changed. The concentration can be lowered.

In order to selectively vary the concentration of the catalytic element, the introduction amount of the catalytic element is selectively controlled. When the ion doping method is used, the dose amount may be selectively controlled. When the layer containing the catalytic element is formed in close contact with the silicon film, the thickness of the layer and the concentration of the catalytic element in the compound forming the layer may be selectively controlled. Further, in order to prevent the selective introduction of the catalytic element, a mask is used to prevent the selective introduction of the catalytic element.

According to the results of the research conducted by the present inventor, the concentration of the catalytic element is 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁸ atoms / cm ³ . By doing so, it has been found that it is possible to obtain a crystalline semiconductor that does not hinder the formation of a semiconductor element. Therefore, the content concentration of the catalytic element is 1 × in the silicon film of the TFT of the peripheral circuit.
10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ is preferable, and 1 × 10 5 in the silicon film of the TFT of the matrix circuit.
It is preferably less than ¹⁵ atoms / cm ³ . Note that secondary ion mass spectrometry (SIMS) may be used as a method for measuring such a minute amount of concentration. In this case, even with the same silicon film, the concentration near the interface and the inside of the film may be measured differently. However, the concentration of the catalytic element should be the minimum measured value regardless of the interface or inside of the silicon film. Is defined.

Alternatively, it is easy to define the amount of the catalytic element introduced into the silicon film by the amount per unit area (that is, the dose amount) rather than the concentration. Therefore, in the semiconductor circuit according to the present invention, the amount of the catalytic element contained in the active region of the thin film transistor of the peripheral circuit per unit area is the amount of the catalytic element contained in the active region of the thin film transistor of the matrix circuit per unit area. It is preferably 10 times or more.

Further, in the semiconductor circuit according to the present invention,
In particular, in order to ensure low off current characteristics in the TFT of the matrix circuit, a lightly-doped low-impurity region is formed between the source and drain regions and the channel formation region. The drain side region of the low impurity region is generally called an LDD (lightly doped drain) region. Since the LDD region functions as a high resistance region, off current can be reduced. Further, a so-called offset gate region may be formed in the TFT of the matrix circuit between the channel forming region and the low concentration impurity region. Since the offset gate region also functions as a high resistance region, the off current can be further reduced.

An offset region may be formed in the TFT of the peripheral circuit in order to further reduce the off current. However, since the LDD region and the offset region are high resistance regions, the mobility of the TFT is lowered, so it is necessary to prevent the mobility of the TFT in the peripheral circuit from being impaired. Therefore, for example, the width of the LDD region and the offset region may be narrower than that of the TFT of the peripheral circuit.

The steps of forming the semiconductor circuit having the above-mentioned structure are as follows: (1) First step of forming a film containing a catalytic element on a silicon film in an amorphous state and substantially adhering thereto.
And a step of forming a second region in which the coating film having substantially the catalytic element is in close contact with the silicon film and is not formed. (2) By heat treatment, only the first region or the first region
Of crystallizing the region and the second region. (3) The regions of the first and second silicon films are irradiated with laser light or intense light equivalent thereto to crystallize or accelerate crystallization.
Alternatively, a step of increasing crystallinity. (4) A step of etching the silicon film to form an island-shaped active region. Consists of.

Alternatively, other steps for forming the semiconductor circuit having the above-described structure are as follows: (1) ′ The first region where the catalytic element is intentionally introduced into the silicon film and the catalytic element is intentionally introduced into the silicon film. Step (2) ′ of forming a second region which is not introduced in the step (2) ′ A step of performing a heat treatment to crystallize the first or the first and second regions. (3) ′ A step of crystallizing, accelerating crystallization, or enhancing crystallinity by irradiating the silicon film in the first and second regions with a laser or strong light equivalent thereto (4) The process comprises etching the silicon film to form an island-shaped active region.

When the catalyst element is formed into a film, the concentration of the catalyst element is sufficiently low so that the film thickness becomes extremely thin. As one of the methods for forming such a coating, there is a method using a vacuum device such as sputtering or vacuum deposition. Further, as another method, there is a method such as a spin coating method or a dip (immersion) method which is performed under atmospheric pressure. These methods are simple and highly productive. In this case, a solution prepared by dissolving an acetate salt, a nitrate salt, an organic acid salt or the like containing a catalytic element in an appropriate solvent and adjusting the concentration to an appropriate value may be used.

It is difficult to form an extremely thin film of 100 Å or less uniformly by a general physical film forming method such as sputtering or vacuum vapor deposition, and finally the concentration of the catalytic element in the silicon film is increased. It has the disadvantage of being difficult to control.

In particular, the spin coating method using a solution is a useful means for achieving uniform crystal growth because the catalyst element can be made to exist uniformly and thinly. Further, in this method, since the concentration of the catalyst element in the solution can be easily controlled, the concentration of the catalyst element in the silicon film can be finally easily controlled.

In the above step (1), it is required that the coating film containing the catalytic element adheres "substantially" to the silicon film. Here, "substantially" may be in direct contact or may be in indirect contact via a thin film. This is because the catalyst element can be introduced even if a thin silicon oxide film having a thickness of several tens of liters is present.

In the step (1) ', the region into which the catalytic element is introduced may be formed by means such as an ion implantation method. Alternatively, the catalytic element may be introduced by forming a film of the catalytic element compound and performing thermal annealing.

In the above step (1) ', even if the region into which the catalytic element is introduced is heated, it does not always crystallize. For example, when heat treatment is applied at a temperature of about 300 ° C., the amorphous silicon does not crystallize, but the catalytic element can be diffused into the amorphous silicon.

The following four are considered as preferable embodiments of the invention disclosed in this specification. The first is a method in which the peripheral circuit and the matrix circuit are crystallized by arranging the peripheral circuit so that the catalytic element is selectively added and then performing optical annealing by irradiating laser light over the entire surface of the substrate. In this case, since the annealing effect due to the irradiation of the laser beam varies depending on the presence or absence of the catalyst element or the difference in the concentration of the catalyst element, regions having different crystallinity can be selectively obtained.

Secondly, after arranging so as to selectively add the catalyst element mainly to the peripheral circuit, thermal annealing is carried out to mainly crystallize the peripheral circuit or enhance the crystallinity. After that, optical annealing is performed by irradiating laser light over the entire surface of the substrate to crystallize both the peripheral circuit and the matrix circuit, or to increase the crystallinity.

The higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of the catalyst element, the lower the crystallization temperature, and at the same time, the shorter the crystallization time. If the thermal annealing is performed at a high temperature of 600 ° C. or higher, the entire surface including the region where the catalytic element is not introduced is crystallized, but if the heating is performed at 550 ° C. for about 4 hours, the catalytic element is introduced. It is possible to selectively crystallize only the formed region or the region where the concentration of the catalyst element is high. Then, the photo-annealing can promote the crystallization of the previously crystallized region and the crystallization of the uncrystallized region.

Thirdly, after arranging so as to selectively add the catalyst element mainly to the peripheral circuit, optical annealing is performed over the entire surface of the substrate to crystallize both the peripheral circuit and the matrix circuit or to enhance the crystallinity. After that, it is a method of performing thermal annealing.

Fourthly, after arranging so that the catalyst element is selectively added mainly to the peripheral circuit, thermal annealing is performed to mainly crystallize the peripheral circuit or enhance the crystallinity. After that, optical annealing is performed over the entire surface of the substrate to crystallize the peripheral circuits and the matrix circuit or to enhance the crystallinity. Furthermore, after that,
This is a method of performing thermal annealing. In the second and fourth methods described above, there is a step of performing crystallization by thermal annealing using a catalytic element, but it may be horizontal growth or vertical growth.

Using a quartz substrate as the substrate and performing the heat treatment for crystallization at a temperature of 800 ° C. to 1100 ° C. is very useful in terms of obtaining higher crystallinity. In this case, the action of the metal element that promotes crystallization can be utilized to the maximum extent, and a crystalline silicon film having extremely excellent crystallinity can be obtained.

[0038]

In the semiconductor circuit having the above structure, a TFT of an active matrix circuit is manufactured by using a silicon film having a small amount of catalytic element. By introducing or not introducing the catalytic element into the silicon film at a low concentration, an active region having a low degree of crystallization (relatively low order) can be formed. By using such an active region, it is possible to obtain a TFT having low mobility, but low variation in off-current characteristics.

Further, a TFT for a peripheral circuit is manufactured by using a silicon film containing a large amount of catalytic elements. That is, by introducing the catalytic element into the silicon film at a relatively high concentration and utilizing its action, an active region having a high degree of crystallization (relatively high order) can be formed. By using the active region, it is possible to obtain a TFT having a large mobility and allowing a large ON current to flow.

That is, a TFT having a low off current characteristic,
Two types of TFTs having contradictory characteristics, that is, TFTs having high on-current characteristics, are selectively formed on the same substrate and in a series of the same process.

In particular, T arranged in the pixel matrix area
By forming the LDD region in the FT, the TFT arranged in the pixel matrix region can be made to have a low off-current characteristic.

In the invention disclosed in this specification, it is required that the concentration of the catalyst element in the portion forming the TFT, which requires a low off-current, be lower than the concentration of the catalyst element in the portion forming the high speed TFT. It Regarding the difference in concentration, it is preferable that the amount of the catalytic element per unit area in the latter region is 10 times or more that in the former case.

In particular, the catalytic element forms a trap level in the silicon film and becomes a factor of deteriorating the off current characteristic. Therefore, the silicon film forming the TFT arranged in the pixel region where low off current characteristic is required. It is preferable not to exist in them.

The reason why the catalytic element deteriorates the off-current characteristic is as follows. That is, the carriers passing through the trap levels existing due to the catalytic element contribute to the off current,
This leads to an increase in off current.

Specifically, in order to further reduce the off current, it is desirable that the concentration of the catalyst element in the active region of the TFT, which requires a low off current, be less than 1 × 10 ¹⁵ atoms / cm ³ .

Further, a low concentration impurity region is arranged in a thin film transistor arranged in a circuit requiring a low off-current characteristic, and a low concentration impurity region is arranged in a thin film transistor arranged in a region requiring a high speed operation. It is preferable not to arrange them. However, in order to obtain the required characteristics, the low-concentration impurity region may be formed in the thin film transistor of the peripheral circuit which is required to operate at high speed.

The four aspects of the invention disclosed in the specification set forth above.
In one preferred embodiment, in the third and fourth cases, thermal annealing is performed after optical annealing. This is effective in removing the stress strain generated by the optical annealing. Further, when photo-annealing is performed by laser light irradiation, defects are formed in the film, and thermal annealing is also effective in reducing the defects.

In the second and fourth cases, thermal annealing is performed after the catalyst element is added. In this step, crystallization proceeds in the region where the catalyst element is added,
Even in the region where the catalyst element is not added, hydrogen is sufficiently released from the amorphous silicon film, so that the effect of the subsequent optical annealing can be further enhanced. For such a purpose, the thermal annealing is 450-
It may be carried out at 580 ° C. for 0.5 to 8 hours.

The effect of the semiconductor circuit according to the present invention is most prominent when it is applied to a monolithic active matrix circuit. However, the effect is not limited to the monolithic active matrix circuit and can be applied to other circuits. It is clear to have

For example, as shown in FIG. 1B, it is considered that the present invention is applied to a system in which a liquid crystal display device and a control unit including a computer are integrated. The liquid crystal display device includes a row decoder / driver, a column decoder / driver, and an active matrix circuit. On the other hand, the control unit controls C for controlling the entire device.
It has a PU, and the CPU is connected to the correction memory and the input / output of the memory. Furthermore, the output of the input port for inputting information from the outside of the device is connected to the CPU, and the output of the CPU is connected to the row decoder / row via the XY branch.
It is connected to the driver and the column decoder / driver respectively. The correction memory is for storing the characteristics of each pixel as data, and it is preferable to use a non-volatile memory for this. Random access memory such as DRAM, SRAM
It may be a memory (RAM).

The semiconductor circuit of the present invention can be applied to the peripheral circuit and active matrix circuit of the liquid crystal device as described above. Here, the present invention is applied to the correction memory of the control unit, the memory, and the transistor used in the CPU. Consider applying the invention. Since the memory is a RAM, it is required that the off-state current is small and the dispersion of the value is small for each element. Further, the transistor used in the CPU is required to operate at high speed.

In this case, a crystalline silicon film formed without introducing a catalytic element is used for the memory transistor, and a crystalline silicon film formed by introducing a catalytic element is used for the CPU transistor. You can use it. This contradiction can be resolved. Since the correction memory has a particularly low off-current and does not require an excellent high-speed operation, a transistor of the correction memory is manufactured using a crystalline silicon film that does not introduce a catalytic element,
Data can be held stably.

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on the illustrated embodiments. [Embodiment 1] FIG. 2 shows a manufacturing process of this embodiment. FIG. 2 shows a manufacturing process of one of the substrates included in the active matrix liquid crystal display device. The present embodiment relates to a method for manufacturing a monolithic active matrix circuit, in which the peripheral circuit is CMOS. Figure 2
For simplicity, only the NMOS is shown in the peripheral circuit portion, the left side is the peripheral circuit, and the right side is the matrix circuit.

First, a silicon oxide film 20 serving as a base film having a thickness of 2000 Å is formed on a glass substrate 201 by a plasma CVD method.
2 is formed into a film. Monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O) were used as source gases, and the substrate temperature during film formation was 3
The temperature is 80 to 500 ° C., for example, 230 ° C.

The silicon oxide film 202 thus formed
Has a relatively low etching rate and can be a hard film. Since this uses nitrous oxide as the source gas,
This is because the film becomes a silicon oxynitride film containing 1 to 10% of nitrogen. A typical etching rate of the silicon oxide film 202 is acetic acid buffered hydrofluoric acid (AB) in which the ratio of hydrofluoric acid, ammonium fluoride and acetic acid is 1:50:50.
800-1 in etching at 23 ° C. with HF)
It becomes about 100Å / min. After that, an amorphous silicon film 203 having a thickness of 500Å is formed by plasma CVD method or low pressure thermal CVD method.

Further, a thickness of 1 is formed by the plasma CVD method.
A 000Å silicon oxide film 204 is formed. In this case,
TEOS and oxygen are used as source gases. The silicon oxide film 204 thus formed has a higher etching rate than the silicon oxide film 202 previously formed, and is typically 2000 to 3000 Å / min (ABHF, 23
° C) is shown. Next, the silicon oxide film 204 is patterned by a known photolithography method. In this way, only the amorphous silicon film 203 in the peripheral circuit region is exposed. The silicon oxide film 204 functions as a mask when introducing a catalytic element that promotes crystallization of silicon. Further, by performing thermal annealing at 550 ° C. for 1 hour in an oxidizing atmosphere, an extremely thin (estimated to be 40 to 100 Å) silicon oxide film is formed on the exposed surface of the amorphous silicon film 203.

1-100 by spin coating
An extremely thin nickel acetate thin film 205 is formed by applying a ppm nickel acetate aqueous solution. As a result, a nickel element, which is a catalytic element that promotes crystallization of silicon, is brought into contact with and held on the amorphous silicon film 203. The thin silicon oxide film is formed on the surface of the amorphous silicon film 203 in advance so that the aqueous solution can be uniformly applied to the surface of the amorphous silicon film 203. (Fig. 2 (A))

Next, in a nitrogen atmosphere, at 550 ° C.,
Perform thermal annealing for 4 hours. The nickel acetate thin film 205 decomposes into nickel at about 400 ° C. In the peripheral circuit region, since the nickel acetate thin film 205 is in close contact with the amorphous silicon film 203, the nickel element is removed by the thermal annealing process.
Spread to 03. As a result, the amorphous silicon film 2
03 is crystallized (vertical growth), and the crystalline silicon region 2
06a is formed.

On the other hand, since the silicon oxide film 204 exists in the matrix circuit region, the nickel element cannot diffuse into the amorphous silicon film 203. Further, since the amorphous silicon without the catalytic element is hardly crystallized by the thermal annealing at 550 ° C., the amorphous silicon film 203 in the matrix circuit region remains in the amorphous state, but hydrogen in the film is released.

The amorphous silicon film 203 deposited by the CVD method (particularly the plasma CVD method) has a high hydrogen content and contains about 10% or more of hydrogen in the formed state. Hydrogen contained in the amorphous silicon film 203 in the matrix circuit region is sufficiently released, so that the hydrogen content becomes 0.
It is possible to obtain amorphous silicon containing almost 1% or less of silicon. The amorphous silicon from which hydrogen is desorbed can be crystallized very easily, and can be crystallized with good reproducibility by irradiation with laser light.

After the thermal annealing process, the silicon oxide film 204, which is a mask for nickel element, is removed to expose the amorphous silicon film 203 in the matrix region, and XeCl excimer laser light (wavelength 308 nm) is used.
Irradiate. In this embodiment, the energy density of the laser is 250 to 300 mJ / cm ² . As a result, the crystallinity of the crystalline silicon region 206a is further improved. In addition, the amorphous silicon film 20 in the matrix circuit area
3 is crystallized and transformed into a crystalline silicon region 206b. Furthermore, in order to alleviate the stress strain due to laser irradiation, thermal annealing is performed again. In this embodiment, 5
Thermal annealing is performed at 50 ° C. for 4 hours. (Fig. 2 (B))

In this embodiment, since the hydrogen concentration of the amorphous film 203 in the matrix circuit region is sufficiently reduced in the thermal annealing process before laser irradiation, the crystalline silicon region 206b is irradiated even when the laser beam irradiation is low in energy density. Has the required crystallinity.

Then, the crystalline silicon regions 206a, 2
06b are respectively etched to form island-shaped active regions 207.
a and 207b are formed. Thickness 1 by sputtering method
A 200 Å silicon oxide film 208 is formed as a gate insulating film. Further, a 4000 Å thick aluminum film (containing 0.2 to 0.5% by weight of scandium) is formed by the sputtering method. Then, the surface thereof is anodized to form an aluminum oxide film (not shown) having a thickness of 100 to 300 Å, then photoresist masks 209a and 209b are formed, and the aluminum film is etched to form a gate electrode. 210a and 210b are formed. Note that the photoresist masks 209a and 209b used for etching are left as they are. ((Figure 2
(C))

Next, the applicant of the present invention disclosed in Japanese Unexamined Patent Publication No. 6-3386.
As disclosed in No. 12, photoresist mask 2
Porous anodic oxidation is performed with 09a and 209b attached.
In this step, porous anodic oxides 211a and 211b are formed on the side surfaces of the gate electrodes 210a and 210b. In this embodiment, the thickness of the porous anodic oxides 211a and 211b is 3000 to 10000Å, for example 5000Å.
The thickness of the porous anodic oxides 211a and 211b determines the width of the low concentration impurity region formed later. Next, photoresist masks 209a and 209b
And the gate electrodes 210a and 210b are anodized to form the dense anodic oxide coatings 212a and 212b.
Form to a thickness of 00Å. (Fig. 2 (D))

The anodic oxide coatings 212a and 212b have two major roles. First, when aluminum is used as the gate electrode material, it has a role as a barrier film for preventing abnormal growth and dissolution of aluminum in the subsequent heating process and laser light irradiation process. The second is to form the offset gate region by using the dense anodic oxide coatings 212a and 212b as a mask in the subsequent impurity ion implantation step. The thickness of the dense anodic oxide coatings 212a and 212b can be selected from the range of about 100Å to 3000Å, but the thickness of the offset gate region is 100.
If the thickness is not more than 0Å, its role will not be significant, so the thickness of the dense anodic oxide coatings 212a, 212b will be 100
0 Å or more is required.

In addition, the porous anodic oxides 211a, 2
11b and the dense anodic oxide coatings 212a and 212b can be made separately by changing the electrolytic solution at the time of anodic oxidation. Porous anodic oxides 211a, 211
If b is formed, the electrolytic solution may be, for example, 3
% Oxalic acid may be used. The dense anodic oxide 212
If a and 212b are to be formed, 3 as an electrolytic solution
% Tartaric acid may be used.

Next, the porous anodic oxides 211a, 211
The silicon oxide film 208 is etched by the dry etching method using b as a mask to form the gate insulating films 213a and 213a.
13b is formed. Further, using a mixed solution of phosphoric acid, acetic acid and nitric acid (aluminum mixed acid), porous anodic oxide 211a,
Only 211b is etched. Aluminum mixed acid etches the porous anodic oxides 211a and 211b, but the dense anodic oxide coatings 212a and 212b are hardly etched. Will remain.

Then, the gate insulating films 213a, 213
Impurities are introduced into the active region by an ion doping method using 3b as a mask. When forming an NMOS transistor, phosphorus is doped. When manufacturing a PMOS transistor, boron is doped. In this embodiment, the peripheral circuit is composed of CMOS, but
Only NMOS transistors are shown in FIG.

When doping phosphorus, first, 10 to
5 × 10 ^{14 to} 5 × 1 with a relatively low acceleration voltage of 30 keV
Phosphorus ions are implanted at a relatively high dose of 0 ¹⁵ atoms / cm ² . At this time, since the accelerating voltage is low and the ion penetration depth is shallow, phosphorus is mainly implanted into the regions of the active regions 207a and 207b that are not covered with the gate insulating films 213a and 213b.

Next, phosphorus ions are implanted again at a relatively high acceleration voltage of 60 to 95 keV and at a relatively low dose of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² . In this case,
Since the acceleration voltage is high, ions penetrate deeply,
The gate insulating film 2 is formed in the active regions 207a and 207b.
Phosphorus is also implanted into the region covered with 13a and 213b. Boron is also doped by the same method. After doping the impurity ions, laser light is irradiated to activate the impurity ions. (Fig. 2 (E))

As a result, the high-concentration impurity regions 214a and 214b doped with a high-concentration impurity and the low-concentration impurity regions 215a and 21b doped with a low-concentration phosphorus are doped.
5b and 5b are respectively formed so as to form a so-called double drain structure. Note that the low-concentration impurity regions 215a,
The drain side of 215b becomes a region generally called an LDD region.

Further, since impurity ions do not substantially invade the lower layers of the gate electrodes 210a and 210b, they become channel forming regions. Offset gate regions 216 and 21 are the regions between the channel forming region and the drain side of the low concentration impurity regions 215a and 215b, that is, the LDD regions.
7 The offset gate regions 216 and 217 are LDs
The same effect as in the case of providing the D region can be obtained, and an effect of reducing the off current is produced. The offset gate regions 216 and 217 are formed because the dense anodic oxide coatings 212a and 210b formed around the gate electrodes 210a and 210b function as masks during the implantation of impurity ions.

After that, as a first interlayer insulator, a silicon oxide film 218 having a thickness of 4000 Å is formed by a plasma CVD method.
Is deposited, a contact hole is formed in this, and aluminum electrodes / wirings 219a to 219c are formed. Further, as a second interlayer insulator, a 2000-Å-thick silicon nitride film 220 is deposited by a plasma CVD method, a contact hole is formed on the drain side of the TFT in the matrix region, and a pixel electrode 221 made of ITO is formed. In this way, a monolithic active matrix circuit can be formed. (Fig. 2 (F))

The typical field effect mobility of the NMOS TFT manufactured in this embodiment is 140 to 180 in the peripheral circuit.
cm ² / Vs, matrix circuit 20 to 30 cm ² / V
can be s. Further, the off-state current of the matrix circuit can be 1.3 pA on average, and the variation (3σ) can be less than one digit.

[Embodiment 2] This embodiment will be described with reference to FIG. First, a silicon oxide film 202 serving as a base film having a thickness of 2000Å is formed on a glass substrate 201 by a plasma CVD method.
An amorphous silicon film 203 having a thickness of 500 Å is formed by a low pressure CVD method, and a silicon oxide film 204 having a thickness of 1000 Å is further formed by a plasma CVD method.

Then, the silicon oxide film 204 is etched to expose only the amorphous silicon film 203 in the peripheral circuit region. Further, by immersing the substrate in an ammonia solution of hydrogen peroxide water, the exposed surface of the amorphous silicon film 203 is extremely thin (40 to 100).
Form a silicon oxide film (presumed to be Å). Then, as in Example 1, an extremely thin nickel acetate thin film 205 is formed by the spin coating method. (Fig. 2 (A))

After that, thermal annealing is performed at 400 ° C. for 0.5 hour. In this step, the nickel acetate thin film 205 is decomposed, and nickel element is slightly diffused in the amorphous silicon film 203. The silicon oxide film 204 is removed to expose the amorphous silicon film 203. Buffer hydrofluoric acid is used in the step of etching the silicon oxide film 204. At this time, the amorphous silicon film 203
Although the nickel remaining on the upper surface and the surface layer of the amorphous silicon film 203 having a high nickel concentration are etched, a sufficient amount of nickel for crystallization is diffused and present in the amorphous silicon film 203. .

Then, XeCl excimer laser light (wavelength 308 nm) is irradiated. In this embodiment, the energy density of the laser may be in the range of 300~400mJ / cm ^2, for example, and 350 mJ / cm ^2.
As a result, the amorphous silicon film 203 in the peripheral circuit region and the matrix circuit region is crystallized and transformed into crystalline silicon regions 206a and 206b. In particular, the crystalline silicon region 206a has excellent crystallinity because of the catalytic action of nickel element.

In this embodiment, the amorphous silicon film 2 is used.
Since 03 is formed by the low pressure CVD method, the hydrogen content is small in the film-formed state. Therefore, the silicon film 203 in the matrix circuit region does not contain nickel element during laser irradiation, but can be transformed into a crystalline silicon region having appropriate crystallinity by irradiation with laser light having a low energy density. (Fig. 2 (B))

After that, thermal annealing is performed to alleviate the stress strain caused by laser irradiation. In this embodiment, 55
Thermal annealing is performed at 0 ° C. for 4 hours. Next, the crystalline silicon regions 206a and 206b are etched to form island-shaped active regions 207a and 207b. A silicon oxide film 208 having a thickness of 1200Å is formed as a gate insulating film. Further, a 4000Å thick aluminum film (containing 0.2 to 0.5% by weight of scandium) by the sputtering method.
To form. A photoresist mask 209 on this surface
a and 209b are formed. These masks 209a, 2
09b is used to etch the aluminum film,
Gate electrodes 210a and 210b are formed. The photoresist masks 209a and 209b used for etching are left as they are. (Fig. 2 (C))

Next, the gate electrodes 210a and 210b are anodized to form porous anodic oxides 211a and 211b and dense anodic oxide coatings 212a and 212b, respectively. (Fig. 2 (D))

Next, the porous anodic oxides 211a, 211
The silicon oxide film 208 is etched by the dry etching method using b as a mask, and the gate electrodes 210a, 21
0b under the gate insulating films 213a, 213 of silicon oxide.
b is left. Using the gate insulating films 213a and 213b as a semi-transparent mask, impurities are introduced into the active region by the ion doping method. As a result, the high-concentration impurity regions 214a and 21a doped with high-concentration impurities
4b and low-concentration impurity regions 215a and 215b doped with low-concentration impurities are formed, respectively. The drain side of the low-concentration impurity regions 215a and 215b is a region generally called an LDD region. Further, since impurity ions do not substantially invade the lower layers of the gate electrodes 210a and 210b, they serve as channel formation regions. Offset gate regions 216 and 217 are formed between the channel formation region and the LDD region. (Fig. 2 (E))

After that, the first interlayer insulator (silicon oxide film)
218, aluminum electrodes / wirings 219a to 217
c, the second interlayer insulator (silicon nitride film) 220, and the pixel electrode 221 made of ITO are sequentially formed. In this way, a monolithic active matrix circuit can be formed. (Fig. 2 (F))

[Embodiment 3] FIG. 3 shows a manufacturing process of this embodiment. This embodiment relates to a method for manufacturing a monolithic active matrix circuit, in which the left side represents a peripheral circuit and the right side represents a matrix circuit. In addition,
Although the peripheral circuit is formed into CMOS, only NMOS is shown in FIG. 3 for simplification.

First, a silicon oxide film 30 is formed on a glass substrate 301 by plasma CVD as a base film having a thickness of 2000 liters.
2 is formed into a film. Further, by a plasma CVD method, an amorphous silicon film 303 having a thickness of 500Å and a thickness of 100 is formed.
A 0Å silicon oxide film 304 is sequentially formed.

The silicon oxide film 304 is patterned by a known photolithography method to form a window 305 for selectively introducing a catalytic element into a part of the amorphous silicon film 303 in the peripheral circuit region. The patterned silicon oxide film 304 functions as a mask for selectively introducing nickel, which is a catalytic element that promotes crystallization of silicon, and the amorphous silicon film 303 is exposed at the window 305.

By performing thermal annealing at 550 ° C. for 1 hour in an oxidizing atmosphere, an extremely thin (estimated to be 40 to 100 Å) silicon oxide film (not shown) is formed on the exposed surface of the amorphous silicon film 303. To do. Then, by a spin coating method, a nickel acetate aqueous solution of 1 to 100 ppm is used, and the solution is uniformly and thinly applied to the surface of the substrate 301 using a spin coater to form an extremely thin nickel acetate thin film 306. In the window 305, the nickel acetate thin film 306 is in close contact with the amorphous silicon film 303. (Fig. 3 (A))

Next, thermal annealing is performed at 550 ° C. for 8 hours in a nitrogen atmosphere. By this thermal annealing process, the window 3
In 05, the nickel acetate thin film 306 is decomposed, and nickel is added to the amorphous silicon film 303 in the peripheral circuit region.
It spreads and invades into the area of. As the nickel diffuses, the amorphous silicon film 303 in the peripheral circuit region
Crystallizes in the horizontal direction (horizontal growth) as shown by the arrow in the figure to form a crystalline silicon region 307a. (Fig. 3 (B))

On the other hand, the amorphous silicon film 303 in the matrix circuit region is not crystallized because nickel cannot reach silicon due to the presence of the silicon oxide film 304. However, due to this thermal annealing, the hydrogen contained in the amorphous silicon film 303 permeates the silicon oxide film 304 and is released to the outside, and the hydrogen content is reduced to 0.
1% or less of the amorphous silicon region 307b is formed.

Then, the silicon oxide film 304 is removed, the crystalline silicon region 307a and the amorphous silicon region 307b are exposed, and XeF excimer laser light (wavelength 353 nm) is irradiated. In this embodiment, the energy density of the laser is 250 to 300 mJ /
cm ² As a result, the crystalline silicon region 307a
Of the highly crystalline silicon region 3 is further improved.
08a. In addition, the amorphous silicon region 307
b is crystallized by irradiation with laser light and becomes a crystalline silicon region 308b. (Fig. 3 (C))

The crystalline silicon regions 308a and 308b are respectively etched to form island-shaped active regions 309a and 309a.
09b is formed. Then, monosilane and dinitrogen monoxide are used as source gases by the plasma CVD method to obtain a thickness of 1
A 200 Å silicon oxide film is formed as a gate insulating film.
Further, an aluminum film (containing 0.2 to 0.5% by weight of scandium) having a thickness of 4000 Å is formed by a sputtering method and is patterned to form the gate electrode 310.
a and 310b are formed.

The gate electrodes 310a and 310b are anodized to sequentially form porous anodic oxides 311a and 311b and dense anodic oxide coatings 313a and 313b. Then, the silicon oxide film under the gate electrodes 310a and 310b is etched to form the gate insulating films 312a and 312b.
To form. (FIG. 3D) In this example, the porous anodic oxide 311a,
The thickness of 311b is 3000Å, and the thickness of the dense anodic oxide coatings 313a and 313b is 1500Å.

Next, the porous anodic oxides 311a and 311 are used.
After etching b, impurity ions are doped to form source / drain regions. In the doping process, the gate insulating films 312a, 312b,
The gate electrodes 310a and 310b and the dense anodic oxide coatings 313a and 313b function as a mask, and the high concentration impurity regions 314a and 314b and the low concentration impurity region 31 are formed.
5a and 315b are formed, and offset gate regions 300a and 300b are further formed. (Fig. 3 (E))

The low-concentration impurity regions 315a and 315b are determined by the thickness of the porous anodic oxides 311a and 311b,
It becomes 3000Å. Also, the offset gate area 300
The thicknesses of a and 300b are the same as the dense anodic oxide coating 313.
It is determined by the thickness of a and 313b, and becomes 1500Å. Such a configuration is particularly useful when it is desired to obtain low off-current characteristics.

After that, the first interlayer insulator (silicon oxide film)
316 is formed by a sputtering method. Further, aluminum electrodes / wirings 317a, 317b, 317c, a second interlayer insulator (silicon nitride film) 318, and a pixel electrode 319 made of ITO are formed. In this way, a monolithic active matrix circuit can be formed. (Fig. 3 (F))

[Embodiment 4] This embodiment will be described with reference to FIG. In FIG. 3, the left side represents a peripheral circuit and the right side represents a matrix circuit.

The glass substrate 30 is formed by the plasma CVD method.
1, a silicon oxide film 302 having a thickness of 2000Å and a thickness of 50
0Å amorphous silicon film 303, thickness 1000Å
The silicon oxide film 304 is sequentially formed. Silicon oxide film 30
4 is patterned by a known photolithography method to form a window 305 for adding a catalytic element. Further, it is treated with a mixed solution of hydrogen peroxide solution and ammonia to form an extremely thin silicon oxide film on the surface of the amorphous silicon film 303 exposed in the window 305. Then, an extremely thin nickel acetate thin film 306 is formed by spin coating. (Fig. 3 (A))

Next, thermal annealing is performed at 550 ° C. for 8 hours in a nitrogen atmosphere. By this thermal annealing process, the window 3
In 05, the nickel acetate thin film 306 is decomposed, and nickel is added to the amorphous silicon film 303 in the peripheral circuit region.
It spreads and invades into the area of. As the nickel diffuses, the amorphous silicon film 303 in the peripheral circuit region
Crystallizes in the horizontal direction (horizontal growth) as shown by the arrow in the figure to form a crystalline silicon region 307a. (Fig. 3 (B))

On the other hand, the amorphous silicon film 303 in the matrix circuit region is not crystallized because nickel cannot reach silicon due to the presence of the silicon oxide film 304. However, due to this thermal annealing, the hydrogen contained in the amorphous silicon film 303 permeates the silicon oxide film 304 and is released to the outside, and the hydrogen content is reduced to 0.
1% or less of the amorphous silicon region 307b is formed.

After that, the silicon oxide film 304 is removed, the crystalline silicon region 307a and the amorphous silicon region 307b are exposed, and XeF excimer laser light (wavelength 353 nm) is irradiated. In this embodiment, the energy density of the laser is 250 to 300 mJ /
cm ² As a result, the crystalline silicon region 307a
Of the highly crystalline silicon region 3 is further improved.
08a. In addition, the amorphous silicon region 307
b is crystallized by irradiation with laser light and becomes a crystalline silicon region 308b. (Fig. 3 (C))

The crystalline silicon regions 308a and 308b are respectively etched to form island-shaped active regions 309a and 311.
09b is formed. Then, monosilane and dinitrogen monoxide are used as source gases by the plasma CVD method to obtain a thickness of 1
A 200 Å silicon oxide film is formed as a gate insulating film.
Further, an aluminum film (containing 0.2 to 0.5% by weight of scandium) having a thickness of 4000 Å is formed by a sputtering method and is patterned to form the gate electrode 310.
a and 310b are formed. Gate electrodes 310a, 31
0b is anodized to form a porous anodic oxide 311a, 31
1b, dense anodic oxide coatings 313a and 313b are sequentially formed. After that, the silicon oxide film under the gate electrodes 310a and 310b is etched to remove the gate insulating film 31.
2a and 312b are formed. (Fig. 3 (D))

Next, the porous anodic oxides 311a and 311 are used.
b is etched and doped to form high-concentration impurity regions 314a and 314b and low-concentration impurity regions 315.
a, 315b are formed. Offset gate area 3
00a and 300b are formed simultaneously. (Fig. 3
(E))

After that, the first interlayer insulator (silicon oxide film)
316, aluminum electrodes / wirings 317a, 317
b, 317c, second interlayer insulator (silicon nitride film) 31
8. A pixel electrode 319 made of ITO is formed. In this way, a monolithic active matrix circuit can be formed. (Fig. 3 (F))

[Embodiment 5] FIG. 4 shows a manufacturing process of this embodiment. This embodiment relates to a method for manufacturing a monolithic active matrix circuit, in which the left side represents a peripheral circuit and the right side represents a matrix circuit. In addition,
Although the peripheral circuit is formed into CMOS, only NMOS is shown in FIG. 4 for simplification.

On the glass substrate 401, a base silicon oxide film 402 having a thickness of 2000 Å and a thickness of 5 are formed by a plasma CVD method.
00Å amorphous silicon film 403, thickness 1000
A silicon oxide film 404 of Å is continuously formed. Then, the silicon oxide film 404 is etched to expose only the amorphous silicon film 403 in the peripheral logic circuit region. Furthermore, the substrate is exposed to ultraviolet light in an ozone atmosphere (the light source is a mercury lamp).
Is irradiated to form an extremely thin silicon oxide film (not shown) on the exposed surface of the amorphous silicon 403 film. Then, an extremely thin nickel acetate thin film 405 is formed by spin coating.
(Fig. 4 (A))

Next, in a nitrogen atmosphere, at 550 ° C.,
Perform thermal annealing for 4 hours. The nickel acetate thin film 405 decomposes into nickel at about 400 ° C., and diffuses into the amorphous silicon film 403 in the peripheral circuit region. As nickel diffuses, the amorphous silicon film 403 in the peripheral circuit region is laterally crystallized (horizontal growth) as shown by the arrow in the figure. Transformed into crystalline silicon.

On the other hand, the amorphous silicon film 403 in the matrix circuit region is not crystallized because nickel cannot diffuse because the silicon oxide film 404 exists. However, this thermal annealing causes hydrogen contained in the amorphous silicon film 403 to pass through the silicon oxide film 404 and be released to the outside to form an amorphous silicon region having a hydrogen content of 0.1% or less. (Fig. 4
(B))

After that, the silicon oxide film 404 is removed to expose the silicon film, and this is irradiated with KrF excimer laser light (wavelength 248 nm). As a result, the crystallinity of the crystalline silicon film in the peripheral logic circuit region is further improved to become crystalline silicon 406a. Further, the amorphous silicon film 403 in the matrix circuit region is crystallized to become crystalline silicon 406b. (Fig. 4 (B))

In this state, the crystalline silicon 406b in the matrix circuit region is not sufficient to obtain the semiconductor characteristics required in this embodiment, and the crystalline silicon 406b is irradiated with a laser beam having a higher energy density to further improve the crystallinity. It is necessary to improve. However, when such a laser beam irradiates the crystalline silicon 406a of the peripheral logic circuit,
Conversely, the crystallinity deteriorates.

Therefore, in this embodiment, as shown in FIG. 4C, a mask 407 is provided in the peripheral logic circuit area and only the crystalline silicon area 406b is irradiated with the laser beam. Silicon nitride that absorbs ultraviolet light is used for the mask 407. Energy density of laser light is 350-400 mJ / cm
² , for example, 380 mJ / cm ² . KrF excimer laser light (wavelength 248 nm) is used as the laser light. Under this condition, the energy density of the laser light is 350 mJ / cm ² in the portion covered with the mask 407.
The crystalline silicon 406a is not substantially affected because it is attenuated below. A crystalline silicon region 406c having higher crystallinity can be formed in the matrix circuit region through two laser irradiation steps. After the laser irradiation, thermal annealing may be performed in order to relax the stress strain. (Fig. 4 (C))

Then, the crystalline silicon regions 406a, 4
06c are respectively etched to form island-shaped active regions 40.
8a and 408b are formed. Then, a 1200 Å-thick silicon oxide film 409 is formed as a gate insulating film by a sputtering method. Further, the thickness is 40 by the sputtering method.
A 00Å aluminum film (containing 0.2-0.5 wt% scandium) was formed.

Only in the matrix circuit area, the gate electrode 41 is formed.
Porous anodic oxide 41 with a thickness of 4000Å on the side of 0b
1 is formed. At this time, no current is passed through the gate electrode / wiring 410a of the peripheral logic circuit. Further, dense anodic oxide coatings 412a and 412b are formed on the upper surfaces and side surfaces of the gate electrodes 410a and 410b to a thickness of 2000Å. (Fig. 4 (D))

Next, using the porous anodic oxide 411 and the dense anodic oxide coatings 412a and 412b as masks, a silicon oxide film 4 is formed by a dry etching method.
09 is etched to form gate insulating films 413a and 413.
b is formed. Now, only the porous anodic oxide 411 is etched using aluminum mixed acid.

Using the gate insulating films 413a and 413b as masks, impurities are toped to the active regions 408a and 408b by ion doping. When forming an NMOS transistor, phosphorus is doped. PM
When manufacturing an OS transistor, boron is doped. In this embodiment, the peripheral circuit is composed of CMOS, but FIG. 3 shows only the NMOS transistor.

As a result, the thin film transistors of the peripheral circuit and the matrix circuit, together with the high concentration impurity regions 414a and 414b doped with high concentration phosphorus, respectively,
Offset gate regions 400a and 400b are formed, respectively. Further, since the porous anodic oxide 411 is formed only in the matrix circuit region, the thin-film transistor of the matrix circuit has the low-concentration phosphorus-doped low-concentration impurity region region 412 formed therein, which has a double drain structure. Becomes Further, the width of the low concentration impurity region region 412 is equal to the thickness of the porous anodic oxide 411, and 4000
It is Å. (Fig. 4 (E))

Thereafter, the first interlayer insulator (thickness 4000
(Å silicon oxide film) 413 is deposited, and contact holes are formed in this, and titanium electrodes / wirings 417a and 417 are formed.
b, 417c and 417d are formed. Further, a second interlayer insulator (2000 Å thick silicon nitride film) 418 is deposited, a contact hole is formed in the drain electrode 417d of the TFT in the matrix region, and the pixel electrode 4 made of ITO is formed.
19 is formed. In this way, a monolithic active matrix circuit is formed. (Fig. 4 (F))

In the structure shown in this embodiment, since the thin film transistor arranged in the peripheral circuit region is not formed with the low concentration impurity region, the mobility is suppressed from being lowered, and the high speed operation is possible. On the other hand, since the low-concentration impurity regions are formed only in the thin film transistors arranged in the matrix region, the off current value can be reduced.

[Embodiment 6] FIG. 5 shows a manufacturing process of this embodiment. FIG. 5 is a manufacturing process diagram of one of the substrates constituting the active matrix type liquid crystal display device. The present embodiment relates to a method for manufacturing a monolithic active matrix circuit, in which the peripheral circuit is CMOS. In FIG. 5, for simplification, the peripheral circuit part is NM.
Only the OS is illustrated, the left side is a peripheral circuit, and the right side is a matrix circuit.

First, plasma CVD is performed on the glass substrate 501.
By the method, a base silicon oxide film 502 having a thickness of 2000Å and a silicon film 503 in an amorphous state having a thickness of 500Å are continuously formed. Then heat at 450 ° C for 1 hour,
Hydrogen in the amorphous silicon film 503 is released.

Thereafter, the silicon film 503 is irradiated with KrF excimer laser light (wavelength 248 nm). In this embodiment, laser irradiation is performed twice in order to improve the uniformity of crystallinity. In the first irradiation, the energy density of the laser is 200 to 250 mJ / cm ² , for example, 22
It is set to 0 mJ / cm ² . In the second laser irradiation, the energy density of the laser is made higher than that in the first time, and
50 to 400 mJ / cm ² , for example, 380 mJ / cm
^Set to ² . Silicon film 50 by laser irradiation twice
3 is entirely crystallized. (Figure 5 (A))

Then, a silicon nitride film 50 having a thickness of 3000 Å is formed.
4 is formed and etched to expose only the silicon film 503 in the peripheral logic circuit area. Furthermore, by irradiating ultraviolet light (light source is a mercury lamp) in an ozone atmosphere,
An extremely thin silicon oxide film is formed on the exposed surface of the silicon film 503. Then, an extremely thin nickel acetate thin film 505 is formed by spin coating.
(Fig. 5 (B))

In this state, silicon ions are implanted by the ion implantation method. Ion acceleration voltage is 10-30k
V and the dose amount are 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms / cm ² . As a result, in the peripheral logic circuit region not covered with the silicon nitride film 504, the silicon film 506a in an amorphous state is formed by the impact damage of the ions. On the other hand, since the silicon film 503 in the matrix circuit region is covered with the silicon nitride film 504, the crystallized state is maintained by the previous laser irradiation. (FIG. 5C) Note that the order of the step of FIG. 5B and the step of FIG. 5C may be interchanged.

Next, thermal annealing is performed in a nitrogen atmosphere at 550 ° C. for 4 hours to crystallize the amorphous silicon film 506a in the peripheral logic circuit region to obtain a crystalline silicon film 506b. Then, the crystalline silicon film 506b
The crystallinity is further improved by irradiating with laser light.
In this embodiment, laser irradiation is performed twice in order to improve the uniformity of crystallinity. At this time, since the silicon film 503 in the matrix circuit region is covered with the silicon nitride film 504, the crystallinity obtained by the previous laser irradiation is retained. (FIG. 5D) After that, the silicon nitride film 504 is removed. Through the above steps, crystalline silicon films required in the matrix circuit region and the peripheral logic circuit region can be obtained. Note that thermal annealing may be performed after the irradiation of the laser light in order to reduce stress distortion.

Then, the crystalline silicon film is etched to form island-shaped active regions. A 1200 Å thick silicon oxide film is formed as a gate insulating film by the sputtering method. Further, an aluminum film (containing 0.2 to 0.5% by weight of scandium) having a thickness of 4000 Å is formed by a sputtering method and patterned to form a gate electrode 5
07a and 507b are formed.

Gate electrode 5 of peripheral circuit and matrix circuit
A porous anodic oxide and a dense anodic oxide are sequentially formed on 07a and 507b. The thickness of the porous anodic oxide in the peripheral circuit area is 3000 Å, the thickness of the porous anodic oxide in the matrix circuit side area is 6000 Å, and the dense anodic oxide is in the peripheral circuit and matrix. Both circuits were set to 500Å.

Next, using the porous anodic oxide and the dense anodic oxide as a mask, the silicon oxide film under the gate electrodes 507a and 507b is etched to form the gate insulating film 508.
a and 508b are formed, and then the porous anodic oxide is peeled off. Further, as in the fifth embodiment, the active region is doped with impurity ions by the ion doping method. As a result, an N-channel thin film transistor having a double drain structure including the high-concentration N-type regions 509a and 509b and the low-concentration N-type regions 510a and 510b is obtained. Since the dense anodic oxide film is as thin as 500Å, the offset gate region is small. Therefore, its existence is not shown. The high concentration N-type regions 509a and 509b correspond to the source / drain regions. (Fig. 5 (E))

The low-concentration N-type region formed between the source or drain region and the channel forming region mainly lowers the electric field strength near the boundary between the channel forming region and the drain region and improves the off-current characteristic. Especially that effect. However, the low-concentration N-type region (low-concentration impurity region) is a high-resistance region, which lowers the mobility and thus the operating speed of the thin film transistor. Therefore, the thin film transistor of the peripheral circuit which is required to operate at high speed does not necessarily have to have the low concentration impurity region,
In particular, if it is necessary to reduce the off-current value, it may be provided so as not to impair the mobility characteristics.

In this embodiment, since the thickness of the porous anodic oxide in the peripheral circuit region was 3000 Å, the width of the low concentration N type region 510a was 3000 Å, and the porous anodic oxide in the matrix circuit side region was Since the thickness is 6000Å, the width of the low concentration N-type region 510b is 6000Å. That is, in a thin film transistor in a peripheral logic circuit region where high mobility is required and low off-current characteristics are not required so much, the width of a low concentration N-type region is narrowed, while high mobility is not required and low off-current characteristics are low. Since the width of the low-concentration impurity region of the required thin film transistor in the matrix circuit region is increased, it is possible to selectively form the thin film transistor having the characteristics required in the circuit region.

After that, the first interlayer insulator (thickness 4000
Å silicon oxide film) 511 is deposited, contact holes are formed in the film, and titanium electrodes / wirings 511a and 511 are formed.
b, 511c and 511d are formed. Further, a second interlayer insulator (a silicon nitride film having a thickness of 2000 Å) 513 is deposited, a contact hole is formed in the drain electrode 512d of the thin film transistor in the matrix region, and a pixel electrode 514 made of ITO is formed. In this way, a monolithic active matrix circuit is formed. (Fig. 5
(F))

[Embodiment 7] FIG. 6 shows a manufacturing process of this embodiment. FIG. 6 shows a manufacturing process of one of the substrates included in the active matrix liquid crystal display device. The present embodiment relates to a method for manufacturing a monolithic active matrix circuit, in which the peripheral circuit is CMOS. In FIG. 6, for simplicity, only the NMOS is shown in the peripheral circuit portion, and the left side is the peripheral circuit.
The matrix circuit is on the right.

First, a base silicon oxide film 622 having a thickness of 2000Å and a silicon film 623 in an amorphous state having a thickness of 500Å are successively formed on a glass substrate 621 by a plasma CVD method.

Then, a coating solution for forming a silicon oxide film containing nickel at a predetermined concentration in a solution of a silicon compound and additives in an organic solvent is applied to the surface of the silicon film 623 and further baked. Silicon oxide film 624
To form. For example, the coating liquid for forming a silicon oxide film is OCD (Ohka Diffusion Sourc) of Tokyo Ohka Kogyo Co., Ltd.
e) Use the Type2 Si59000, this solution with nickel (II) acetylacetonate - the door by mixing the solution obtained by dissolving in methyl acetate, SiO ₂ is 2.0 wt%, so the nickel is 200~2000ppm adjust. An appropriate amount of this solution is dropped on the surface of the amorphous silicon film 623, and spin coating is performed at 2000 rpm for 15 seconds using a spinner. And pre-bake at 250 ℃ 30
By performing this for a minute, a silicon oxide film 624 containing nickel is formed. The prebaking temperature may be determined in consideration of the decomposition temperature of the nickel compound. (Fig. 6
(A))

As the coating liquid for forming the silicon oxide film 624, fine powder of silicon oxide dispersed in an organic solvent may be used. When the above OCD is used as the solution and nickel is used as the catalyst, the following method can be adopted. (1) A method of directly adding a nickel compound to OCD. (2) A method in which a nickel compound is dissolved in a solvent to prepare a solution, and the solution is added to OCD.

When the above method (1) is adopted, the nickel compound must be one that is soluble in the OCD solvent. For example, nickel acetylacetone
And nickel 2-ethylhexanoate can be used as the nickel compound. When the method (2) is adopted, the solution of the nickel compound may be water, alcohol, ester, ketone or the like, and preferably the same solution as that used as the solvent of OCD is used. Is desirable.

In this case, nickel is introduced as a nickel compound. The nickel compound is typically nickel bromide, nickel acetate, nickel oxalate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate,
A material selected from nickel formate, nickel acetylacetonate, and nickel 4-cyclohexylbutyrate can be used by dissolving in alcohol.

It is also useful to add a surfactant to the solution containing the catalytic element. On the surface to be formed, an adhesive agent such as HMDS (Hexa-
By using (methyl-disilazane), the adhesion to the surface to be formed can be increased.

The above description is an example of using a solution in which nickel, which is a catalytic element, is completely dissolved. However, even if nickel is not completely dissolved, a powder of nickel alone or a nickel compound is dispersed in the dispersion medium. A material such as an emulsion uniformly dispersed in the above may be mixed with the OCD and used.

In this embodiment, the thickness of the silicon oxide film 624 is 400 Å (Sample I) and 3000 Å (Sample I).
Two samples of I) were formed. After that, the silicon oxide film 624 is etched to expose the silicon film 623 in the matrix circuit region. Next, in a nitrogen atmosphere,
Thermal annealing is performed at 50 ° C. for 4 hours. As a result, since the nickel contained in the silicon oxide film 624 diffuses into the amorphous silicon film 623 in the lower peripheral logic circuit area, the amorphous silicon film 623 is crystallized in the peripheral logic circuit area. , A crystalline silicon film 625a is obtained. On the other hand, the silicon oxide film 62
The amorphous silicon film 623 in the matrix circuit region not covered with No. 4 is not crystallized because nickel does not diffuse, but hydrogen is released and becomes amorphous silicon having a low hydrogen concentration.

Thereafter, with the silicon oxide film 624 attached, K
Irradiation with rF excimer laser light (wavelength 248 nm) is performed. In this embodiment, in order to improve the uniformity of crystallinity,
Laser irradiation is performed twice. Irradiation with laser light is 200 to 250 mJ / cm ² , for example, 22 during the first irradiation.
It is set to 0 mJ / cm ² . Also, during the second irradiation, 350
˜400 mJ / cm ² , for example 380 mJ / cm ² . As a result, the amorphous silicon in the matrix circuit region is crystallized to obtain the crystalline silicon film 625b. (Fig. 6 (B))

On the other hand, the crystalline silicon film 6 in the peripheral circuit region
In Sample I, 25a has a thickness of the silicon oxide film 624 of 40
Since it is extremely thin as 0 Å, the laser light is emitted from the silicon oxide film 62.
4 through which a considerable amount of energy (~ 2
00 mJ / cm ² , second irradiation ~ 340 mJ / cm
^{Since 2} ) has arrived, the crystallinity of the crystalline silicon film 625a can be further enhanced ,. Crystalline silicon film 625
get c. (Fig. 6 (C))

However, in the sample II, the silicon oxide film 6 was used.
Since the thickness of 24 is as thick as 3000 Å, the energy of the laser beam is absorbed by the silicon oxide film 624 in a considerable amount, and therefore the crystallinity of the crystalline silicon film 625a cannot be improved. Therefore, for sample II, after irradiating laser light to crystallize the amorphous silicon in the matrix circuit region, the silicon oxide film 624 is removed, and further laser light is radiated. The crystallinity of the crystalline silicon film 625a is improved. In this embodiment, laser light irradiation is performed with a laser energy density of 300 to 350 mJ / cm ² , for example, 340 mJ / cm ² . With such an energy density, the crystalline silicon film 625a in the matrix circuit region is hardly affected.
Thus, the crystalline silicon film 625c is obtained.

Through the above steps, the crystalline silicon film 6 required for the matrix circuit area and the peripheral logic circuit area is formed.
25b and 625c are obtained. After laser irradiation,
Thermal annealing may be performed to relieve the stress strain.

After that, the crystalline silicon films 625b and 625b are formed.
5c is etched to form an island-shaped active region. (FIG. 6D) After that, the crystalline silicon film is etched to form island-shaped active regions. Thickness of 1200Å by sputtering method
Is formed as a gate insulating film. further,
A 4000 Å thick aluminum film (containing 0.2 to 0.5% by weight of scandium) is formed by a sputtering method and patterned to form gate electrodes 626a, 6
26b is formed.

Gate electrodes 6 of peripheral circuit and matrix circuit
A porous anodic oxide and a dense anodic oxide are sequentially formed on 26a and 626b. The thickness of the porous anodic oxide in the peripheral circuit area is 3000 Å, the thickness of the porous anodic oxide in the matrix circuit side area is 6000 Å, and the thickness of the dense anodic oxide is the peripheral circuit and the matrix. Both circuits were set to 300Å.

Next, using the porous anodic oxide and the dense anodic oxide as a mask, the silicon oxide film under the gate electrodes 626a and 626b is etched to form a gate insulating film 627.
a and 627b are formed, and then the porous anodic oxide is peeled off.

Further, as in the fifth embodiment, the active region is doped with impurity ions by the ion doping method.
As a result, an N-channel thin film transistor having a double drain structure including the high-concentration N-type regions 628a and 628b and the low-concentration N-type regions 629a and 629b is obtained. The high concentration N-type regions 628a and 628b correspond to the source / drain regions. The thickness of the dense anodic oxide coating is 300
As thin as Å, the offset gate area is small. Therefore, its existence is not shown. (Figure 6 (D))

Then, the first interlayer insulator (thickness 4000
Å silicon oxide film) 630 is deposited, contact holes are formed in this, and titanium electrodes / wirings 631a and 631 are formed.
b, 631c, 631d are formed. Further, a second interlayer insulator (a silicon nitride film having a thickness of 2000 Å) 632 is deposited, a contact hole is formed in the drain electrode 631d of the TFT in the matrix region, and the ITO pixel electrode 6 is formed.
33 is formed. In this way, a monolithic active matrix circuit can be formed. (Fig. 6
(E))

In this example, since the thickness of the porous anodic oxide in the peripheral circuit region was 3000 Å, the width of the low concentration N-type region 510a was 3000 Å, and the porous anodic oxide in the matrix circuit side region was Since the thickness is 6000Å, the width of the low concentration N-type region 510b is 6000Å. That is, the width of the low concentration N-type region is narrowed in the thin film transistor in the peripheral logic circuit region, which requires high mobility and does not require low off-current characteristics. On the other hand, in the thin film transistor in the matrix circuit area where high mobility is not required and low off current characteristics are required, the width of the low concentration impurity area is made large, so that a thin film transistor having characteristics required in the circuit area is selected. Can be formed as desired.

[0149]

In the semiconductor circuit according to the present invention, the active element in the peripheral circuit area contains a catalytic element that promotes crystallization of silicon, and the matrix circuit area does not contain this catalytic element. Since active regions having crystallinity different from each other are formed in a predetermined region, a thin film transistor is manufactured using such active regions, so that a peripheral circuit has high on-current characteristics on the same substrate. A thin film transistor can be formed, and a thin film transistor having low off-state current characteristics can be formed in the matrix circuit. When this is applied to a liquid crystal display, mass productivity and characteristics can be improved.

In the method for manufacturing a thin film semiconductor of the present invention, a thin film transistor having a high on-current characteristic suitable for a peripheral circuit and a thin film transistor having a low off current characteristic suitable for a matrix circuit are formed by the same process. Therefore, the process is not complicated and the productivity is not reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a conventional monolithic active matrix circuit.

FIG. 2 is a cross-sectional view of a substrate for each manufacturing process of Examples 1 and 2.

FIG. 3 is a cross-sectional view of a substrate for each manufacturing process of Examples 3 and 4.

4A to 4C are cross-sectional views of the substrate in each manufacturing process of Example 5.

5A to 5C are cross-sectional views of the substrate in each manufacturing process of Example 6.

6A to 6C are cross-sectional views of the substrate in each manufacturing process of Example 7.

[Explanation of symbols]

201 glass substrates 202, 204, 208, 216 silicon oxide film 203 amorphous silicon film 205 nickel acetate thin film 206a crystalline silicon region 206b amorphous silicon regions 209a, 209b photoresist masks 210a, 210b gate electrodes 211a, 211b porous anodic oxide 212a, 212b Dense anodic oxides 213a, 213b Gate insulating films 214a, 214b Regions 215a, 215b heavily doped with phosphorus ions Regions 216, 217 lightly doped with phosphorus ions Offset gate regions 218 Silicon oxide film 219a to 219c Aluminum electrode / wiring 220 Silicon nitride film 221 Pixel electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 627G (72) Inventor Hisashi Otani 398 Hase, Atsugi-shi, Kanagawa Prefecture Semiconductor Energy Laboratory Co., Ltd. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi, Kanagawa Prefecture, Semiconductor Energy Laboratory Co., Ltd. (56) Reference JP-A-6-267988 (JP, A) JP-A-8-6053 (JP, A) JP-A-6-104432 (JP, A) ) JP-A-5-173179 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/336 G02F 1/1368

Claims (18)

(57) [Claims] 1. A semiconductor circuit having a peripheral circuit and a matrix circuit, wherein each of the peripheral circuit and the matrix circuit has a thin film transistor, wherein the thin film transistor of the peripheral circuit is crystallized.
Amorphous silicon in the active region consisting of a silicon film
The concentration of the catalytic element for promoting crystallization, 1 × 10 ¹⁵ ~1
× 10 ¹⁹ atoms / cm ³ and the thin film transistor of the matrix circuit was crystallized.
Amorphous state in the active region consisting of silicon film
The concentration of the catalytic element that promotes crystallization of the recon is 1 × 10
^{The number of} atoms is less than ¹⁵ atoms / cm ³ , and the thin film transistor of the matrix circuit has a low-concentration impurity region formed between a source region, a drain region, and a channel formation region. 2. The amount of the catalyst element contained in the active region of the thin film transistor of the peripheral circuit per unit area in the active region of the thin film transistor of the matrix circuit according to claim 1. A semiconductor circuit characterized in that the amount of the catalyst element contained is 10 times or more the amount per unit area. 3. The semiconductor circuit according to claim 1 , wherein the field effect mobility of the thin film transistor of the peripheral circuit is higher than the field effect mobility of the thin film transistor of the matrix circuit. 4. A any one of claims 1 to 3, as the catalyst element, Fe, Co, Ni, Rh , Pd, O
A semiconductor circuit comprising one or more elements selected from s, Ir, Pt, Cu or Au. 5. A any one of claims 1 to 4, the concentration of the catalyst element, a semiconductor circuit, characterized in that it is defined by a minimum value of values measured by secondary ion mass spectrometry. 6. A any one of claims 1 to 5, the thin film transistor of said matrix circuit, a semiconductor, characterized in that an offset region formed between the channel formation region and the low concentration impurity regions circuit. 7. The method according to any one of claims 1 to 6, wherein
Note that semiconductor circuits are used in liquid crystal displays.
Characteristic semiconductor circuit. 8. A method of manufacturing a semiconductor circuit, comprising a peripheral circuit region and a matrix circuit region each including a thin film transistor, wherein the thin film transistor in the matrix circuit region has a low-concentration impurity region, wherein the peripheral circuit region and the matrix circuit region. Forming a silicon film in an amorphous state on each of the peripheral circuits, and introducing a catalyst element for promoting crystallization of amorphous silicon into the amorphous silicon film in the peripheral circuit region, wherein a region and the matrix circuit region
Heating the silicon film Amorphous state, the silicon film of the amorphous state of the peripheral circuit region crystallized silicon of the amorphous silicon film above was crystallized in the peripheral circuit region and the matrix circuit region
A method for manufacturing a semiconductor circuit, which comprises irradiating a semiconductor film with laser light . 9. A method of manufacturing a semiconductor circuit, comprising a peripheral circuit region and a matrix circuit region each including a thin film transistor, wherein the thin film transistor in the matrix circuit region has a low concentration impurity region, wherein the peripheral circuit region and the matrix circuit region. Forming a silicon film in an amorphous state on each of them, and forming a film having a catalytic element that adheres to the silicon film in an amorphous state in the peripheral circuit region and promotes crystallization of silicon in an amorphous state , wherein a peripheral circuit region and the matrix circuit region
Heating the silicon film Amorphous state, the silicon film of the amorphous state of the peripheral circuit region crystallized silicon of the amorphous silicon film above was crystallized in the peripheral circuit region and the matrix circuit region
A method for manufacturing a semiconductor circuit, which comprises irradiating a semiconductor film with laser light . 10. A method for manufacturing a semiconductor circuit, comprising: a peripheral circuit region including a thin film transistor and a matrix circuit region respectively; and the thin film transistor in the matrix circuit region having a low concentration impurity region, wherein the peripheral circuit region and the matrix circuit region. Amorphous silicon film is formed on each of the above, and the amorphous silicon film in the peripheral circuit region is formed.
A silicon oxide film is formed on the silicon oxide film , and an amorphous film is formed on the silicon oxide film in the peripheral circuit region.
Solution containing a catalytic element that promotes crystallization of crystalline silicon
Was applied, the A of the peripheral circuit region and the matrix circuit region
Heating the silicon film Amorphous state, the silicon film of the amorphous state of the peripheral circuit region crystallized silicon of the amorphous silicon film above was crystallized in the peripheral circuit region and the matrix circuit region
A method for manufacturing a semiconductor circuit, which comprises irradiating a semiconductor film with laser light . 11. A method of manufacturing a semiconductor circuit, comprising a peripheral circuit region and a matrix circuit region each including a thin film transistor, wherein the thin film transistor in the matrix circuit region has a low-concentration impurity region, wherein the peripheral circuit region and the matrix circuit region. Forming a silicon film in an amorphous state on each of the peripheral circuits, and introducing a catalyst element for promoting crystallization of amorphous silicon into the amorphous silicon film in the peripheral circuit region, wherein a region and the matrix circuit region
Irradiating a laser beam to the silicon film Amorphous state, the Amo of the peripheral circuit region and the matrix circuit region
The silicon film in the rufus state is crystallized to connect the peripheral circuit region and the matrix circuit region with each other.
A method for manufacturing a semiconductor circuit, which comprises heating a crystallized silicon film . 12. A method of manufacturing a semiconductor circuit, comprising a peripheral circuit region and a matrix circuit region each including a thin film transistor, wherein the thin film transistor in the matrix circuit region has a low-concentration impurity region, wherein the peripheral circuit region and the matrix circuit region. Forming a silicon film in an amorphous state on each of them, and forming a film having a catalytic element that adheres to the silicon film in an amorphous state in the peripheral circuit region and promotes crystallization of silicon in an amorphous state , wherein a peripheral circuit region and the matrix circuit region
Irradiating a laser beam to the silicon film Amorphous state, the Amo of the peripheral circuit region and the matrix circuit region
The silicon film in the rufus state is crystallized to connect the peripheral circuit region and the matrix circuit region with each other.
A method for manufacturing a semiconductor circuit, which comprises heating a crystallized silicon film . 13. A method of manufacturing a semiconductor circuit, comprising a peripheral circuit region and a matrix circuit region each including a thin film transistor, wherein the thin film transistor in the matrix circuit region has a low-concentration impurity region, the peripheral circuit region and the matrix circuit region. Amorphous silicon film is formed on each of the above, and the amorphous silicon film in the peripheral circuit region is formed.
A silicon oxide film is formed on the silicon oxide film , and an amorphous film is formed on the silicon oxide film in the peripheral circuit region.
Solution containing a catalytic element that promotes crystallization of crystalline silicon
Was applied, the A of the peripheral circuit region and the matrix circuit region
Irradiating a laser beam to the silicon film Amorphous state, the Amo of the peripheral circuit region and the matrix circuit region
The silicon film in the rufus state is crystallized to connect the peripheral circuit region and the matrix circuit region with each other.
A method for manufacturing a semiconductor circuit, which comprises heating a crystallized silicon film . 14. The method according to claim 10 or 13 ,
A method of manufacturing a semiconductor circuit, wherein the catalyst element is applied by a spin coating method. 15. The odor according to any one of claims 8 to 10.
The crystallized silicon film in the peripheral circuit area and
And the amorphous state of the matrix circuit area.
After irradiating the laser beam on the recon film, it is special to heat it.
A method for manufacturing a semiconductor circuit as a characteristic. 16. In any one of claims 8 to 15, as the catalyst element, Fe, Co, Ni, Rh, P
A method of manufacturing a semiconductor circuit, wherein one or more kinds of elements selected from d, Os, Ir, Pt, Cu or Au are used. 17. any one of claims 8 to 16, a method for manufacturing a semiconductor circuit, wherein the temperature for heating is four hundred and fifty to five hundred eighty ° C.. 18. The odor according to any one of claims 8 to 17.
In the crystallized silicon film in the peripheral circuit region
The concentration of the catalytic element is 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms
/ Cm ³ is a method of manufacturing a semiconductor circuit characterized by
Law.