JP2873669B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a semiconductor having crystallinity and a method for manufacturing the same.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs) using thin film semiconductors are known. This TFT is
A thin film semiconductor (active layer) is formed on a substrate, and is configured using the thin film semiconductor. This TFT is used for various integrated circuits, and is particularly used for a switching element provided in each pixel of an electro-optical device, particularly an active matrix type liquid crystal display device, and a driver element formed in a peripheral circuit portion. I have.

[0003] As a thin film semiconductor used for a TFT,
Although it is convenient to use an amorphous silicon film, there is a problem that its electrical characteristics are low. In order to obtain an improvement in TFT characteristics, a silicon thin film having crystallinity may be used.
The silicon film having crystallinity is called polycrystalline silicon (polysilicon), microcrystalline silicon (microcrystalline silicon), or the like. In order to obtain a silicon film having this crystallinity, an amorphous silicon film may be formed first, and then crystallized by heating.

[0004] However, the crystalline silicon thin film obtained by heating has a relatively small particle size and is not uniform in size, which causes variations in characteristics. In addition, the mobility (mobility), which is a measure of the capability at the time of forming an element, is significantly inferior to that of single crystal silicon, and improvement in these characteristics is required.

Background of the Invention According to the study of the present inventors, trace amounts of elements such as nickel, palladium, and lead are deposited on the surface of an amorphous silicon film, and then heated to obtain 450 nm. It has been found that crystallization can be performed at a temperature of about 550 ° C. to about 550 ° C. for a processing time of about 4 hours. The obtained crystal grains can also be controlled by the crystallization temperature and time, which means that an active layer required for the device can be produced.

[0006] In order to introduce the above trace elements (catalytic elements that promote crystallization), plasma treatment, vapor deposition, and ion implantation may be used. Plasma treatment refers to the use of a material containing a catalyst element as an electrode in a parallel plate type or positive column type plasma CVD apparatus, and generation of plasma in an atmosphere such as nitrogen or hydrogen to form a catalyst element on an amorphous silicon film. This is a method of adding. However, the presence of a large amount of such elements in a semiconductor impairs the reliability and electrical stability of a device using such a semiconductor, and is not preferable.

In other words, the above-mentioned elements that promote crystallization such as nickel (the elements that promote crystallization are referred to as catalyst elements in the present specification) are necessary when crystallizing amorphous silicon. It is desirable that the crystallized silicon is not contained as much as possible. In order to achieve this purpose, at the same time as selecting a catalyst element that has a strong tendency to be inactive in crystalline silicon, the amount of the catalyst element required for crystallization is minimized,
Crystallization must be performed in a minimum amount. For that purpose, it is necessary to precisely control the amount of the catalyst element to be introduced.

The inventor of the present invention has formed an amorphous silicon film using nickel as a catalyst element, added nickel by a plasma treatment method, and further produced a crystalline silicon film by a heat treatment. Detailed examination of the conversion process and the like revealed the following. (1) When nickel is introduced onto an amorphous silicon film by plasma treatment, nickel has already penetrated to a considerable depth in the amorphous silicon film before the heat treatment is performed. (2) The initial nucleation of the crystal occurs from the surface into which nickel is introduced. (3) Even when nickel is formed on an amorphous silicon film by a vapor deposition method, crystallization occurs as in the case where plasma processing is performed.

From the above, it is concluded that all nickel introduced by the plasma treatment is not functioning effectively. That is, it is considered that some nickel does not function sufficiently even if a large amount of nickel is introduced. From this, it is considered that the point (plane) where nickel and silicon are in contact functions at the time of low-temperature crystallization.
Then, it is concluded that it is necessary that nickel be dispersed as finely as possible in an atomic state. In other words, it is concluded that "what is necessary is to introduce as low a concentration of nickel as possible in the form of atoms in the vicinity of the surface of the amorphous silicon film in a range where low-temperature crystallization is possible".

A method for introducing a trace amount of nickel only near the surface of the amorphous silicon film, in other words, a method for introducing a trace amount of a catalytic element for promoting crystallization only near the surface of the amorphous silicon film. Can be a vapor deposition method.
However, the vapor deposition method has a problem that the controllability is poor and it is difficult to strictly control the introduction amount of the catalyst element. Further, it is necessary that the amount of the catalyst element introduced be as small as possible, but in this case, there is a problem that crystallinity is insufficient.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a method of producing a crystalline silicon thin film having a crystallinity by heat treatment using a catalytic element. And the amount of (2) Use a method with high productivity. (3) Higher crystallinity than that obtained by heat treatment is obtained. It is intended to satisfy such requirements.

[0012]

According to the present invention, a silicon film having crystallinity is obtained by using the following means in order to satisfy the above object. That is, the present invention holds a catalyst element alone or a compound containing the catalyst element in contact with the amorphous silicon film to promote crystallization of the amorphous silicon film, and the amorphous silicon film contains the catalyst element alone or 450 ° C. to 650 ° C. in a state where the compound containing the catalytic element is in contact with
For example, heat treatment is performed at a relatively low temperature of about 550 ° C. to crystallize a part or all of the amorphous silicon film. Further, the crystallization is further promoted by annealing at a temperature higher than the crystallization temperature, for example, about 1000 ° C. when the substrate is quartz. Thus, a crystalline silicon film having extremely good crystallinity is obtained.

As a method for introducing a catalytic element for promoting crystallization, a method in which a solution containing the catalytic element is applied to the surface of the amorphous silicon film is useful. Particularly, the present invention is characterized in that the catalytic element is introduced in contact with the surface of the amorphous silicon film. This is extremely important in controlling the amount of the catalytic element. The catalyst element is introduced
The upper surface or the lower surface of the amorphous silicon film may be used. If the catalytic element is introduced on the upper surface of the amorphous silicon film, a solution containing the catalytic element may be applied onto the amorphous silicon film after the amorphous silicon film is formed. If the catalyst element is introduced into the lower surface of the silicon film, a solution containing the catalyst element is applied to the base surface before forming the amorphous silicon film, and the catalyst element is held in contact with the base surface. I just need.

Further, the present invention is characterized in that an active region having at least one PN, PI, NI or other electrical junction of a semiconductor device is formed using a crystallized crystalline silicon film. Examples of the semiconductor device include a thin film transistor (TFT), a diode, and an optical sensor.

By employing the configuration of the present invention, the following basic significance can be obtained. (A) The concentration of the catalyst element in the solution can be strictly controlled in advance to further increase the crystallinity and reduce the amount of the element. (B) If the solution is in contact with the surface of the amorphous silicon film,
The amount of the catalyst element introduced into the amorphous silicon is determined by the concentration of the catalyst element in the solution. (C) Since the catalytic element adsorbed on the surface of the amorphous silicon film mainly contributes to the crystallization, the catalytic element can be introduced at a minimum necessary concentration. (D) A crystalline silicon film having good crystallinity can be obtained without requiring a high-temperature process.

In the method of applying a solution containing an element promoting crystallization on the amorphous silicon film, an aqueous solution, an organic solvent solution, or the like can be used as the solution. Here, “containing” includes both the meaning of being included as a compound and the meaning of being included simply by being dispersed.
As the solvent containing the catalytic element, a solvent selected from polar solvents such as water, alcohol, acid, and ammonia can be used.

When nickel is used as a catalyst and this nickel is contained in a polar solvent, nickel is introduced as a nickel compound. Typical examples of the nickel compound include nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, nickel formate, nickel acetylacetonate, and 4-cyclohexylbutyric acid. A material selected from nickel, nickel oxide, and nickel hydroxide is used.

As the solvent containing the catalyst element, a non-polar solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform and ether can be used. In this case, nickel is introduced as a nickel compound. As the nickel compound, typically, a compound selected from nickel acetylacetonate and nickel 2-ethylhexanoate can be used.

It is also useful to add a surfactant to the solution containing the catalytic element. This is to increase the adhesion to the surface to be coated and control the adsorption. This surfactant may be applied in advance on the surface to be coated. When using nickel alone as a catalyst element, it is necessary to dissolve it in an acid to make a solution.

The above is an example in which a solution in which nickel as a catalytic element is completely dissolved is used. Even if nickel is not completely dissolved, a powder composed of nickel alone or a nickel compound is dispersed in a dispersion medium. A material such as an emulsion which is uniformly dispersed in the emulsion may be used. Alternatively, a solution for forming an oxide film may be used. As such a solution, OCD (Ohka Diffusion) of Tokyo Ohka Kogyo Co., Ltd.
Source) can be used. With the use of this OCD solution, a silicon oxide film can be easily formed by applying it on the surface to be formed and baking it at about 200 ° C. Further, since it is easy to add impurities, it can be used in the present invention. The same applies to the case where a material other than nickel is used as the catalyst element.

When nickel is used as a catalyst element for promoting crystallization and a polar solvent such as water is used as a solution solvent for containing the nickel, when these solutions are directly applied to the amorphous silicon film, the solution becomes elastic. It may be lost. In this case, a thin oxide film having a thickness of 100 ° or less is formed, and a solution containing a catalytic element is applied thereon, whereby the solution can be applied uniformly. It is also effective to improve the wetting by adding a material such as a surfactant to the solution.

Further, by using a non-polar solvent such as a toluene solution of nickel 2-ethylhexanoate as a solution, it is possible to apply directly to the surface of the amorphous silicon film. In this case, it is effective to apply a material such as an adhesive used in applying the resist in advance. However, care must be taken when the amount of coating is too large, since this would hinder the addition of the catalytic element to the amorphous silicon.

The amount of the catalyst element contained in the solution depends on the type of the solution, but as a general tendency, the amount of nickel is 200 ppm to 1 ppm, preferably 50 ppm to 1 ppm (in terms of weight) based on the solution. It is desirable. This is a value determined in view of the nickel concentration in the film after crystallization and the resistance to hydrofluoric acid.

The heating temperature during crystallization is 450 ° C. to 6 ° C.
It is important that the temperature be 50 ° C. In the present invention, it is premised that a crystalline silicon thin film having a uniform grain size and high crystallinity is obtained by performing crystallization only from a portion in contact with the catalytic element and the amorphous silicon thin film as described above. It is not desirable that nucleation or crystallization progresses from other portions because it leads directly to variation in characteristics. According to the experiments by the inventors, the above 450 ° C. to 6 ° C.
It has been found that if the temperature is short in the range of 50 ° C., crystallization of the portion not in contact with the catalyst element can be ignored, and the configuration of the present invention can be obtained. If the temperature is lower than the above temperature range, sufficient crystal growth cannot be performed even if a catalyst element is added. Similarly, if the temperature is higher than the above temperature range, crystal growth will occur regardless of the catalyst.

Similarly, annealing at a higher temperature is performed after the crystallization treatment, whereby the characteristics of the interface between the crystal grains can be further improved, and the crystallinity of the silicon film can be further improved.
Without this step, the barriers at the grain boundaries are high, and typically adverse effects such as an increase in mobility occur.
Regarding reliability, it is difficult to form a stable device due to the influence of a catalytic element bonded to a small amount of an amorphous component present at a grain boundary.

Further, by further progressing this constitution of the present invention, it is possible to extremely reduce the amount of the catalytic element, to terminate the crystallization by the first heating immediately after the nucleation, and then to carry out the crystal growth by high-temperature annealing. . In this case, it is possible to perform the nucleation process and the crystal growth process separately and at a temperature suitable for each process.

High-temperature annealing for improving crystallinity is annealing in a general electric furnace (thermal annealing).
Alternatively, a method of irradiating strong light, particularly infrared light, may be employed. Since infrared light is hardly absorbed by glass and easily absorbed by a silicon thin film, the silicon thin film formed on the glass substrate can be selectively heated. An annealing method using infrared light is rapid thermal annealing (RTA).
Or it is called a rapid thermal process (RTP).

Further, by selectively applying a solution containing a catalyst element, crystal growth can be selectively performed. In particular, in this case, toward the region where the solution has not been applied, the crystal can be grown from the region where the solution has been applied in a direction substantially parallel to the surface of the silicon film. In this specification, a region where crystal growth is performed in a direction substantially parallel to the surface of the silicon film is referred to as a region where crystal growth is performed in a lateral direction.

It has been confirmed that the region where the crystal has grown in the lateral direction has a low concentration of the catalytic element. It is advantageous to use a crystalline silicon film as the active layer region of the semiconductor device. In particular, the impurity concentration in the active layer region is generally preferably low. Therefore, forming the active layer region of the semiconductor device using the region where the crystal is grown in the lateral direction is extremely advantageous in device fabrication.

In the present invention, the most remarkable effect can be obtained when nickel is used as a catalyst element. However, other usable types of catalyst elements are preferably Pt, Cu, Ag, Au, In, and In. , Sn, Pd,
P, As, and Sb are mentioned. Group VIII element, III
One or more elements selected from b, IVb, and Vb elements can also be used.

The method of introducing the catalytic element is not limited to the use of an aqueous solution or a solution such as alcohol, but a wide range of substances containing the catalytic element can be used.
For example, a metal compound or oxide containing a catalyst element can be used.

[0032]

【Example】

[Embodiment 1] In this embodiment, a catalyst element that promotes crystallization is contained in an aqueous solution, applied onto an amorphous silicon film, then crystallized by heating, and then crystallized by high-temperature thermal annealing. This is an example that enhances the performance. With reference to FIG. 1, the process up to the point where a catalytic element (here, nickel is used) is introduced will be described. In this embodiment, quartz glass is used as the substrate 11. The size is 100mm x 1
00 mm.

First, an amorphous silicon film is formed by plasma CVD or LPCVD to form an amorphous silicon film of 100 to 15 nm.
00 ° is formed. Here, the amorphous silicon film 12 is formed to a thickness of 1000 ° by a plasma CVD method. (FIG. 1 (A)) Then, a hydrofluoric acid treatment is performed to remove dirt and a natural oxide film, and then an oxide film 13 is formed to a thickness of 10 to 50 °. If the contamination can be ignored, a natural oxide film may be used as it is instead of the oxide film 13.

The exact thickness of the oxide film 13 is unknown because it is extremely thin, but it is estimated to be about 20 °.
In this embodiment, the oxide film 13 is formed by irradiation with UV light in an oxygen atmosphere. The film was formed by irradiating UV in an oxygen atmosphere for 5 minutes. As a method for forming the oxide film 13, a thermal oxidation method may be used. Further, a treatment by hydrogen peroxide may be used.

The oxide film 13 is to spread the acetate solution over the entire surface of the amorphous silicon film in the subsequent step of applying an acetate solution containing nickel. That is,
This is for improving the wettability. When an acetate solution is directly applied to the surface of a normal amorphous silicon film, nickel cannot be introduced to the entire surface of the amorphous silicon film because the amorphous silicon repels the acetate solution. . That is, uniform crystallization cannot be performed.

Next, an acetate solution is prepared by adding nickel to the acetate solution. The concentration of nickel is 25 ppm. Then, 2 ml of this acetate solution is dropped on the surface of the oxide film 13 on the amorphous silicon film 12 to form an acetate solution water film 14, and this state is maintained for 5 minutes. And spinner 15
And spin dry (2000 rpm, 60 seconds). (Fig. 1 (C), (D))

The concentration of nickel in the acetic acid solution is 1
If it is at least 10 ppm, preferably at least 10 ppm, it will be practical. When a nonpolar solvent such as a toluene solution of nickel 2-ethylhexanoate is used as the solution, the oxide film 13 is unnecessary, and the catalyst element can be directly introduced onto the amorphous silicon film.

By performing this step of applying the nickel solution once to a plurality of times, a layer containing nickel having an average film thickness of several to several hundreds of mm is formed on the surface of the amorphous silicon film 12 after spin drying. Can be formed. In this case, nickel in this layer diffuses into the amorphous silicon film in the subsequent heating step and acts as a catalyst for promoting crystallization. Note that this layer is not necessarily a complete film.

After the application of the solution, the state is maintained for one minute. Although the concentration of nickel contained in the silicon film 12 can be finally controlled by the holding time, the largest controlling factor is the concentration of the solution. Then, in a heating furnace, 550 in a nitrogen atmosphere.
Heat treatment at 4 ° C. for 4 hours. As a result, the substrate 11
The silicon thin film 12 having crystallinity formed thereon can be obtained.

The above-mentioned heat treatment can be performed at a temperature of 450 ° C. or higher. However, if the temperature is low, the heating time must be prolonged, and the production efficiency decreases. Further, if the temperature is too high, crystal growth starts from a portion other than the portion in contact with nickel, and as a result, a crystalline silicon film composed of large-sized silicon particles cannot be produced. In this embodiment, the method of introducing a catalytic element on the amorphous silicon film is described, but a method of introducing a catalytic element below the amorphous silicon film may be adopted. In this case, the catalyst element may be introduced onto the base film using a solution containing the catalyst element before the formation of the amorphous silicon film.

Silicon film 12 having crystallinity by heat treatment
After that, a hydrofluoric acid treatment is performed to remove dirt and a natural oxide film. And at 1000 ° C. for 30 minutes to 2 hours,
Here, annealing for 100 minutes is performed in nitrogen to increase the crystallinity inside the crystal grains (an effect of reducing defects inside the crystal can be expected by performing this step) and improve the characteristics of the interface. This process may be performed in oxygen to improve the crystallinity and form a thermal oxide film of about 1000 °. After that, the oxide film was removed, and as a result of observation by TEM, the obtained crystalline silicon film exhibited a polycrystalline state composed of large-diameter crystal grains having anisotropy .
It was found that the long sides of the crystal grains were longer than 10 μm, and their sizes were relatively uniform.

[Embodiment 2] In this embodiment, in the manufacturing method shown in Embodiment 1, a silicon oxide film of 1200 ° is selectively provided, and nickel is selectively introduced using this silicon oxide film as a mask. . FIG. 2 shows an outline of a manufacturing process in this embodiment. First, a quartz glass substrate (10 cm square) 1
1 on which an amorphous silicon film is formed by plasma CVD or LPCV.
A film is formed to a thickness of 1000 ° by D (low pressure thermal CVD).
Next, the silicon oxide film 21 serving as a mask is
Here, the film is formed to have a thickness of 1200 °. According to experiments performed by the inventors, the thickness of the silicon oxide film 21 is 500
However, it has been confirmed that there is no problem, and if the film quality is dense, the film may be thinner.

Then, by the usual photolithography process,
The silicon oxide film 21 is etched into a required pattern. Then, a thin silicon oxide film 20 is formed by ultraviolet irradiation in an oxygen atmosphere. The production of the silicon oxide film 20 is as follows.
This is performed by irradiating UV light for 5 minutes in an oxygen atmosphere. The thickness of the silicon oxide film 20 is 20 to 50.
It is considered to be about Å (FIG. 2 (A)). The silicon oxide film 20 is for improving the wettability, but when the size of the solution matches the size of the pattern, the silicon oxide film 20 may be added just depending on only the hydrophilicity of the silicon oxide film of the mask. However, such a case is special, and it is generally safer to use the silicon oxide film 20.

In this state, as in the first embodiment, 10
5 ml of an acetate solution containing 0 ppm of nickel is dropped (in the case of a 10 cm square substrate). At this time, spin coating is performed at 50 rpm for 10 seconds using the spinner 15 to form a uniform water film 14 on the entire substrate surface.
Further, in this state, after holding for 5 minutes, the spinner 15
And spin dry at 2,000 rpm for 60 seconds. In addition, this holding | maintenance is 0-15 on a spinner.
It may be performed while rotating at 0 rpm. (Figure 2
(B))

Then, the amorphous silicon film 12 is crystallized by performing a heat treatment at 550 ° C. (nitrogen atmosphere) for 4 hours. At this time, the nickel-introduced portion 22
As shown at 23 from the region, crystal growth is performed in the lateral direction to the region 25 into which nickel has not been introduced.
In FIG. 2C, reference numeral 24 denotes a region where nickel is directly introduced and crystallization is performed, and reference numeral 25 denotes a region where crystallization is performed in a lateral direction. In the region of 25, it has been confirmed that crystal growth is performed substantially in the <111> axis direction.

When TEM observation is performed at this stage, columnar crystals of uniform width are grown radially from the nickel-added region to the periphery of the obtained crystalline silicon film. It was found that an amorphous portion remained in the gap. Next, after the crystallization step by the heat treatment, the silicon oxide film is removed, and the heating temperature is set to 1000 in nitrogen.
Anneal at ℃ to further improve the crystallinity of the silicon film 12. By this step, the region 25 where the crystal is grown in the lateral direction is formed.
Can greatly improve the crystallinity.

When the crystalline silicon film was observed with a TEM, it was found that the above-mentioned gaps between the columnar crystals were crystallized, and that pseudo-epitaxial growth with the columnar crystals as nuclei occurred. Further, as a result, the crystal grain boundaries become very incomprehensible, and as if they were huge crystal grains (up to several tens μm).
As described above), a polycrystalline silicon film was obtained.

In this embodiment, the concentration of nickel in the region where nickel is directly introduced is changed from 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ⁵ by changing the solution concentration and the holding time.
^It can be controlled within the range of ¹⁹ cm ^-3 , and similarly, the concentration of the lateral growth region can be controlled to be lower than that. The nickel concentration in this film has a U-shaped distribution in the film thickness direction, and the above-mentioned concentration indicates the bottom portion (minimum value) of this U-shaped distribution.

The crystalline silicon film formed by the method shown in this embodiment is characterized by having good hydrofluoric acid resistance. According to the findings of the present inventors, a crystalline silicon film obtained by introducing nickel by plasma treatment and crystallizing
Low hydrofluoric acid resistance. For example, in the manufacture of a TFT, the work of forming a silicon oxide film functioning as a gate insulating film or an interlayer insulating film on a crystalline silicon film and forming a hole through the hole forming process for forming the electrode is performed. Needed.
In such a case, a step of removing the silicon oxide film with buffered hydrofluoric acid is usually adopted. However, when the hydrofluoric acid resistance of the crystalline silicon film is low, it is difficult to selectively remove only the silicon oxide film, and there is a problem that the crystalline silicon film is also etched at the same time.

However, when the crystalline silicon film has hydrofluoric acid resistance, the difference (selectivity) between the etching rates of the silicon oxide film and the crystalline silicon film can be made large. It can be selectively removed, which is extremely advantageous in the manufacturing process. As described above, the region where the crystal is grown in the lateral direction has a low concentration of the catalytic element and has good crystallinity. Therefore, it is advantageous to use this region as the active region of the semiconductor device. For example, it is extremely useful to use it as a TFT channel formation region.

[Embodiment 3] In this embodiment, a TFT is manufactured using a crystalline silicon film manufactured by using the method of the present invention. The TFT of this embodiment can be used for a driver circuit or a pixel portion of an active matrix type liquid crystal display device. It is needless to say that such a TFT can be used not only in a liquid crystal display device but also in a thin film integrated circuit generally called.

FIG. 3 shows an outline of the manufacturing process of this embodiment.
First, an underlying silicon nitride film (not shown) is formed on the N0 glass substrate 11, and a silicon oxide film (not shown) is
A film is formed to a thickness of 00 °. The silicon nitride film and the silicon oxide film are provided for preventing diffusion of impurities from the glass substrate.

Then, an amorphous silicon film 104 is formed to a thickness of 500 ° in the same manner as in the first embodiment. As the film forming means, it was effective in terms of device characteristics to use amorphous silicon formed by LPCVD using polysilane such as silane or disilane. After the hydrofluoric acid treatment for removing the natural oxide film, a thin oxide film is formed to a thickness of about 20 ° by irradiation with UV light in an oxygen atmosphere. The thin oxide film may be formed by a method using a water treatment or thermal oxidation.

Then, an acetate solution containing 10 ppm of nickel is applied, held for 5 minutes, and spin-dried using a spinner. Thereafter, the silicon oxide film is removed with buffered hydrofluoric acid, and the silicon film is crystallized by heating at 550 ° C. for 4 hours. By performing the heat treatment, a silicon film in which an amorphous component and a crystalline component are mixed can be obtained. This crystal component is a region where a crystal nucleus during subsequent crystal growth at a high temperature is present.

Thereafter, annealing is performed at 800 ° C. for 2 hours in nitrogen to crystallize the entire surface and promote the crystallinity of the silicon film. By this step, crystal growth is performed with the crystal nuclei existing in the crystal components as nuclei. Next, an island-shaped region 104 is formed by patterning the crystallized silicon film. The island-shaped region 104 forms an active layer of the TFT. Then, silicon oxide 105 having a thickness of 200 to 1500 °, here 1000 °, is formed. This silicon oxide film functions as a gate insulating film. (FIG. 3 (A))

In this state, heat treatment in an electric furnace or irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) or strong light equivalent thereto is performed, whereby the silicon active layer region 104 and the silicon oxide film 105 are irradiated.
May be improved. In particular, RTA (rapid thermal annealing) using infrared light can selectively heat only silicon without heating the glass substrate, so that the temperature of the substrate is kept at or below the softening point of N0 glass. Annealing equivalent to high-temperature annealing can be performed, and the interface state at the interface between silicon and the silicon oxide film can be reduced.

Thereafter, a tantalum film having a thickness of 2000 to 1 μm is formed by an electron beam evaporation method, and is patterned to form a gate electrode 106. Next, anodic oxidation is performed using platinum as a cathode and the tantalum gate electrode as an anode. The anodic oxidation is performed by first increasing the voltage to 80 V with a constant current and maintaining the state for one hour to complete the process. In this embodiment, in the constant current state, the voltage rising speed is suitably 2 to 5 V / min. In this way, the thickness of 1500 to 350
The anodic oxide 109 of 0 °, for example, 2000 ° is formed. (FIG. 3 (B))

Thereafter, an impurity (phosphorus) is implanted into the island-like silicon region of each TFT in a self-aligned manner by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. The dose is 1-4 × 10 ¹⁵ c
m ^-2 .

Further, as shown in FIG. 3C, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) is applied to improve the crystallinity of the portion where the crystallinity is deteriorated by the introduction of the impurity region. The energy density of the laser is 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . Thus, N-type impurity (phosphorus) regions 108 and 109 are formed. The sheet resistance in these regions was 200 to 800 Ω / □.

In the above step, heat treatment in an electric furnace may be used instead of using laser light. Also,
1000-120 in a short time using a flash lamp
The temperature is raised to 0 ° C. (temperature of the silicon monitor) to heat the sample, so-called RTA (rapid thermal annealing; also called RTP, rapid thermal process).
Alternatively, strong light equivalent to so-called laser light may be used.

Then, an interlayer insulator 110 is formed on the entire surface.
Plasma CVD of TEOS as raw material and oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
A silicon oxide film having a thickness of 3000 is formed by method D. The substrate temperature is 250 to 450 ° C., for example, 350 ° C.
After the film formation, the silicon oxide film is mechanically polished to obtain a flat surface. (FIG. 3 (D))

Then, the interlayer insulator 110 is etched to form contact holes in the source / drain of the TFT as shown in FIG. 1E, and wirings 112 and 113 of chromium or titanium nitride are formed. Conventionally, a crystalline silicon film into which nickel has been introduced by using a plasma treatment has a lower selectivity to buffered hydrofluoric acid than a silicon oxide film.
In the step of forming the contact hole, etching is often performed.

However, when nickel is introduced by using an aqueous solution at a low concentration of 10 ppm as in this embodiment, since the hydrofluoric acid resistance is high, it is necessary to stably form the contact hole with good reproducibility. it can. Finally, annealing in hydrogen at 300 to 400 ° C. for 0.1 to 2 hours completes the hydrogenation of the active layer. Thus, the TFT is completed. Then, a large number of TFTs manufactured at the same time are arranged in a matrix to complete an active matrix liquid crystal display device. This TFT has source / drain regions 108/109 and a channel formation region 114. Reference numeral 115 denotes an NI electrical junction.

When the structure of this embodiment is employed, the concentration of nickel present in the active layer is about 3 × 10 ¹⁸ cm ^-3 ,
Alternatively, 1 × 10 ¹⁶ cm ^{−3 to} 3 × 10 ¹⁸ or less.
cm ⁻³ . TF manufactured in this example
As for T, mobility of 200 cm ² / Vs or more in N channel is obtained. In addition, it has been confirmed that the threshold voltage (V _th ) is small and has good characteristics. Further, it has been confirmed that the variation in the mobility is within ± 10%. This small variation is due to incomplete crystallization due to the heat treatment and high temperature in the post-process (800 in this embodiment).
° C) It is considered that this is due to the step of promoting crystallinity by heat treatment. When only the crystallization step by the heat treatment at 650 ° C. or less is used, the N chakel type is 150 cm ^2.
/ Vs or more can be easily obtained, but the variation is large and uniformity as in this embodiment cannot be obtained.

In this embodiment, an embodiment using tantalum gate is shown, but it goes without saying that this may be a silicon gate using N-type or P-type polycrystalline silicon. Further, a configuration may be adopted in which high-temperature thermal annealing is performed after the island is etched. In this case, it is difficult to align the mask due to the shrinkage of the substrate. Therefore, it is desirable to use quartz as the substrate.

[Embodiment 4] In this embodiment, as shown in Embodiment 2, nickel is selectively introduced, and electrons are grown by using a region where crystals are grown laterally (in a direction parallel to the substrate) from that portion. 4 shows an example of forming a device. When such a configuration is employed, the nickel concentration in the active layer region of the device can be further reduced, and a highly preferable configuration can be obtained from the viewpoint of electrical stability and reliability of the device.

FIG. 4 shows a manufacturing process of this embodiment. First,
The quartz substrate 201 is washed, and a 2000-nm-thick silicon oxide base film 202 is formed by plasma CVD using TEOS and oxygen as source gases. This step can be neglected if problems such as contamination can be neglected. Then, an intrinsic (I-type) amorphous silicon film 203 having a thickness of 500 to 1500 Å, for example, 1000 例 え ば is formed by a plasma CVD method. Next, a silicon oxide film 205 having a thickness of 500 to 2000 Å, for example, 1000 連 続 is continuously formed by a plasma CVD method. Then, the silicon oxide film 205 is selectively etched to form a region 206 where amorphous silicon is exposed.

Next, a solution (here, an acetate solution) containing nickel, which is a catalyst element for promoting crystallization, is applied by the method described in the second embodiment. The concentration of nickel in the acetic acid solution is 100 ppm. Other detailed steps and conditions are the same as those described in the second embodiment.

Thereafter, under a nitrogen atmosphere, 500 to 620
C., for example, at 550.degree. C. for 4 hours, to crystallize the silicon film 203. FIG. The crystallization proceeds in a direction parallel to the substrate as indicated by an arrow, starting from the region 206 where the nickel and silicon films are in contact. In the drawing, a region 204 indicates a portion crystallized by directly introducing nickel, and a region 203 indicates a portion crystallized in the lateral direction. The crystal in the horizontal direction indicated by 203 is 25 μm
It is about. Further, it has been confirmed that the crystal growth direction is substantially in the <111> axis direction. (FIG. 4 (A))

After the crystallization step by the above-described heat treatment, the silicon oxide film 205 is entirely etched, and then high-temperature thermal annealing is further performed at 1050 ° C. for about 60 minutes in oxygen to improve the crystallinity. In this step, a thermal oxide film of about 1000 ° is formed simultaneously with the improvement of the crystallinity. When stress does not matter, this thermal oxide film may be used as a gate insulating film. In this embodiment, in consideration of stress, the use of a thermal oxide film as the gate insulating film was avoided.

Next, the thermal oxide film is removed. Then, the silicon film 204 is dry-etched to form the island-shaped active layer region 2.
08 is formed. At this time, a region indicated by 206 in FIG. 4A is a region where nickel is directly introduced, and is a region where nickel is present at a high concentration. It has also been confirmed that nickel also exists at a high concentration at the tip of crystal growth. It has been found that in these regions, the nickel concentration is higher than in the intermediate region. Therefore, in the present embodiment, in the active layer 208,
The circuit was designed such that these regions with a high nickel concentration did not overlap with the channel formation region.

Thereafter, a high-temperature CVD oxide film is formed by LPCVD using TEOS while the substrate is heated to 800 ° C. to 850 ° C. This becomes the silicon oxide film 209 acting as a gate insulating film. This silicon oxide film 209
Is 1000 mm thick. (FIG. 4 (B)) Subsequently, a polycrystalline silicon film doped with P or B serving as a gate electrode is formed to a thickness of 1000 to 400 by LPCVD.
A gate electrode 2
Form 10. (FIG. 4 (C))

Next, by an ion doping method (also referred to as a plasma doping method), an impurity for imparting an N conductivity type in a self-aligned manner to the active layer region (which constitutes the source / drain and channel) using the gate electrode 210 as a mask. (Here, phosphorus) is added. Phosphine (PH ₃ ) is used as a doping gas, and the accelerating voltage is 60 to 90 k.
V, for example, 80 kV. Dose amount is 1 × 10 ¹⁵ -8
× 10 ¹⁵ cm ^-2 , for example, 4 × 10 ¹⁵ cm ^-2 . As a result, N-type impurity regions 212 and 213 can be formed.

Thereafter, heating was performed in a nitrogen atmosphere at 600 ° C. for 12 hours to activate the impurities. After this activation step, if necessary, at 400 ° C. in a hydrogen atmosphere,
Heat treatment for one hour was effective in lowering the defect level density. Subsequently, a silicon oxide film 2 having a thickness of 6000
14 is formed as an interlayer insulator by a plasma CVD method. Further, a transparent polyimide film 215 is formed by spin coating, and the surface is flattened.

Then, contact holes are formed in the interlayer insulators 214 and 215, and the electrodes / wirings 217 and 218 of the TFT are formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete an active matrix circuit having a TFT. (FIG. 4F) Since the TFT manufactured in this embodiment can obtain high mobility, it can be used for a driver circuit of an active matrix liquid crystal display device.

[Embodiment 5] FIG. 5 is a sectional view showing a manufacturing process of this embodiment. First, a silicon oxide base film 502 having a thickness of 2000 ° is formed on a quartz substrate 501 by a sputtering method.
To form Next, plasma CVD or LPCVD
Depending on the method, the thickness may be 500-1500Å, for example 1000
Å An intrinsic (I-type) amorphous silicon film is formed. And
According to the method described in the first embodiment, nickel is introduced as a catalytic element for promoting crystallization to the surface of the amorphous silicon film. Then, it is crystallized by thermal annealing in a nitrogen atmosphere (atmospheric pressure) at 550 ° C. for 4 hours. Then, the silicon film is formed in a thickness of 10 to 1000 μm.
Etching to the size of m-square, island-like silicon film (TFT
503) is formed. (FIG. 5 (A))

Thereafter, annealing is performed for about 2 hours in an oxygen atmosphere at 800 to 1100 ° C., typically 1000 ° C., to improve the crystallinity and the characteristics of the interface, and to further improve the gate insulating film made of a thermal oxide film. The film 504 has a thickness of 500
It is formed to a thickness of about 1500 °, for example, 1000 °. It should be noted that due to such oxidation, the surface of the initial silicon film is reduced by 50 ° or more, and as a result, the contamination of the outermost surface portion of the silicon film does not reach the silicon-silicon oxide interface. is there. That is, a clean silicon-silicon oxide interface is obtained. Since the thickness of the silicon oxide film is twice as large as that of the silicon film to be oxidized, when a silicon film having a thickness of 1000 mm is oxidized to obtain a silicon oxide film having a thickness of 1000 mm, the thickness of the remaining silicon film is reduced. The thickness will be 500 mm.

After the silicon oxide film 504 is formed by thermal oxidation, a nitrous oxide atmosphere (1 atm, 100%), 6
Anneal at 00 ° C. for 2 hours. (FIG. 5 (B)) Subsequently, a thickness of 3000 to 8 is applied by a low pressure CVD method.
000 °, for example, 6000 ° of polycrystalline silicon (0.01 to
(Containing 0.2% phosphorus). Then, the gate electrode 505 is formed by etching the silicon film. further,
Using this silicon film as a mask, an impurity (phosphorus in this case) for imparting N conductivity type to the active layer region (source / drain and channel) is self-aligned by ion doping (also called plasma doping). Added.

As a doping gas, phosphine (P
H ₃ ) and an acceleration voltage of 60 to 90 kV, for example, 80
kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ c
m ⁻² , for example, 5 × 10 ¹⁵ cm ⁻² . As a result, N
Mold impurity regions 506 and 507 are formed. afterwards,
A thermal annealing process is performed in nitrogen at 600 ° C. for 12 hours to activate the impurities. The activation step may be performed by laser light irradiation. (FIG. 5 (C))

Similarly, the step of activating the impurities comprises:
A lamp annealing method using near-infrared light may be used. Near infrared rays are more easily absorbed by crystallized silicon than amorphous silicon, and effective annealing comparable to thermal annealing at 1000 ° C. or higher can be performed. On the other hand, it is hardly absorbed by the glass substrate (far-infrared light is absorbed by the glass substrate, but visible / near-infrared light (wavelength: 0.5 to 4 μm) is hardly absorbed). Since heating is not required and processing can be performed in a short time, it can be said that this method is an optimal method in a process in which shrinkage of a glass substrate becomes a problem.

Subsequently, a silicon oxide film 50 having a thickness of 6000.degree.
8 is formed as an interlayer insulator by a plasma CVD method. Polyimide may be used as the interlayer insulator. Further, a contact hole is formed, and TF is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
T electrodes / wirings 509 and 510 are formed. Finally, 1
Annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at atmospheric pressure to complete the TFT. (FIG. 5 (D))

The mobility of the TFT obtained by the above method is 110 to 150 cm ² / Vs, and the S value is 0.2 to 0.5.
V / digit. In addition, a P-channel TFT in which the source / drain was doped with boron was manufactured by the same method, and the mobility was 90 to 120 cm ² / Vs.
The S value is 0.4 to 0.6 V / digit, the mobility is 20% or more higher than the case where a gate insulating film is formed by a known PVD method or CVD method, and the S value is 20% or more. Diminished.

[Embodiment 6] In this embodiment, an electro-optical system using an integrated circuit including a display, a CPU, and a memory mounted on one glass substrate as shown in FIG. 6 will be described. This embodiment is an example in which each integrated circuit is manufactured by using a TFT using a crystalline silicon film according to the present invention.

In FIG. 6, an input port reads a signal inputted from the outside and converts it into an image signal. A correction memory is provided on a panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. It is a unique memory. In particular, the correction memory has information unique to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected in accordance therewith is sent to pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when a pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the brightness of the surrounding pixels is the same.

The CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. Further, the backlight that irradiates the substrate from the back surface can be changed according to the image information. As shown in this embodiment, a highly integrated liquid crystal display device can be obtained by forming an integrated circuit required for a TFT using a crystalline silicon film over the same substrate.

[Embodiment 7] This embodiment will be described with reference to FIGS. FIG. 7 is a sectional view showing a step of manufacturing a TFT in this embodiment. After the quartz substrate 701 was washed with a mixed solution of hydrogen peroxide and ammonia (aqueous ammonia) at 70 ° C., a 2000-μm-thick silicon oxide film 702 was deposited by sputtering. Further, an amorphous silicon film having a thickness of 500 ° was deposited by a plasma CVD method. The substrate temperature during film formation was 160 ° C.

Then, a very thin silicon oxide film was formed on the surface of the amorphous silicon film by immersing the substrate in an aqueous ammonia solution at 70 ° C. for 5 minutes. Then, a nickel acetate solution was applied to the surface of the silicon film in the same manner as in Examples 1 and 2 by spin coating. Nickel acetate concentration is 10p
pm. Thereafter, a thermal annealing process was performed to crystallize the amorphous silicon film. The thermal annealing treatment was performed in two stages: first, a process mainly for removing hydrogen at 450 ° C. for 1 hour, and a subsequent process for crystallization at 550 ° C. for 2 hours. Thus, a crystalline silicon film 703 was obtained.

Further, the silicon oxide film on the surface of the silicon film is removed with an etchant in which acetic acid, hydrofluoric acid, and ammonium fluoride are mixed at a ratio of 50: 1: 50, and in this state, a KrF excimer laser beam is irradiated. Furthermore, the crystallinity was improved. (FIG. 7 (A)) Then, thermal oxidation is performed at 550 ° C. for one hour to form a thin silicon oxide protective film (not shown) on the silicon film surface, and the silicon film is dry-etched to form an island shape. Active layer region 704
(For N-channel TFT), 705 (for P-channel TFT)
For) formed. (FIG. 7 (B))

Next, phosphorus and boron are selectively implanted into the active layer by ion doping to form an N-channel type TF.
T source 706, drain 707, P channel type TF
A source 708 and a drain 709 of T were formed. The dose of phosphorus was 5 × 10 ¹⁴ cm ⁻² , the acceleration voltage was 10 kV, the dose of boron was 1 × 10 ¹⁵ cm ⁻² , and the acceleration voltage was 10 kV. Then, the silicon oxide protective film was removed. (FIG. 7
(C))

Again, thermal oxidation is performed at 550 ° C. for 1 hour to form a thin silicon oxide film on the surface of the active layer region.
The thickness is 12 by the plasma CVD method using TEOS.
A silicon oxide film 710 of 00 ° was deposited. And 800
A thermal annealing treatment was performed at 30 ° C. for 30 minutes. At this time, in this embodiment, two kinds of thermal annealing treatments were performed. That is, the first is thermal annealing (sample A) in a nitrogen atmosphere.
The second is thermal annealing (sample B) in a dinitrogen monoxide atmosphere.

Next, a thickness of 4000 mm is formed by a sputtering method.
Was deposited. 0.1 for aluminum
It contained 8% by weight of scandium (Sc). Then, the aluminum film is etched and the gate electrode 71 is etched.
1 (for N-channel TFT), 712 (for P-channel TFT)
For) formed. At this time, various positional relationships between the gate electrode and the source / drain were formed. That is, the distance between the drain and the gate electrode is x [μm], the distance between the source and the gate electrode is y [μm], and x = + 4, +
2, +1, 0, -2, y = + 4, +2, +1, 0, -2
And Here, the negative sign means that the source / drain and the gate electrode overlap.

Further, an ammonia solution of tartaric acid (pH =
By performing anodic oxidation in 6.9 to 7.1), anodic oxide (aluminum oxide) films 713 and 714 having a thickness of about 2000 ° were formed on the surface of the gate electrode. For the anodic oxidation, a method described in JP-A-5-267667 was used. After the anodizing step, the gate wiring was divided. (FIG. 7 (D))

Then, the interlayer insulator 715 is plasma-CV
Deposited by method D. The interlayer insulator had a two-layer structure of a silicon nitride film (lower film) with a thickness of 500 ° and a silicon oxide film (upper film) with a thickness of 5000 °. The substrate temperature during film formation is 35
0 ° C. Then, a contact hole was opened in the interlayer insulator, and a metal film having a two-layer structure of a titanium film having a thickness of 500 ° and an aluminum film (containing 2% of silicon) having a thickness of 8000 ° was deposited by a sputtering method.

Thereafter, the metal film is dry-etched,
A source electrode 716 and a drain electrode 717 of an N-channel TFT and a source electrode 718 and a drain electrode 719 of a P-channel TFT were formed. Finally, thermal annealing was performed at 350 ° C. for one hour in a hydrogen atmosphere. Thus, a TFT was formed. (FIG. 7E) Further, a passivation film may be formed using a silicon nitride film in order to prevent moisture, mobile ions, and the like from entering from the outside.

In this embodiment, unlike Embodiments 3 to 5,
After the source / drain is formed, a high-temperature (800 ° C. in this embodiment) thermal annealing process is performed. In this step, not only the crystallinity of silicon of the active layer is improved, but also the activation of the source / drain and the improvement of the interface characteristics of the gate insulating film can be performed at the same time.

In this embodiment, two kinds of samples were prepared by using nitrogen (sample A) and dinitrogen monoxide (sample B) as the atmosphere during the above-described thermal annealing treatment. The characteristics were good. For example, the S value of the N-channel TFT was 0.16 to 0.23 V / digit for sample A, but was 0.14 to 0.19 V / digit for sample B. This indicates that the interface characteristics of the gate insulating film by dinitrogen monoxide have been improved. However, P
No significant difference was found for the channel type TFT.

FIGS. 8 to 11 show the relationship between the offset length of the gate electrode / source / drain and the TFT characteristics. 8 shows the initial field-effect mobility, FIG. 9 shows the variation rate of the field-effect mobility after repeating the measurement 10 times (a negative sign means an increase in the field-effect mobility), and FIG. 10 shows the initial threshold. 11 shows an initial off-state current, and FIG. 11A shows a P-channel TFT and FIG. 11B shows an N-channel TFT.

The variation rate of the field-effect mobility (FIG. 9) was not evaluated because elements having a field-effect mobility of less than 10 cannot be evaluated significantly. From the above results, it can be seen that good characteristics were not obtained in a device in which the gate and the source / drain were too far apart, and preferable characteristics were obtained in a device in which the gate electrode and the source / drain slightly overlapped. (FIGS. 8 to 11)

[0099]

[Effect] By introducing a catalytic element to form a crystalline silicon film having a large grain size at a relatively low temperature and then annealing at a higher temperature, a silicon film having a very high crystallinity can be obtained. When a semiconductor device is manufactured using such a crystalline silicon film, a device with high productivity and excellent characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 shows the steps of an example.

FIG. 2 shows a process of an example.

FIG. 3 shows a manufacturing process of an example.

FIG. 4 shows a manufacturing process of an example.

FIG. 5 shows a manufacturing process of an example.

FIG. 6 shows a configuration of an example.

FIG. 7 shows a manufacturing process of an example.

FIG. 8 shows TFT characteristics (field-effect mobility) of an example.

FIG. 9 shows TFT characteristics (variation rate of field-effect mobility) of an example.

FIG. 10 shows TFT characteristics (threshold voltage) of the example.

FIG. 11 shows TFT characteristics (off-state current) of the example.

[Explanation of symbols]

 11 ··· glass substrate 12 ··· amorphous silicon film 13 ··· silicon oxide film 14 ··· acetic acid solution film containing nickel 15 ··· spinner 21 ··· for mask Silicon oxide film 20 silicon oxide film 11 glass substrate 104 active layer 105 silicon oxide film 106 gate electrode 109 oxide layer 108 source / Drain region 109 ... Drain / source region 110 ... Interlayer insulating film (silicon oxide film) 112 ... Electrode 113 ... Electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/12 (56) References JP-A-61-63107 (JP, A) JP-A-3-280420 (JP, A) JP-A-5-82442 (JP, A) JP-A-7-161634 (JP, A)

Claims (26)

(57) [Claims] 1. A to have a active region formed on a quartz substrate
That a semiconductor device, said active region, a heat treatment of 450 ° C. to 650 ° C. in a state in which a layer containing a catalytic element for promoting crystallization of amorphous silicon is in contact with the upper or lower surface of the amorphous silicon film And said heat treatment
Thermal annealing at a temperature higher than the heat treatment temperature in an electric furnace after patterning the amorphous silicon film into islands ,
A crystalline silicon film obtained by crystallizing the amorphous silicon film
The semiconductor device characterized by comprising at. 2. The semiconductor device according to claim 1, wherein in the active region, the silicon film having crystallinity has crystal grains having a grain size of 10 μm or more. 3. to have a active region formed on a quartz substrate
A semiconductor device that, said active region, 450 ° C. in a state in which a layer containing a catalytic element for promoting crystallization of amorphous silicon is selectively contact with the upper surface or lower surface of the amorphous silicon film 650 C heat treatment and the heat
After the treated amorphous silicon film is patterned into an island shape, the amorphous silicon film is crystallized by thermal annealing at a temperature higher than the heat treatment temperature in an electric furnace . Have
A semiconductor device comprising a silicon film . 4. The method of claim 3, in the active region, the silicon film having a crystalline semiconductor device which features that it is binding <br/> crystal growth in the schematic <111> axis. 5. A any one <br/> of claims 1 to 4, a silicon film having a crystallinity, wherein a polycrystalline silicon film. 6. A any one <br/> of claims 1 to 5, as the catalyst element, Ni, Pd, Pt, C
A semiconductor device, wherein one or more elements selected from u, Ag, Au, In, Sn, P, As, and Sb are used. 7. The any one <br/> of claims 1 to 5, as the catalyst element, VIII group, IIIb group, IVb
A semiconductor device, wherein one or more elements selected from the group consisting of Vb and Vb elements are used. 8. A any one <br/> of claims 1 to 7, the concentration of the catalyst element in the active region, 1 × 10 ¹⁹ atoms · A semiconductor device having a size of cm ^-3 or less. 9. A any one <br/> of claims 1 to 8, wherein the active region is a semiconductor device comprising PI, PN, that has at least one bonding represented by NI. 10. The method according to claim 1, wherein:
In the paragraph , the semiconductor device is a thin film transistor, a diode, or an optical sensor. 11. to contact the upper surface or lower surface of the amorphous silicon film formed on a quartz substrate, a step of forming a layer containing a catalytic element for promoting crystallization of amorphous silicon, the non Heat treating the amorphous silicon film at 450 ° C. to 650 ° C. to crystallize the amorphous silicon film; and patterning the crystallized silicon film to form an island-shaped region.
Forming an area, and thermally annealing the island area at a higher temperature than the heat treatment in an electric furnace to form the island area.
Promoting the crystallinity of the region . 12. selective contact to the upper surface or lower surface of the amorphous silicon film formed on a quartz substrate, selectively forming a layer containing a catalytic element for promoting crystallization of amorphous silicon Performing a heat treatment of the amorphous silicon film at 450 ° C. to 650 ° C. to crystallize the amorphous silicon film; and patterning the crystallized silicon film to form an island-shaped region.
Forming an area, and thermally annealing the island area at a higher temperature than the heat treatment in an electric furnace to form the island area.
Promoting the crystallinity of the region . 13. The method according to claim 11, wherein
A method for manufacturing a semiconductor device, wherein the temperature of the thermal annealing in the step of promoting the crystallinity of the island region is 800 ° C. to 1100 ° C. 14. in contact with the upper or lower surface of the amorphous silicon film formed on a quartz substrate, a higher engineering that form a layer containing a catalytic element for promoting crystallization of amorphous silicon, Heat-treating the amorphous silicon film at 450 ° C. to 650 ° C. to generate crystal nuclei in a region of the amorphous silicon film in contact with the layer containing the catalytic element ; Pattern to form island-shaped areas
Forming the island-shaped region in an electric furnace at a higher temperature than the heat treatment.
The thermally annealed, Ryo of the island and the crystal nucleus in the nucleus
Crystallizing a region ; and a method for manufacturing a semiconductor device. 15. selective contact to the upper surface or lower surface of the amorphous silicon film formed on a quartz substrate, that form a layer containing a catalytic element which promotes crystallization of the amorphous silicon Engineering a degree, the steps of the amorphous silicon film was heat-treated at 450 ° C. to 650 ° C., to generate a crystal nucleus region in contact with the layer containing the catalyst element in the amorphous silicon film, the amorphous Pattern the silicon film to form island-like regions
A step of forming said thermally annealing the island-like regions <br/> at a temperature higher than the heat treatment in an electric furnace, and the crystal nuclei in the nuclear form of the island territories
Crystallizing a region ; and a method for manufacturing a semiconductor device. 16. Any of claims 11 to 15
In any one of the above items , Ni, Pd, P
A method for manufacturing a semiconductor device, wherein one or more elements selected from t, Cu, Ag, Au, In, Sn, P, As, and Sb are used. 17. Any of claims 11 to 15
In any one of the above-mentioned, the catalyst element may be a group VIII, IIIb
A method for manufacturing a semiconductor device, comprising using one or more kinds of elements selected from Group IV, Group IVb, and Group Vb elements. 18. Any of claims 11 to 17
In one paragraph, the concentration of the catalyst element of the crystalline been crystalline silicon film promotes the semiconductor instrumentation 置作 made wherein the at 1 × 10 ¹⁹ atoms · cm ^-3 or less. 19. Any of claims 11 to 18
Or in item 1, the crystalline silicon film which is conducive to the crystallinity, semiconductor instrumentation 置作 <br/> made wherein the polycrystalline silicon film. 20. Any of claims 11 to 19
2. The method for manufacturing a semiconductor device according to claim 1 , wherein the layer containing the catalyst element is formed by a coating method using a solution containing the catalyst element. 21. The method according to claim 20, wherein the solvent of the solution containing the catalyst element is a polar solvent, and at least one of water, an alcohol, an acidic solution, and an aqueous ammonia solution is used as the polar solvent. A method for manufacturing a semiconductor device. 22. The solvent according to claim 20, wherein the solvent of the solution containing the catalyst element is a polar solvent, at least nickel is used as the catalyst element, and nickel bromide, nickel acetate, nickel oxalate are used as the solute of the solution. At least one nickel compound selected from the group consisting of nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, nickel formate, nickel acetylacetonate, nickel 4-cyclohexylbutyrate, nickel oxide and nickel hydroxide A method for manufacturing a semiconductor device, which is used. 23. The method according to claim 20, wherein a surfactant is added to the solution containing the catalyst element. 24. The solvent according to claim 20, wherein the solvent of the solution containing the catalyst element is a non-polar solvent, and the non-polar solvent includes benzene, toluene, xylene, carbon tetrachloride,
A method for manufacturing a semiconductor device, wherein at least one of chloroform and ether is used. 25. The solvent according to claim 20, wherein the solvent of the solution containing the catalyst element is a nonpolar solvent, at least nickel is used as the catalyst element, and nickel acetylacetonate, 4 -Nickel cyclohexyl butyrate, nickel oxide, nickel hydroxide, 2-
A method for manufacturing a semiconductor device, wherein at least one nickel compound selected from nickel ethylhexanoate is used. 26. The method according to claim 20, wherein the solution containing the catalyst element is a solution for forming a silicon oxide film containing the catalyst element.