JPH0582442A - Manufacture of polycrystalline semiconductor thin film - Google Patents

Manufacture of polycrystalline semiconductor thin film

Info

Publication number
JPH0582442A
JPH0582442A JP26846991A JP26846991A JPH0582442A JP H0582442 A JPH0582442 A JP H0582442A JP 26846991 A JP26846991 A JP 26846991A JP 26846991 A JP26846991 A JP 26846991A JP H0582442 A JPH0582442 A JP H0582442A
Authority
JP
Japan
Prior art keywords
thin film
polycrystalline semiconductor
semiconductor thin
layer
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26846991A
Other languages
Japanese (ja)
Inventor
Takashi Noguchi
隆 野口
Toshiharu Suzuki
俊治 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP26846991A priority Critical patent/JPH0582442A/en
Publication of JPH0582442A publication Critical patent/JPH0582442A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve the crystallinity of a polycrystalline semiconductor thin film so as to improve the transistor characteristics of the thin film, such as mobility, ON/OFF ratio, etc., by annealing the thin film formed to crystals of a large grain size by irradiating the thin film with excimer laser light. CONSTITUTION:In the first process, a polycrystalline semiconductor layer 14 is grown by growing an amorphous semiconductor layer 13b formed on the upper surface of a substrate 11 by low-temperature solid-phase growth and, in the second process, a polycrystalline semiconductor thin film 15 is formed by reducing the thickness of the layer 14 by removing the upper layer side of the layer 14. In the third process, the thin film 15 is annealed by irradiating the thin film 15 with excimer laser light 30.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多結晶半導体薄膜の製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline semiconductor thin film.

【0002】[0002]

【従来の技術】非晶質シリコンの低温固相成長は現在非
常に盛んに行われている。この低温固相成長では、結晶
の大粒径化が可能である。しかし、大粒径化したシリコ
ン粒(粒径が1μm以上のもの)の内部には、双晶や転
移等の微小な結晶欠陥が存在するために、高温アニール
処理が必要になる。特に高温で非常に短時間で行うアニ
ール処理の一つに、エキシマレーザ光照射によって膜全
体を溶融することなくアニール処理する方法がある。こ
のアニール処理方法は、処理後の膜の平坦性がよくしか
も低温化プロセスに適合する。このため、SRAMやL
CD等の製造方法におけるアニール処理方法として有効
である。
2. Description of the Related Art Low temperature solid phase growth of amorphous silicon is now very popular. With this low temperature solid phase growth, it is possible to increase the crystal grain size. However, high-temperature annealing is required because minute crystal defects such as twins and dislocations are present inside the silicon grains having a large grain size (having a grain size of 1 μm or more). In particular, one of the annealing treatments performed at a high temperature in a very short time is a method of performing the annealing treatment by excimer laser light irradiation without melting the entire film. This annealing method has good flatness of the film after processing and is suitable for a low temperature process. Therefore, SRAM and L
It is effective as an annealing method in the manufacturing method of CDs and the like.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、エキシ
マレーザ光は、その波長が短く、シリコンに対する吸収
係数(α)がおよそ106 cm-1と大きい。このため、
エキシマレーザ光は、多結晶シリコン膜中の10nm程
度の深さまでしか到達しないので、エキシマレーザ光照
射によってアニール処理される深さは熱伝導を考慮して
40nm程度になる。ところが、厚さが40nm程度以
下の多結晶シリコン膜では、十分な大きさの結晶粒が得
られない。そこで、大きな結晶粒(例えば粒径が1μm
以上)が得られる厚い多結晶シリコン膜(例えば厚さが
100nm)を形成し、この厚い多結晶シリコン膜に対
してエキシマレーザ光照射によるアニール処理を行った
場合には、厚い多結晶シリコン膜は深さがおよそ40n
mまでしかアニール処理されない。 したがって、膜厚
方向の全域にわたって結晶性に優れた大きな結晶粒を有
する多結晶シリコン膜を形成することは困難であった。
However, excimer laser light has a short wavelength and a large absorption coefficient (α) for silicon of about 10 6 cm -1 . For this reason,
Since the excimer laser light reaches only a depth of about 10 nm in the polycrystalline silicon film, the annealing depth by the irradiation of the excimer laser light is about 40 nm in consideration of heat conduction. However, with a polycrystalline silicon film having a thickness of about 40 nm or less, a sufficiently large crystal grain cannot be obtained. Therefore, large crystal grains (for example, grain size 1 μm
When a thick polycrystalline silicon film (for example, having a thickness of 100 nm) that can obtain the above) is formed and the thick polycrystalline silicon film is annealed by irradiation of excimer laser light, the thick polycrystalline silicon film is Depth is about 40n
It is annealed only up to m. Therefore, it is difficult to form a polycrystalline silicon film having large crystal grains with excellent crystallinity over the entire thickness direction.

【0004】本発明は、結晶性に優れた多結晶半導体薄
膜の製造方法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a polycrystalline semiconductor thin film having excellent crystallinity.

【0005】[0005]

【課題を解決するための手段】本発明は、上記目的を達
成するためになされた多結晶半導体薄膜の製造方法であ
る。すなわち、第1の工程で、基板の上面に形成した非
晶質半導体層を低温固相成長させることにより多結晶半
導体層を形成し、次いで第2の工程で、多結晶半導体層
の上層側を除去することで、当該多結晶半導体層を薄膜
化して多結晶半導体薄膜を形成する。その後第3の工程
で、多結晶半導体薄膜にエキシマレーザ光を照射してア
ニール処理する。
The present invention is a method for manufacturing a polycrystalline semiconductor thin film, which has been made to achieve the above object. That is, in the first step, the amorphous semiconductor layer formed on the upper surface of the substrate is subjected to low temperature solid phase growth to form a polycrystalline semiconductor layer, and then in the second step, the upper side of the polycrystalline semiconductor layer is formed. By removing, the polycrystalline semiconductor layer is thinned to form a polycrystalline semiconductor thin film. Then, in a third step, the polycrystalline semiconductor thin film is irradiated with excimer laser light and annealed.

【0006】[0006]

【作用】上記多結晶半導体薄膜の製造方法では、多結晶
半導体層を非晶質半導体層の低温固相成長により形成し
たので、多結晶半導体層は大粒径の結晶で形成される。
また多結晶半導体層を薄膜化し、多結晶半導体薄膜を形
成した後にエキシマレーザ光を照射したので、多結晶半
導体薄膜の膜厚方向の全域にわたって均一にアニール処
理される。
In the above method of manufacturing a polycrystalline semiconductor thin film, the polycrystalline semiconductor layer is formed by low temperature solid phase growth of the amorphous semiconductor layer, so that the polycrystalline semiconductor layer is formed of crystals having a large grain size.
Further, since the polycrystalline semiconductor layer is thinned and the polycrystalline semiconductor thin film is formed and then irradiated with the excimer laser light, the polycrystalline semiconductor thin film is uniformly annealed over the entire thickness direction.

【0007】[0007]

【実施例】本発明の実施例を図1に示す製造工程図によ
り説明する。図に示すように、まず第1の工程(1)
で、例えば化学的気相成長法によって、基板(例えばシ
リコン基板)11の上面に酸化シリコン(SiO2 )層
12を形成する。続いて例えば化学的気相成長法によっ
て、酸化シリコン層12の上面に非晶質シリコンよりな
る非晶質半導体層13を40nm以上の厚さ(例えば1
50nmの厚さ)に成膜する。次いで第1の工程(2)
で、低温(例えばおよそ600℃で20時間)で固相成
長させることにより、非晶質半導体層13中に結晶粒を
成長させて、例えば粒径が2μm以上の多結晶シリコン
よりなる多結晶半導体層14を形成する。
Embodiments of the present invention will be described with reference to the manufacturing process diagrams shown in FIG. As shown in the figure, first, the first step (1)
Then, a silicon oxide (SiO 2 ) layer 12 is formed on the upper surface of a substrate (for example, a silicon substrate) 11 by, for example, a chemical vapor deposition method. Then, an amorphous semiconductor layer 13 made of amorphous silicon is formed on the upper surface of the silicon oxide layer 12 by a chemical vapor deposition method to a thickness of 40 nm or more (for example, 1
The thickness is 50 nm). Then the first step (2)
Then, by performing solid phase growth at a low temperature (for example, at about 600 ° C. for 20 hours), crystal grains are grown in the amorphous semiconductor layer 13, and a polycrystalline semiconductor made of polycrystalline silicon having a grain size of 2 μm or more, for example. Form the layer 14.

【0008】また前記第1の工程(1)において、化学
的気相成長法によって基板11の上面に多結晶シリコン
層を形成し、その後形成した多結晶シリコン層にシリコ
ン(Si+ )をイオン注入して、多結晶シリコン層を非
晶質化して、非晶質半導体層13を形成してもよい。あ
るいは、基板11の上面に酸化シリコン層12を形成し
ないで、基板11を石英ガラスで形成し、この基板11
に上記同様に化学的気相成長法によって非晶質シリコン
よりなる非晶質半導体層13を成膜することも可能であ
る。
In the first step (1), a polycrystalline silicon layer is formed on the upper surface of the substrate 11 by the chemical vapor deposition method, and then the formed polycrystalline silicon layer is ion-implanted with silicon (Si + ). Then, the polycrystalline silicon layer may be made amorphous to form the amorphous semiconductor layer 13. Alternatively, without forming the silicon oxide layer 12 on the upper surface of the substrate 11, the substrate 11 is formed of quartz glass, and the substrate 11 is formed.
Further, similarly to the above, it is possible to form the amorphous semiconductor layer 13 made of amorphous silicon by the chemical vapor deposition method.

【0009】次いで第2の工程で、多結晶半導体層14
の上層側をエッチングして、当該多結晶半導体層14よ
りなる多結晶半導体薄膜15を形成する。多結晶半導体
薄膜15は、エキシマレーザ光30を照射することによ
り多結晶半導体薄膜15の膜厚方向の全域にわたってア
ニール処理される厚さとして、例えば40nm以下の厚
さに形成される。また上記エッチングは、多結晶半導体
薄膜15の被エッチング面が面あれを起こさないよう
に、例えばエッチングダメージが少ない通常のプラズマ
エッチングまたはアンモニア(NH3 )と過酸化水素水
(H2 2 +H2 O)との混合溶液によるウエットエッ
チングで行う。
Then, in a second step, the polycrystalline semiconductor layer 14 is formed.
The upper layer side is etched to form a polycrystalline semiconductor thin film 15 made of the polycrystalline semiconductor layer 14. The polycrystalline semiconductor thin film 15 is formed to have a thickness of, for example, 40 nm or less as a thickness that is annealed over the entire region of the polycrystalline semiconductor thin film 15 in the film thickness direction by irradiating the excimer laser light 30. Further, the above-mentioned etching is carried out by, for example, ordinary plasma etching with little etching damage or ammonia (NH 3 ) and hydrogen peroxide solution (H 2 O 2 + H 2 ) so that the surface to be etched of the polycrystalline semiconductor thin film 15 does not become rough. Wet etching with a mixed solution with O) is performed.

【0010】その後第3の工程で、多結晶半導体薄膜1
5の全面にエキシマレーザ光30(例えばエネルギー密
度がおよそ280mJ/cm2 )を照射して、多結晶半
導体薄膜15をアニール処理する。このアニール処理に
よって、多結晶半導体薄膜15中の双晶や転移等の結晶
欠陥が低減され、多結晶半導体薄膜15の結晶性が改善
される。
Then, in a third step, the polycrystalline semiconductor thin film 1
The entire surface of 5 is irradiated with excimer laser light 30 (for example, energy density is about 280 mJ / cm 2 ) to anneal the polycrystalline semiconductor thin film 15. By this annealing treatment, crystal defects such as twins and dislocations in the polycrystalline semiconductor thin film 15 are reduced, and the crystallinity of the polycrystalline semiconductor thin film 15 is improved.

【0011】上記実施例で説明した如くにして形成した
多結晶半導体薄膜15は、一つの結晶粒が大きく(例え
ば粒径が2μm以上)、その結晶粒の結晶性は改善され
ている。このような多結晶半導体薄膜15の一つの結晶
粒に薄膜トランジスタ(図示せず)を形成した場合また
は複数の結晶粒にわたって薄膜トランジスタ(図示せ
ず)を形成した場合には、リーク電流が少ない、移動度
が高い、スイングが低い、ON/OFF比が大きい等の
特性を有する薄膜トランジスタになる。またエキシマレ
ーザ光照射によるアニール処理では、多結晶半導体薄膜
15の表面がほぼ平坦でしかも面あれがほとんどないの
で、その後のプロセス処理が容易になる。
In the polycrystalline semiconductor thin film 15 formed as described in the above embodiment, one crystal grain is large (for example, the grain size is 2 μm or more), and the crystallinity of the crystal grain is improved. When a thin film transistor (not shown) is formed on one crystal grain of such a polycrystalline semiconductor thin film 15 or when a thin film transistor (not shown) is formed over a plurality of crystal grains, the leakage current is small and the mobility is low. Is a thin film transistor having characteristics such as a high value, a low swing, and a large ON / OFF ratio. Further, in the annealing treatment by irradiation with excimer laser light, the surface of the polycrystalline semiconductor thin film 15 is substantially flat and there is almost no surface roughness, so that the subsequent process treatment becomes easy.

【0012】[0012]

【発明の効果】以上、説明したように本発明によれば、
基板上の非晶質半導体層を低温固相成長させることによ
り多結晶半導体層を形成したので、結晶粒が大きい多結
晶半導体層を生成できる。また多結晶半導体層を薄膜化
して多結晶半導体薄膜を形成した後、エキシマレーザ光
照射を行ったので、多結晶半導体薄膜は膜厚方向の全域
にわたって均一にアニール処理される。したがって、多
結晶半導体薄膜を形成する結晶の粒径は大きく、しかも
各結晶粒中の結晶欠陥が少なくなるので、各結晶粒内に
トランジスタを形成した場合にはトランジスタ特性の向
上が図れる。
As described above, according to the present invention,
Since the polycrystalline semiconductor layer is formed by low-temperature solid-phase growth of the amorphous semiconductor layer on the substrate, the polycrystalline semiconductor layer having large crystal grains can be generated. Further, since the excimer laser light irradiation is performed after thinning the polycrystalline semiconductor layer to form the polycrystalline semiconductor thin film, the polycrystalline semiconductor thin film is uniformly annealed over the entire area in the film thickness direction. Therefore, the grain size of the crystals forming the polycrystalline semiconductor thin film is large, and the crystal defects in each crystal grain are small. Therefore, when the transistor is formed in each crystal grain, the transistor characteristics can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の製造工程図である。FIG. 1 is a manufacturing process diagram of an example.

【符号の説明】[Explanation of symbols]

11 基板 13 非晶質半導体層
14 多結晶半導体層 15 多結晶半導体薄膜 30 エキシマレーザ光
11 substrate 13 amorphous semiconductor layer
14 Polycrystalline semiconductor layer 15 Polycrystalline semiconductor thin film 30 Excimer laser light

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板の上面に形成した非晶質半導体層を
低温固相成長させることにより多結晶半導体層を生成す
る第1の工程と、 前記多結晶半導体層の上層側を除去することで、当該多
結晶半導体層を薄膜化して多結晶半導体薄膜を形成する
第2の工程と、 前記多結晶半導体薄膜層にエキシマレーザ光を照射して
アニール処理する第3の工程とによりなることを特徴と
する多結晶半導体薄膜の製造方法。
1. A first step of forming a polycrystalline semiconductor layer by low-temperature solid-phase growth of an amorphous semiconductor layer formed on an upper surface of a substrate, and removing an upper layer side of the polycrystalline semiconductor layer. A second step of thinning the polycrystalline semiconductor layer to form a polycrystalline semiconductor thin film, and a third step of irradiating the polycrystalline semiconductor thin film layer with an excimer laser beam for annealing treatment. And a method for manufacturing a polycrystalline semiconductor thin film.
JP26846991A 1991-09-18 1991-09-18 Manufacture of polycrystalline semiconductor thin film Pending JPH0582442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26846991A JPH0582442A (en) 1991-09-18 1991-09-18 Manufacture of polycrystalline semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26846991A JPH0582442A (en) 1991-09-18 1991-09-18 Manufacture of polycrystalline semiconductor thin film

Publications (1)

Publication Number Publication Date
JPH0582442A true JPH0582442A (en) 1993-04-02

Family

ID=17458939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26846991A Pending JPH0582442A (en) 1991-09-18 1991-09-18 Manufacture of polycrystalline semiconductor thin film

Country Status (1)

Country Link
JP (1) JPH0582442A (en)

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US6319761B1 (en) 1993-06-22 2001-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US6713330B1 (en) 1993-06-22 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
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US5882960A (en) * 1993-06-25 1999-03-16 Semiconductor Energy Laboratory Co., Ltd Method of preparing a semiconductor having a controlled crystal orientation
US5895933A (en) * 1993-06-25 1999-04-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6756657B1 (en) 1993-06-25 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Method of preparing a semiconductor having controlled crystal orientation
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