JPS5853824A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5853824A
JPS5853824A JP56152681A JP15268181A JPS5853824A JP S5853824 A JPS5853824 A JP S5853824A JP 56152681 A JP56152681 A JP 56152681A JP 15268181 A JP15268181 A JP 15268181A JP S5853824 A JPS5853824 A JP S5853824A
Authority
JP
Japan
Prior art keywords
layer
silicon layer
sio2
amorphous
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56152681A
Other languages
Japanese (ja)
Other versions
JPH0335821B2 (en
Inventor
Junji Sakurai
桜井　潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56152681A priority Critical patent/JPS5853824A/en
Publication of JPS5853824A publication Critical patent/JPS5853824A/en
Publication of JPH0335821B2 publication Critical patent/JPH0335821B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To eliminate exfoliations of and SiO2 layer and an Si layer to be single-crystallized, by forming the deposit of the SiO2 layer and Si layer in a sputtering at 500 deg.C or less, when the SiO2 layer is produced on an Si substrate, the polycrystalline or amorphous Si layer is deposited thereon and covered with the SiO2 layer, and the Si layer is single crystallized by scanning a laser beam. CONSTITUTION:When forming an SiO2 layer 2 on an Si substrate 1, a magnetron sputtering is performed at a low temperature at 500 deg.C or less for preferably at 100 deg.C or less resulting in the thickness of 0.6-1mum at a growing speed of 100- 200Angstrom /min. Next, also when the polycrystalline or amorphous Si layer 3 is deposited thereon, it is formed to the thickness of 0.5mum at the same temperature and growing speed and in the same means, the entire surface is covered with the SiO2 cap layer 4, the laser beam 5 is irradiated in the direction of the arrow mark A resulting in the fusion of the layer 3 and the single crystallization. Thus, exfoliations of layers 2 and 3 are eliminated, and the thermal damage provided to the device is reduced.

Description

【発明の詳細な説明】 本発、明祉半導体装置の製造方法に係シ、特にレーザア
ニーリングされる非晶質又は多結晶シリコン基板の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a Meishi semiconductor device, and more particularly to a method of manufacturing an amorphous or polycrystalline silicon substrate subjected to laser annealing.

従来からシリコン（１００）基板上に０．２５μｍ程度
の熱配化膜、即ち絶縁層をウニｙ　ｌ”　０２　＊１０
００℃４０分で形成し９、更にその上にＣＶＤ法（５Ｉ
Ｈ４：　８３０℃）尋によって多結晶シリコン層を形成
してレーずビームを照射する仁とで多結晶シリコン層を
単結晶化するレーデアニーリング方法が知られている。Conventionally, a thermal alignment film of about 0.25 μm, that is, an insulating layer, has been deposited on a silicon (100) substrate.
Formed at 00°C for 40 minutes 9, and then CVD method (5I)
A laser annealing method is known in which a polycrystalline silicon layer is formed at a temperature of 830° C. and then a laser beam is irradiated to convert the polycrystalline silicon layer into a single crystal.

更にシリコン基板上Ｋ　Ｏ，６−１μ厚の熱酸化膜を形
成し、諌熱酸化膜上にＣＶＤ法により多結晶シリボン層
を０．１〜０．５μ積層し、該多結晶シリコン層をキャ
ブとして熱酸化（〜１００１）するか、８１．Ｎ４（ｚ
　ＯＯＸ　）層ヲ設ケル！　５にすＬ、このように積層
した半導体基板上にレーザを照射して多結晶シリコン層
を単結晶化するレーデアニーリング方法も知られている
・ これらレーずアニールによって多結晶シリコン層を単結
晶化する際に多結晶シリコン層が酸化膜から剥離し５て
しまう弊害を生じる。この原因については熱酸化膜と多
結晶シリコン又は非晶質シリコン層との熱膨張率の違い
によりてストレスが掛った状態でＣＶＤ法等で積層され
た層にレーザエネルギを与えて多結晶又は非晶質シリコ
ン層を融解状態とした時にストレスが元に戻るヒとによ
りて生じるものと説明されている。Furthermore, a thermal oxide film with a thickness of 6-1 μm is formed on the silicon substrate, a polycrystalline silicon layer of 0.1 to 0.5 μm is laminated on the thermal oxide film by CVD, and the polycrystalline silicon layer is deposited in a cap. thermal oxidation (~1001) as 81. N4(z
OOX) Set up the layer! 5. A laser annealing method is also known in which a laser is irradiated onto the semiconductor substrates laminated in this way to convert the polycrystalline silicon layer into a single crystal.These laser annealing processes convert the polycrystalline silicon layer into a single crystal. When oxidizing, the polycrystalline silicon layer peels off from the oxide film, causing a problem. The cause of this is that laser energy is applied to the layers stacked by CVD method etc. under stress due to the difference in thermal expansion coefficient between the thermal oxide film and the polycrystalline or amorphous silicon layer. It is explained that this is caused by the stress returning to its original state when the crystalline silicon layer is brought into a molten state.

本発明は上述のような欠点を除去した半導体基板の製造
方法を提供するものであシ、その特徴とするところは基
板上に形成する絶縁層、即ち熱酸化膜と骸熱酸化膜上に
積層する多結晶シリコン層又は非晶質シリコン層をスパ
ッタリングによル少なくとも５００℃以下の低温で堆積
させるようにした半導体基板の製造方法を提供するもの
で、このよう表刃法で得られた半導体基板はレーデアニ
ールに於て酸化膜より非晶質又は多結晶シリコン層が剥
離しない基板を得ることができるものである。The present invention provides a method for manufacturing a semiconductor substrate that eliminates the above-mentioned drawbacks, and its feature is that the insulating layer formed on the substrate, that is, the thermal oxide film and the thermal oxide film laminated on the The present invention provides a method for manufacturing a semiconductor substrate in which a polycrystalline silicon layer or an amorphous silicon layer is deposited by sputtering at a low temperature of at least 500° C. It is possible to obtain a substrate in which the amorphous or polycrystalline silicon layer does not peel off from the oxide film during radar annealing.

以下、本発明の１実施例を図面について一詳記する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第１図はシリコンウェハー基板１としてＰＷ（１００）
シリコンを選択し、該基板１上に絶縁層２として二酸化
シリコン（８１０，）を！ダネト四ンスノや、タリング
によって低温５００℃以下（好ましくは１００℃以下）
で０．６〜１μを成長速度１００〜２００Ｘ／分　で形
成する。更に咳絶縁層２上に同じく非晶質シリコン層３
を形成する。該非晶質シリコン層はアモルファスシリコ
ンを選択し、０．５声厚程度に低温の好ましくは１００
℃以下でマグネトロンスパッタリングされ、成長速度も
絶縁層と同様の１００〜２００１／ｗｉｎ　　に選択す
る。Figure 1 shows PW (100) as silicon wafer substrate 1.
Select silicon and apply silicon dioxide (810,) on the substrate 1 as the insulating layer 2! Low temperature below 500℃ (preferably below 100℃) due to drying and taring
0.6 to 1 μm is formed at a growth rate of 100 to 200×/min. Furthermore, an amorphous silicon layer 3 is also formed on the cough insulation layer 2.
form. The amorphous silicon layer is selected from amorphous silicon, and is heated at a low temperature of about 0.5 mm thick, preferably 100 mm thick.
Magnetron sputtering is performed at a temperature below .degree. C., and the growth rate is selected to be 100 to 2001/win, which is the same as that for the insulating layer.

上記実施例では非晶質シリコン層を選んだがこれは多結
晶シリコン層３でありてもよく、この場合も非晶質シリ
コン層と同様に低温のスパッタリングで積層させること
ができる。In the above embodiment, an amorphous silicon layer is selected, but this may also be a polycrystalline silicon layer 3, and in this case as well, it can be laminated by low-temperature sputtering like the amorphous silicon layer.

尚、上記非晶質シリコン層又社多結晶シリコン層３上に
必要に応じてキャブ用の絶縁層４として二酸化シリコン
層（ＳｔＯ，）を上述の絶縁層２と同様に形成すること
もできる。Incidentally, a silicon dioxide layer (StO,) may be formed as an insulating layer 4 for a cab on the amorphous silicon layer or polycrystalline silicon layer 3, if necessary, in the same manner as the insulating layer 2 described above.

上述のように構成した半導体基板上にｅｖレーデ５等を
照射して入方向に走査すれば非晶質シリコン層又は多結
晶シリコン層は融解して単結晶化がなされる。こうして
得られた半導体基板では全層２．３（又は４）が低温の
マグネトロンスパッタリングで形成される丸めにレーデ
照射時に絶縁層２から単結晶化し九シリコンが剥離する
仁とがなくなることを確認した。When the EV radar 5 or the like is irradiated onto the semiconductor substrate configured as described above and scanned in the incoming direction, the amorphous silicon layer or polycrystalline silicon layer is melted and made into a single crystal. In the semiconductor substrate thus obtained, all layers 2.3 (or 4) were formed by low-temperature magnetron sputtering, and during radar irradiation, the insulating layer 2 became single crystallized, and it was confirmed that there was no layer 2.3 (or 4) in which the silicon was peeled off. .

第２図は本発明の他の実施例を示すものであシ、第１図
で示したレーデアニーリングによって多結晶シリコン層
又は非晶質シリコン層３を単結晶化した単結晶化層６に
ダイオード、トランジスタ、コンデンサ岬のディバイス
の上方に層間絶縁として二酸化シリコン（８１０，）　
＃の絶縁層７を低温スパッタリングによって形成し、更
に該絶縁層γ上に非晶質又は多結晶シリコン層８を同じ
く低温スパッタリングによって第１図と同様に成長速度
１００〜２００　Ｘ／ｗｉｎ程度で成長させる。９は必
要に応じて形成されるキャブ用絶縁層でお−り、同じく
低温スパッタリングで形成する。FIG. 2 shows another embodiment of the present invention, in which a polycrystalline silicon layer or an amorphous silicon layer 3 is formed into a single crystallized layer 6 by the radar annealing shown in FIG. Silicon dioxide (810,) as interlayer insulation above the devices of diodes, transistors and capacitors
An insulating layer 7 of # is formed by low-temperature sputtering, and an amorphous or polycrystalline silicon layer 8 is grown on the insulating layer γ by low-temperature sputtering at a growth rate of about 100 to 200 X/win in the same manner as in FIG. let Reference numeral 9 denotes an insulating layer for the cab, which is formed as required, and is also formed by low-temperature sputtering.

次に同じ様にレーザ５を照射して多結晶シリコン層又は
非晶質シリコン層８を単結晶化し、更に該単結晶化した
シリコン層に２層目のディバイスを形成し、同じ様な工
程で３層目、４層目、・・・・・・の絶縁層、非晶質（
多結晶）シリコン層等の層を形成することで多層Ｌ８Ｉ
を構成することができる。Next, the polycrystalline silicon layer or the amorphous silicon layer 8 is made into a single crystal by irradiating the laser 5 in the same way, and a second layer device is formed on the single crystal silicon layer, and the same process is performed. 3rd layer, 4th layer, etc. insulating layer, amorphous (
Multilayer L8I by forming a layer such as a polycrystalline silicon layer
can be configured.

第２図で示す多層ＬＳＩ構成の場合には従来の構成のよ
うに、各層をＣＶＯ法や熱酸化表どで高温処理しない九
めに多層ＬＳＩに必要な低温グロセスをそのまま利用で
きるものである。In the case of the multilayer LSI structure shown in FIG. 2, unlike the conventional structure, each layer is not subjected to high-temperature treatment by CVO method or thermal oxidation process, and the low-temperature process necessary for the multilayer LSI can be used as is.

本発明は上述のように構成したので絶縁層と多結晶シリ
コン層又は非晶質シリコン層とがレーデアニーリングに
於て剥離しないだけでなく、多層ＬＳＩ化が極めてスム
ー／に行なえ、２回、３回の熱処理によっても低温で絶
縁層中非晶質又は多結晶シリコン層が形成される丸めに
一層目のデバイス等に与える熱的ダメージを低減できる
利点を有するものである。Since the present invention is configured as described above, not only the insulating layer and the polycrystalline silicon layer or the amorphous silicon layer do not peel off during radar annealing, but also multilayer LSI can be formed extremely smoothly. Even by performing the heat treatment three times, it is possible to reduce the thermal damage caused to the first layer device, etc., by forming the amorphous or polycrystalline silicon layer in the insulating layer at a low temperature.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の半導体基板の側断爾図、第２図は本発
明の半導体基板を用いて多層Ｌ８Ｉを作る工程を説明す
るための半導体装置の側断面図である。 １・・・シリコン基板、２　、７−・・絶縁層（！１ｉ
０２）、３．８・・・多結晶又は非晶質シリコン層、４
，９・・・キャブ用絶縁層（ｇｔｏ、）、５・・・レー
ザビーム、ｌＯ・・・デバイス。 第１図 第２図FIG. 1 is a side sectional view of a semiconductor substrate of the present invention, and FIG. 2 is a side sectional view of a semiconductor device for explaining the process of manufacturing a multilayer L8I using the semiconductor substrate of the present invention. 1... Silicon substrate, 2, 7-... Insulating layer (!1i
02), 3.8... Polycrystalline or amorphous silicon layer, 4
, 9... Insulating layer for cab (GTO,), 5... Laser beam, lO... Device. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 絶縁物層上に成長し九非単結晶半導体層にエネルギー線
を照射して単結晶化する半導体装置の製造方法において
、骸絶縁物層および骸非単結晶層をスノ母ツタリングに
よ、！＋５００℃以下の低温で形成することを特徴とす
る半導体装置の製造方法。In a method for manufacturing a semiconductor device in which a non-single crystal semiconductor layer grown on an insulating layer is made into a single crystal by irradiating the non-single crystal semiconductor layer with energy rays, the insulator layer and the non-single crystal layer are grown by snow-buttering. A method for manufacturing a semiconductor device, characterized in that it is formed at a low temperature of +500°C or lower.
JP56152681A 1981-09-26 1981-09-26 Manufacture of semiconductor device Granted JPS5853824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56152681A JPS5853824A (en) 1981-09-26 1981-09-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56152681A JPS5853824A (en) 1981-09-26 1981-09-26 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5853824A true JPS5853824A (en) 1983-03-30
JPH0335821B2 JPH0335821B2 (en) 1991-05-29

Family

ID=15545783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56152681A Granted JPS5853824A (en) 1981-09-26 1981-09-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5853824A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167352A (en) * 1984-02-09 1985-08-30 Agency Of Ind Science & Technol Semiconductor element
US5123975A (en) * 1989-03-28 1992-06-23 Ricoh Company, Ltd. Single crystal silicon substrate
EP0633604A1 (en) * 1993-07-06 1995-01-11 Corning Incorporated Method of crystallizing amorphous silicon and device obtained by using this method
US5985700A (en) * 1996-11-26 1999-11-16 Corning Incorporated TFT fabrication on leached glass surface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167352A (en) * 1984-02-09 1985-08-30 Agency Of Ind Science & Technol Semiconductor element
US5123975A (en) * 1989-03-28 1992-06-23 Ricoh Company, Ltd. Single crystal silicon substrate
EP0633604A1 (en) * 1993-07-06 1995-01-11 Corning Incorporated Method of crystallizing amorphous silicon and device obtained by using this method
US5985700A (en) * 1996-11-26 1999-11-16 Corning Incorporated TFT fabrication on leached glass surface

Also Published As

Publication number Publication date
JPH0335821B2 (en) 1991-05-29

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