JPH0799742B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0799742B2
JPH0799742B2 JP61034722A JP3472286A JPH0799742B2 JP H0799742 B2 JPH0799742 B2 JP H0799742B2 JP 61034722 A JP61034722 A JP 61034722A JP 3472286 A JP3472286 A JP 3472286A JP H0799742 B2 JPH0799742 B2 JP H0799742B2
Authority
JP
Japan
Prior art keywords
semiconductor
opening
substrate
oxide film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61034722A
Other languages
Japanese (ja)
Other versions
JPS62193128A (en
Inventor
隆 野口
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61034722A priority Critical patent/JPH0799742B2/en
Publication of JPS62193128A publication Critical patent/JPS62193128A/en
Publication of JPH0799742B2 publication Critical patent/JPH0799742B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自然酸化膜を低温で容易に除去する方法に関す
るもので、特に三次元回路素子を実現するための固相エ
ピタキシープロセスへの応用に好適である。
TECHNICAL FIELD The present invention relates to a method for easily removing a natural oxide film at a low temperature, and particularly to an application to a solid phase epitaxy process for realizing a three-dimensional circuit device. It is suitable.

〔発明の概要〕[Outline of Invention]

本発明は、半導体基板上に設けられた非結晶又は多結晶
シリコンを基板の一部を種にして単結晶化する固相エピ
タキシー法において、シリコンを堆積するに先立ち、還
元性の雰囲気中で半導体基板に短波長のエネルギー線を
照射することにより、低温で他の領域にダメージを与え
ることなく基板表面の自然酸化膜を除去す、引き続くエ
ピタキシーを可能にするものである。
The present invention relates to a solid phase epitaxy method in which amorphous or polycrystalline silicon provided on a semiconductor substrate is single-crystallized by using a part of the substrate as a seed, and prior to depositing silicon, the semiconductor is placed in a reducing atmosphere. By irradiating the substrate with energy rays of short wavelength, the natural oxide film on the surface of the substrate is removed at low temperature without damaging other regions, which enables subsequent epitaxy.

〔従来の技術〕[Conventional technology]

三次元回路素子を実現するためには、半導体層を多層に
積層する過程でオートドーピングや固相拡散の影響を最
小限に抑える低温プロセスが必要になる。従来から提案
されている種々の方法の中に固相エピタキシー法があ
る。これは、半導体基板の表面の一部を開口して下地結
晶表面を露出させておき、この上に非結晶又は多結晶シ
リコン膜を堆積した後に開口部の下地結晶を種として固
相エピタキシーを起こさせることにより、全体を単結晶
化する技術である。550℃〜650℃の低温処理で単結晶が
得られるので、三次元回路素子の製造に有効な手段とい
われている。
In order to realize a three-dimensional circuit device, a low temperature process that minimizes the effects of autodoping and solid phase diffusion is required in the process of stacking semiconductor layers in multiple layers. Among various methods that have been proposed in the past, there is a solid phase epitaxy method. This is because a part of the surface of the semiconductor substrate is opened to expose the surface of the underlying crystal, and a non-crystalline or polycrystalline silicon film is deposited thereon, and then solid phase epitaxy is performed using the underlying crystal of the opening as a seed. This is a technique for making the whole into a single crystal. Since a single crystal can be obtained by low-temperature treatment at 550 ° C to 650 ° C, it is said to be an effective means for manufacturing a three-dimensional circuit element.

ところで固相エピタキシーを行う場合、通常、開口部を
設けたときに開口部の表面にできる薄い自然酸化膜を除
去することが必要になる。自然酸化膜が存在すると、多
結晶シリコンと基板開口部との接触状態が悪くなり、エ
ピタキシーの進行を阻害するからである。
When performing solid phase epitaxy, it is usually necessary to remove a thin native oxide film formed on the surface of the opening when the opening is formed. This is because the presence of the natural oxide film deteriorates the contact state between the polycrystalline silicon and the substrate opening and hinders the progress of epitaxy.

従来、この自然酸化膜を除去するために、非結晶又は多
結晶シリコンを堆積した後、約1000℃に昇温してH2雰囲
気中でアニーリングを行うことや、シリコンの堆積前に
表面をArスパッタで洗浄すること(例えば日経マイクロ
デバイセス 1985年10月号P79〜87)、あるいは水素プ
ラズマ中でエッチングすることなどが行われれていた。
またMBE装置を用いる場合は、シリコンの堆積前にH2
囲気中で600℃程度のベーキングを行うことによって自
然酸化膜を除去していた。
Conventionally, in order to remove this natural oxide film, after depositing amorphous or polycrystalline silicon, the temperature is raised to about 1000 ° C. and annealing is performed in an H 2 atmosphere. Cleaning by sputtering (for example, Nikkei Micro Devices, October 1985, P79-87) or etching in hydrogen plasma has been performed.
When using the MBE apparatus, the natural oxide film was removed by baking at about 600 ° C. in an H 2 atmosphere before depositing silicon.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、これらの方法は、高温処理時に不純物の
再拡散を引き起こしたり、スパッタあるいはプラズマエ
ッチング時のイオンによる衝撃で基板や素子領域がダメ
ージを受けるという問題があった。更にMBE装置の場合
には装置自体高価であって量産に向かないと言う問題も
あった。
However, these methods have problems that they cause re-diffusion of impurities during high-temperature processing and that the substrate and element regions are damaged by the impact of ions during sputtering or plasma etching. Further, in the case of the MBE device, there is a problem that the device itself is expensive and is not suitable for mass production.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、非結晶シリコンや多結晶シリコンを堆積する
に先立って、還元性の雰囲気中でエキシマレーザ等によ
り半導体基板に短波長のエネルギー線のパルスを照射す
ることにより、低温で他の領域にダメージを与えること
なく、簡単に基板表面の自然酸化膜を取り除くようにし
たものである。
The present invention irradiates a pulse of a short wavelength energy ray on a semiconductor substrate by an excimer laser or the like in a reducing atmosphere prior to depositing amorphous silicon or polycrystalline silicon, so that other regions can be irradiated at low temperature. The natural oxide film on the substrate surface is easily removed without damage.

〔作用〕[Action]

半導体基板に短波長のエネルギー線のパルスが照射され
ると、基板表面の自然酸化膜のみが瞬時に加熱され、他
の領域に熱的な影響を与えることなく自然酸化膜が除去
される。
When the semiconductor substrate is irradiated with a pulse of a short-wavelength energy ray, only the natural oxide film on the substrate surface is instantly heated, and the natural oxide film is removed without thermally affecting other regions.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例について説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の概念を示す。第1図Aに示すように、
単結晶シリコン基板(1)上に絶縁膜(2)に開口部を
設けた試料を洗浄した後には、開口部表面に10Å程度の
薄い自然酸化膜(3)がついた状態になる。次に試料を
CVD装置等、これから非結晶又は多結晶シリコンを堆積
させようとする装置内に導入し、数百Torrの水素雰囲気
にさらす。
FIG. 1 shows the concept of the present invention. As shown in FIG. 1A,
After the sample having the opening formed in the insulating film (2) on the single crystal silicon substrate (1) is washed, a thin natural oxide film (3) of about 10 Å is attached to the surface of the opening. Then the sample
It is introduced into a device such as a CVD device where amorphous or polycrystalline silicon is to be deposited, and exposed to a hydrogen atmosphere of several hundred Torr.

次に水素雰囲気中で基板(1)表面に、短波長(λ<33
0nm)かつ短時間(τ<10-6sec)の均一なエネルギー分
布をもつ光ビームパルス(4)を照射する。このようす
ると開口部のごく表面付近(<1000Å)の部分のみが加
熱され、自然酸化膜(3)は下地のシリコンを損傷する
ことなく除去される。
Next, a short wavelength (λ <33
A light beam pulse (4) having a uniform energy distribution (0 nm) and a short time (τ <10 −6 sec) is irradiated. In this way, only the portion of the opening near the surface (<1000Å) is heated, and the native oxide film (3) is removed without damaging the underlying silicon.

続いて基板(1)上に非結晶又は多結晶シリコン膜
(5)を同装置内で堆積させる(<650℃)。必要に応
じてSi+イオンを注入してアモルファス化処理を行う
(第1図B)。
Subsequently, an amorphous or polycrystalline silicon film (5) is deposited on the substrate (1) in the same device (<650 ° C.). Amorphization is performed by implanting Si + ions as needed (FIG. 1B).

その後、炉加熱やレーザ光照射によりアニーリング(<
650℃)すると開口部から固相エピタキシーが進行し、
非結晶又は多結晶シリコン膜(5)全体が単結晶化して
単結晶層(6)が得られる。(第1図C)。
After that, annealing (<<
650 ° C), solid phase epitaxy proceeds from the opening,
The entire amorphous or polycrystalline silicon film (5) is single crystallized to obtain a single crystal layer (6). (FIG. 1C).

第2図は本発明の方法を三次元回路素子の製造に応用し
た実施例である。この例ではMOSトランジスタで回路を
構成したが、他にバイポーラトランジスタ等によるバリ
エイションも考えられる。
FIG. 2 shows an embodiment in which the method of the present invention is applied to the manufacture of a three-dimensional circuit device. In this example, the circuit is composed of MOS transistors, but other variations such as bipolar transistors may be considered.

まず、第2図Aのように、シリコン基板(1)上に通常
の方法で第1のMOSトランジスタ(7)を設けた後、フ
ィールド酸化膜(2)の適当な箇所に開口(8)を形成
する。続いて第2図Bのように、基板表面全面に層間絶
縁膜となる厚い絶縁膜(9)を設ける。この絶縁膜
(9)は表面の凹凸を補正し、表面を平坦化して上部層
の形成に備える機能も有している。
First, as shown in FIG. 2A, after the first MOS transistor (7) is provided on the silicon substrate (1) by a usual method, an opening (8) is formed at an appropriate position of the field oxide film (2). Form. Subsequently, as shown in FIG. 2B, a thick insulating film (9) serving as an interlayer insulating film is provided on the entire surface of the substrate. This insulating film (9) also has a function of correcting irregularities on the surface and flattening the surface to prepare for formation of the upper layer.

次に先に設けた開口(8)上の絶縁膜を除去し、基板面
を露出させる。洗浄処理を施した後は、第1図Bと同
様、開口(8)の表面は自然酸化膜(3)で覆われた状
態となる(第2図C)。
Next, the insulating film on the opening (8) provided previously is removed to expose the substrate surface. After the cleaning process, the surface of the opening (8) is covered with the natural oxide film (3) as in FIG. 1B (FIG. 2C).

ここで先の例と同様の条件下で短波長の光ビームパルス
(4)を照射し、自然酸化膜(3)を除去する。続いて
非結晶又は多結晶シリコン層(5)を堆積させ(第2図
D)、低温アニーリングを施せば、固相エピタキシーが
進行して単結晶の上層(6)が得られる(第2図E)。
Here, a light beam pulse (4) having a short wavelength is irradiated under the same conditions as in the previous example to remove the native oxide film (3). Subsequently, an amorphous or polycrystalline silicon layer (5) is deposited (FIG. 2D) and subjected to low temperature annealing, solid phase epitaxy proceeds to obtain a single crystal upper layer (6) (FIG. 2E). ).

この後通常の方法を用いて上層(6)に第2のMOSトラ
ンジスタ(10)を形成すると、二重構造の三次元回路素
子を構成することができる(第2図F)。
Thereafter, a second MOS transistor (10) is formed on the upper layer (6) by a usual method, whereby a three-dimensional circuit element having a double structure can be constructed (FIG. 2F).

〔発明の効果〕〔The invention's effect〕

上述のごとく、本発明によれば、還元性雰囲気中で短波
長のパルス光を照射することにより、下地層にダメージ
を与えることなく、低温(<600℃)で効果的に開口部
の自然酸化膜を除去することができる。この方法を用い
ると、基板や下地層の素子領域への影響が最小限に抑え
られるため、素子の形成された半導体層を積層するプロ
セスが必要な三次元回路素子の製造に好適である。更に
装置自体も従来のCVD装置などの通常使われている装置
にエネルギー線を導入するための窓を設けるだけで良
く、むずかしい作業を必要としないので、従来装置との
インターフェースが容易であるという利点もある。
As described above, according to the present invention, by irradiating short-wavelength pulsed light in a reducing atmosphere, the natural oxidation of the opening can be effectively performed at low temperature (<600 ° C.) without damaging the underlayer. The film can be removed. When this method is used, the influence of the substrate and the underlying layer on the element region is suppressed to a minimum, and therefore it is suitable for manufacturing a three-dimensional circuit element that requires a process of stacking semiconductor layers on which elements are formed. Furthermore, the device itself only needs to be provided with a window for introducing energy rays into a conventionally used device such as a conventional CVD device, and since it does not require difficult work, it has the advantage of being easy to interface with the conventional device. There is also.

【図面の簡単な説明】 第1図A〜Cは本発明の方法の概念を示す断面図、第2
図A〜Fは本発明の方法による三次元回路素子の製造の
実施例を示す工程準の断面図である。 (1)はシリコン基板、(2)はフィールド酸化膜、
(3)は自然酸化膜、(4)はエネルギービーム、
(5)はポリシリコン層、(6)は単結晶層、(7)は
第1MOSトランジスタ、(8)は開口部、(9)は層間絶
縁膜、(10)は第2のMOSトランジスタ、(11)はフィ
ールド酸化膜。
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are sectional views showing the concept of the method of the present invention, and FIG.
FIGS. 7A to 7F are sectional views of process steps showing an example of manufacturing a three-dimensional circuit device according to the method of the present invention. (1) is a silicon substrate, (2) is a field oxide film,
(3) is a natural oxide film, (4) is an energy beam,
(5) is a polysilicon layer, (6) is a single crystal layer, (7) is a first MOS transistor, (8) is an opening portion, (9) is an interlayer insulating film, (10) is a second MOS transistor, ( 11) is a field oxide film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成した半導体素子と上記
半導体基板上を覆って形成された絶縁層の上記半導体基
板上に形成された開口部を介して、上記絶縁層上に半導
体層を形成する半導体装置の製造方法において、上記開
口部を形成した後、非結晶又は多結晶半導体を堆積させ
ようとする装置内に導入し、上記開口部を露出した上記
半導体基板表面に減圧還元性雰囲気中で短波長のエネル
ギー線のパルスを照射して上記半導体基板表面をエッチ
ングし、続いて650℃以下で非結晶又は多結晶半導体を
堆積するようにしたことを特徴とする半導体装置の製造
方法。
1. A semiconductor layer is formed on the insulating layer through a semiconductor element formed on the semiconductor substrate and an opening formed on the semiconductor substrate in an insulating layer formed to cover the semiconductor substrate. In the method for manufacturing a semiconductor device according to claim 1, after forming the opening, the amorphous or polycrystalline semiconductor is introduced into a device to be deposited, and the opening is exposed in a reduced pressure reducing atmosphere on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the surface of the semiconductor substrate is etched by irradiating a pulse of an energy ray having a short wavelength, and then an amorphous or polycrystalline semiconductor is deposited at 650 ° C. or lower.
JP61034722A 1986-02-19 1986-02-19 Method for manufacturing semiconductor device Expired - Lifetime JPH0799742B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61034722A JPH0799742B2 (en) 1986-02-19 1986-02-19 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61034722A JPH0799742B2 (en) 1986-02-19 1986-02-19 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62193128A JPS62193128A (en) 1987-08-25
JPH0799742B2 true JPH0799742B2 (en) 1995-10-25

Family

ID=12422217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61034722A Expired - Lifetime JPH0799742B2 (en) 1986-02-19 1986-02-19 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0799742B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810669B2 (en) * 1986-04-11 1996-01-31 日本電気株式会社 Method of forming SOI film
JPH0682643B2 (en) * 1987-03-13 1994-10-19 科学技術庁長官官房会計課長 Surface treatment method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016416A (en) * 1983-07-08 1985-01-28 Hitachi Ltd Vapor growth apparatus
JPS6085515A (en) * 1983-10-17 1985-05-15 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS62193128A (en) 1987-08-25

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