JP2718450B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a wiring formed inside a semiconductor device.

(Prior Art) A method of manufacturing a semiconductor device according to the prior art, particularly a method of manufacturing a wiring portion, will be described below with reference to FIG. Tenth
1A and 1B are cross-sectional views showing a method of manufacturing a wiring according to a conventional technique in the order of steps.

Diffusion layer 110 and diffusion layer 11 formed on the surface of semiconductor substrate 104
When 1 is connected by wiring, first, an insulating layer 102 having an opening is formed on the diffusion layer 110 and the diffusion layer 111 by a photolithography technique or the like.

(FIG. 10 (a)) Next, a wiring material 101 such as aluminum is deposited on the entire surface of the opening and the insulating layer 102 by a sputtering method or the like, and then unnecessary portions of the wiring material 101 are removed by etching. Thus, the wiring was formed. (FIG. 10 (b)) Next, referring to FIG. 11, a method of manufacturing a semiconductor device according to the prior art, in particular, a method of manufacturing a multilayer wiring portion will be described.
FIGS. 11 (a) and 11 (b) are cross-sectional views showing a method of manufacturing a multilayer wiring in the case where wiring is further superposed on the upper part of FIG. 10 (b) in the order of steps. The numbers shown in the drawing of FIG. 11 correspond to those of FIG.

When a wiring is to be formed in the region 115 on the wiring 101, an insulating layer 112 having an opening is formed on the region 115 by a photolithography technique or the like. (FIG. 11 (a)) Next, a wiring material 114 such as aluminum is deposited on the entire surface of the opening and the insulating layer 112 by a sputtering method or the like.
Subsequently, an unnecessary portion of the wiring material 114 is removed by etching. (FIG. 11 (b)) (Problem to be Solved by the Invention) In the above-described method for forming a wiring in a semiconductor device, when the degree of integration of the semiconductor device is improved and one side D of the opening in the diffusion layers 110 and 111 is reduced. The ratio of the thickness t of the insulating layer 102 to one side D of the opening 105, that is, the aspect ratio, increases.
When the aspect ratio increases, it becomes difficult to obtain a good wiring material on the side surface of the opening of the insulating layer 102, as shown at 109 in FIG. 10 (b). Met.

Also, PEP process (Photo Engraving P
In the process of exposure, unnecessary electromagnetic waves are emitted to the wiring resist pattern due to reflection from the wiring material or the like at the stepped portion due to the unevenness under the resist film when exposed to electromagnetic waves such as ultraviolet rays after forming the resist film. . As a result, when the resist is a positive resist, a portion of the developed resist pattern irradiated with unnecessary electromagnetic waves is lost.
If the wiring material is etched using this resist pattern as a mask, the wiring becomes infested. In the case of a negative resist, an unexpected wiring pattern is formed in a portion of the developed resist pattern where unnecessary electromagnetic waves are irradiated. Such a state leads to a defect and a decrease in reliability, and it can be seen that the deterioration of flatness due to the improvement of the integration degree is also a problem here.

Further, when a wiring layer is formed in an upper layer portion in a multilayer wiring, as shown in FIG. 11, an upper wiring 114 and a lower wiring 101 are formed.
It is necessary to form the insulating layer 112 between them. However, in the conventional method, since the lower wiring 101 is not formed flat, the insulating layer 1
There is a step between the upper surface of the lower wiring 101 formed on 02 and the upper surface of the lower wiring 101 formed on the diffusion layer 110. Due to this step, when the insulating layer 112 is formed, cavities as shown in 113 are easily formed, and the wiring is eroded by a cleaning solution or the like when cleaning the semiconductor substrate that has penetrated there, and wiring defects are liable to occur.

As described above, in the wiring process in the conventional method of manufacturing a semiconductor device, it is difficult to obtain a good deposition of a wiring material due to the deterioration of flatness due to the improvement in the degree of integration. The wiring becomes buggy or an unexpected wiring pattern is formed. Further, even in the case of a multilayer wiring, since the lower wiring is not formed flat, there is a problem that a cavity is easily formed in an insulating layer formed between the lower wiring and the upper wiring.

The present invention improves the reliability of a semiconductor device by improving the problem of the deterioration of the flatness of the wiring layer caused by the improvement in the degree of integration, which is observed in the above-mentioned conventional method for manufacturing a semiconductor device. It is an object of the present invention to provide a method for producing the same.

[Constitution of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a step of forming a seed plate having electrical conductivity on a wiring scheduled region on a semiconductor substrate, Growing a wiring layer from a seed plate.

(Operation) According to such a manufacturing method, a seed plate having electrical conductivity is selectively formed, and the seed plate is grown and a wiring layer is formed, so that a wiring having flatness is formed in a predetermined wiring region. It is possible to obtain a layer.

Embodiment A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.

1A to 1H are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

First, a P-type semiconductor substrate 10 having two diffusion layers 11 and 12 formed on the surface via an insulating layer 13 such as a silicon oxide film is prepared. The insulating layer 13 is obtained by selectively oxidizing the P-type semiconductor substrate 10, and the two n-type diffusion layers 11 and 12 are ion-implanted with n-type impurities such as phosphorus and arsenic using the insulating layer 13 as a mask. It is obtained by heat-treating the leverage impurities and electrically activating them. Also, two n-type diffusion layers 11, 12
It is desirable that the impurity concentration on the surface of the substrate be sufficiently high in order to obtain good ohmic contact with a seed plate 14 described later. This is because good ohmic contact can be obtained basically by making the Schottky barrier smaller or thinner by increasing the carrier concentration in the diffusion and conductive layer regions, etc., so that tunneling of carriers is more likely to occur. Therefore n
When forming the type diffusion layers 11 and 12 by the above-described ion implantation method, it is necessary to determine the dose, the acceleration voltage, the ion species, and the heat treatment conditions in consideration of this point. In this embodiment, a wiring for connecting the two n-type diffusion layers 11 and 12 is formed. (FIG. 1A) Subsequently, an aluminum thin film 14 having a thickness of 1000 ° serving as a seed plate is formed on the entire upper surface of the P-type semiconductor substrate 10. The seed plate 14 preferably has good electrical conductivity and can obtain good ohmic contact without reacting with a lower layer (in this case, n-type diffusion layers 11 and 12) when subjected to heat treatment. That is, in the heterojunction region formed by the n-type diffusion layers 11 and 12 and the seed plate 14, it is necessary to prevent the generation of unnecessary electrical barriers other than a thin barrier having a small ohmic contact. Materials other than aluminum satisfying such conditions include, for example, heat resistance,
Refractory metals such as Al-Si, Al-Si-Cu, tungsten, molybdenum, etc., which have excellent reaction resistance; silicides such as titanium and cobalt; nitrides such as tungsten and titanium; A film of polycrystalline silicon or the like doped with an active impurity, or a film in which these films have a multilayer structure. The thickness of the seed plate is determined in consideration of a pattern conversion difference due to processing, a barrier property against a chemical reaction, a stress structure, and the like. Chemical Vap for seed plate formation using chemical reaction to form seed plate
or Deposition (hereinafter referred to as CVD), Metal Organic CVD
(MOCVD), optical CVD, plasma activated CVD (PCVD), magnetron sputtering, a beam method, or the like. (First
(FIG. (B)) The seed plate 14 prepared in this way is used only for selective regions (that is, on the n-type diffusion layers 11 and 12, which are the wiring planned regions, and on the insulating layer 13 between the two diffusion layers). After the resist is selectively exposed to remove the remaining portions, an etching mask pattern 15 developed from the resist is formed.
(FIG. 1 (c)) Using the mask 15 as a mask, a portion of the seed plate 14 other than the wiring area is removed by reactive ion reactive etching or the like. Thereafter, the mask pattern 15 is removed by etching. (FIG. 1 (d)) Next, a silicon oxide film 16 having a thickness of 10000 .ANG. Is formed on the entire surface including the planned wiring region by the CVD method. (FIG. 1 (e)) Subsequently, on the oxide film 16, a resist pattern 17 having an opening in an area where wiring is to be formed is formed. (FIG. 1 (f)) Using this as a mask, on the area to be wired, ie,
The upper silicon oxide film 16 is removed. After that, the resist 17 is removed. (FIG. 1 (g)) Then, using the exposed seed plate 14 as a core, a conductive material is selected.
The wiring layer 18 is formed by growing the oxide film 16 so as to have substantially the same height as the adjacent oxide film 16 by the CVD method. (FIG. 1 (h)) The “substantially the same height” as used herein means not only the same height but also a step break as shown in FIG. 10 (b).
Alternatively, it also includes the degree to which no cavity is formed as shown in FIG. 11 (b).

In addition, in order to form the wiring layer 18 from the seed plate 14, the CVD apparatus shown in FIG. 2 is used. Hereinafter, the CVD apparatus shown in FIG. 2 will be described.

From the input 21, a substrate 25 (substrate up to the step shown in FIG. 1 (g)) in which the seed plate 14 is exposed only in the wiring planned area and the other area is covered with the insulating layer 13 is placed. Next, the substrate 25 is sent to the pre-chamber 22 and subjected to a pretreatment necessary for performing selective growth of the wiring layer, for example, cleaning. Subsequently, the substrate 25 is transferred to the switching room 23, and the subsequent wiring selective growth room 24
The atmosphere and the like are switched. Next, the wiring selection growth room
The substrate 25 is transferred to 24, and a growth raw material gas, for example, an organic tungsten gas, a reducing gas H ₂ , SiH _4, or the like is supplied from the individual inlets 212a to 212z while controlling the pressure, the input / output order, and the like in a time series. A temperature controller 28 controls the temperature of the susceptor 26 also serving as an electric field application electrode. On the other hand, two electrodes 27 connected to a power source 29
An electric field is applied in between, a suitable electromagnetic wave is emitted from the lamp 210 through the window 211, and the temperature cycle of the substrate 25 is controlled by the susceptor 26. With these, the desired metal system, semiconductor system,
Alternatively, these multilayer structures can be selectively grown on the seed plate 14 formed in the wiring planned area.

If such a method of manufacturing a semiconductor device is used,
Is formed in the wiring area, and the wiring layer 18 is formed only on the seed plate 14.
Can be selectively grown. When the wiring layer 18 is selectively grown, the wiring layer 18 can be formed at an arbitrary height by controlling the processing time, each partial pressure of the vapor phase material, the wavelength of the lamp, the intensity, the intensity of the electric field, and the like. . For this reason, by selectively growing the wiring layer 18 to the substantially same height as the adjacent oxide film 16, the flatness is improved and the disconnection state of the wiring layer and the formation of an unscheduled wiring pattern, which were problems of the related art. Is less likely to occur.

FIG. 3 is a sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to the second embodiment of the present invention. The numbers shown in the drawing of FIG. 3 correspond to FIG.

When wiring is further formed on the wiring layer 18 described in the first embodiment, an aluminum thin film 31 serving as a seed plate is formed on the entire surface of the wiring layer 18 and the insulating layer 16. Subsequently, selective processing is performed on the seed plate 31, and the seed plate 31 is left only in the wiring planned area. Next, the insulating layer 32 is formed on the entire surface including the planned wiring region, and the insulating layer 32 on the planned wiring region is removed. Thereafter, using the seed plate 31 as a nucleus, a conductive material is grown to substantially the same height as the adjacent insulating layer 32 to form a wiring layer 33. FIG. 3 shows an example in which up to three wiring layers are formed by repeating the same operation. 34 is a seed plate for forming the third wiring layer, 35
Is an insulating layer that insulates between the third wiring layers, and 36 is a third wiring layer. Similarly, it is also possible to overlap the fourth and fifth layers with the wiring layer.

By using such a manufacturing method, as described in the first embodiment, the flatness of the first-layer wiring is improved, so that the cavity of the insulating layer 32 which has conventionally been caused by the deterioration of the flatness is reduced. Less likely to occur. Even if the wiring layers 33 are stacked, the flatness is not lost as in the first layer.

FIG. 4 is a sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to the third embodiment of the present invention. The numbers shown in the drawing of FIG. 4 correspond to FIG.

In the second embodiment, as the insulating layers and the wiring layers are stacked, a problem of stress migration such as disconnection of the wiring due to the presence of stress applied to the insulating layers and the like occurs. In the third embodiment, in order to reduce such a problem, the insulating layer 41 has a two-layer structure as shown in FIG.
That is, the lower layer 411 is made of a PSG (Phospho-Silicate Glass) film and the upper layer 412 is made of a SiN (silicon nitride) film so that the coefficient of thermal expansion and the reactivity of the material with the wiring are different.
By setting the thickness ratio between the PSG film and the SiN film to an appropriate value, the stress of the entire layer structure is reduced, for example, by applying the stress of SiN and the stress of PSG, thereby suppressing the stress migration. Since this naturally depends on the stress of the wiring layers 18, 33, 36, it depends on the material, structure, forming conditions and the like of the wiring layers 18, 33, 36. Further, in the multilayer wiring structure, “the thickness ratio of the SiN film and the PSG film is changed in each insulating layer 41 (for example, the first layer is the thickness of the SiN film: the thickness of the PSG film = 1: 4, the second layer Means such as “the thickness of the SiN film: the thickness of the PSG film = 3: 2)” and “change the conditions for forming the insulating layer 41 for each layer”. It is also possible to adjust stress by using these means, suppress stress migration, and improve reliability. Alternatively, the stress distribution may be adjusted by making the insulating layer 41 a SiNO (oxynitride) film and changing the composition ratio of x and y for each wiring layer 18, 33, 36 as SiNxOy.

FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.

Although the seed plate 14 is formed after the diffusion layers 11 and 12 are formed in the first to third embodiments, the diffusion layers 11 and 12 are formed by forming the seed plate 14 by, for example, ion implantation. It can also be implemented by the following.

First, an insulating layer 51 such as a silicon oxide film is formed by selectively oxidizing the surface of a P-type semiconductor substrate 50. Then the insulating layer
An aluminum thin film 52 serving as a seed plate is formed on the entire upper surface of a substrate 50 having 51. The conditions and method for forming the seed plate 52 are the same as those in the first embodiment. The seed plate 52 prepared in this manner is removed while leaving the wiring planned area. (FIG. 5 (a)) Next, n-type impurities such as phosphorus and arsenic are ion-implanted into the two n-type diffusion layers 53 and 54 using the insulating layer 51 as a mask, and the impurities are implanted by a rapid thermal annealing method or the like. Al and Si
Is formed by heat treatment and activation in a short time while preventing the above reaction. (FIG. 5 (b)) Thereafter, an insulating layer is formed, and a wiring layer is selectively grown using the seed plate 52 as a nucleus. These steps are the same as in the first embodiment.

If such a method of manufacturing a wiring is used, the diffusion layers 53, 54
And a heat treatment for activating impurities necessary for forming the diffusion layers 53 and 54 can be simultaneously performed. By simultaneously performing the heat treatments required twice, the heat treatment time can be shortened and a diffusion layer having a small depth and a high surface impurity concentration can be obtained, so that the ohmic resistance can be reduced.

6 (a) to 6 (f) are sectional views showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention in the order of steps.

First, a P-type semiconductor substrate 60 having two diffusion layers 61 and 62 formed on the surface thereof via an insulating layer 63 such as a silicon oxide film is prepared. These forming methods are the same as in the first embodiment. In this embodiment, a wiring for connecting the two diffusion layers 61 and 62 is formed. Next, the P-type semiconductor substrate 60
An insulating layer 64 is formed on the entire upper surface of the substrate. For example, a plasma CVD method is used as this forming method, and a silicon oxide film having a thickness of about 12000 is formed. (FIG. 6 (a)) Subsequently, in order to selectively process the formed insulating layer 64, a resist pattern 65 having an opening in a wiring planned area is formed. (FIG. 6 (b)) Using the resist pattern 65 as a mask, the portion of the insulating layer 64 above the wiring region is removed by reactive ion reactive etching or the like. (FIG. 6 (c)) Then, an aluminum thin film 66 serving as a seed plate is placed on the n-type diffusion layer.
It is formed on the entire surface of the insulating layer 63 and the insulating layer 64 between the diffusion layers 61 and 62 and between the two diffusion layers. The forming method and the forming conditions are the same as in the first embodiment. (FIG. 6D) Subsequently, the seed plate 66 is left only on the n-type diffusion layers 61 and 62, which are the planned wiring regions, and on the insulating layer 63 between the two diffusion layers, by using, for example, an etching back method. . (FIG. 6E) Next, using the seed plate 66 as a nucleus, a conductive material is grown to substantially the same height as the insulating layer 64 adjacent to the seed plate 66 to form a wiring layer 67. The selective growth method and growth conditions in this case are the first.
This is the same as the embodiment. (FIG. 6 (f)) When such a manufacturing method is used, the flatness of the semiconductor device is improved as described in the first embodiment, and the disconnection state of the wiring layer, which has been a conventional problem, is improved. Also, it is difficult to form an unexpected wiring pattern. Further, in the first embodiment, a PEP process (Photo Engraving Process) is performed before the wiring is formed, in which the seed plate 14 formed on the entire surface of the substrate 10 is left only in the area where wiring is to be performed (FIG. 1 (c)). The step (FIG. 1 (f)) of forming an opening in the wiring planned area of the oxide film 16 formed on the entire surface of the substrate 10 including the planned area was performed twice. In the fifth embodiment, the two PEP steps are performed only in the step of forming an opening in the wiring planned area of the insulating layer 64 formed on the entire surface of the substrate 60 including the wiring planned area (FIG. 6B). Times. Since the PEP process is performed once, it is possible to simplify the process and eliminate a margin in consideration of a deviation of the mask 15 formed on the seed plate 14 in order to leave the seed plate 14 only in the wiring planned area.

FIG. 7 is a sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. The numbers shown in the drawing of FIG. 7 correspond to FIG.

When an additional wiring layer is formed on the wiring layer 67 described in the fifth embodiment, the insulating layer 71 is formed on the entire surface of the wiring layer 67 and the insulating layer 64. Subsequently, the insulating layer 71 on the wiring planned area is removed. Next, an aluminum thin film 72 serving as a seed plate is placed on the insulating layer 64
It is formed on the entire surface on the insulating layer 71 and on the insulating layer 71. Subsequently, using, for example, an etching back method, the seed plate 72 is left only on the wiring planned area. Thereafter, using the seed plate 72 as a nucleus, a conductive material is grown to substantially the same height as the adjacent insulating layer 71 to form a wiring layer 73. FIG. 7 shows an example in which up to three wiring layers are formed by repeating the same operation. 74 is an insulating layer that insulates between the third wiring layers, 75 is a seed plate for forming the third wiring layer, and 76 is a third wiring layer. Similarly, 4
It is also possible to stack layers, five layers and wiring layers.

If such a manufacturing method is used, cavities of the insulating layer 71 are less likely to occur as described in the second embodiment, and flatness is not lost. Also, as described in the fifth embodiment, PE
Since the number of P steps can be reduced, the steps in the multilayer wiring can be simplified.

8 (a) and 8 (b) are sectional views showing a method of manufacturing a C-MOS inverter circuit according to a seventh embodiment of the present invention in the order of steps. FIG. 8C is a diagram showing a C-MOS circuit according to a seventh embodiment of the present invention.

The seventh embodiment is an example in which the method of manufacturing a semiconductor device according to the present invention is applied to the formation of a C-MOS (complementary MOS) inverter circuit. First, an N-type well 81 is formed by selectively implanting impurities into a P-type Si substrate 80. Thereafter, field oxidation is performed to form a field oxide film 89. Next, an N ⁺ layer 86 serving as a drain electrode and an N ⁺ layer 87 serving as a source electrode are formed by ion implantation. P ⁺ layer 82 serving as a drain electrode
A P ⁺ layer 83 serving as a source electrode is formed in the same manner. Subsequently, a thin oxide film 89 and a polysilicon gate electrode are selectively formed on the gate region (P-type polysilicon 85 for a P-type transistor, N-type polysilicon 88 for an N-type transistor).
To form (FIG. 8A) Next, the source electrode 8 is formed by the method described in the first embodiment.
A seed plate 810 is formed on the drain electrodes 82 and 86, and then the insulating layer 811 is formed to substantially the same height as the gate electrodes 85 and 88. Subsequently, the wiring layer 812 is formed by selectively growing a conductive material to substantially the same height as the gate electrodes 85 and 88 and the insulating layer 811 using the seed plate 810 as a nucleus. This forming method is the same as in the first embodiment. Next, similarly, the seed plate 8 is placed on the insulating layer 811, the wiring layer 812, and the gate electrodes 85 and 88.
Form 13. After that, an insulating layer 818 is formed, and a seed plate 813 is selectively grown to form a wiring layer 814 connecting the drain electrodes 82 and 86. By repeating the same steps, the wiring layer 815 connecting the gate electrodes 85 and 88 is formed.
And a wiring layer for grounding the source electrode 83 of the P-type transistor
A wiring layer 817 connecting the source electrode 816 and the source electrode 87 of the N-type transistor to a power source is formed. (FIG. 8 (b)) A circuit diagram of the C-MOS inverter circuit thus formed is shown in FIG. 8 (c).

When such a manufacturing method is used, the flatness does not deteriorate even when layers are stacked as described in the second embodiment, and the contact coverage is improved as compared with the conventional method.

FIG. 9 is a sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention. The embodiment shown in FIG. 8 is an example in which the method of manufacturing a semiconductor device according to the present invention is applied to TAB (Tape Automated Bonding).

First, a semiconductor substrate 90 having a wiring layer 94 formed in a selective region is prepared. The method of forming the wiring layer 94 is arbitrary. Next, a seed plate 95 is formed on the wiring layer 94. The forming method and the forming conditions are the same as in the first embodiment. Subsequently, an insulating layer 93 is formed on the entire surface of the semiconductor substrate 90 and the seed plate 95, and Bond
The insulating layer 93 in the region to be the ing Pad is removed. Thereafter, using the seed plate 95 in the exposed region as a nucleus, a conductive material is grown to a level higher than the adjacent insulating layer 93 to form a bonding pad 92. The growth method and growth conditions are the same as in the first embodiment.

If such a manufacturing method is used, the mask displacement at the time of forming the wiring layer is eliminated, so that the bonding pad becomes small,
Further, as described in the first embodiment, since the surface flatness is improved, it is suitable for improving the adhesion to the inner lead 91 and for fine processing.

[Effects of the Invention] As described above in detail, according to the present invention, a semiconductor device capable of forming a seed plate having electrical conductivity in a wiring planned region and selectively growing a wiring layer only on the seed plate Can be provided. Therefore, the surface flatness of the semiconductor device is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps, and FIG.
FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps, and FIG. 6 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. FIG. 7 is a sectional view showing a manufacturing method in the order of steps, FIG. 7 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention, and FIGS.
Is a sectional view showing a method of manufacturing a C-MOS circuit according to a seventh embodiment of the present invention in the order of steps, and FIG. 8 (c) shows a C-MOS circuit according to a seventh embodiment of the present invention. Circuit diagram, ninth
FIG. 10 is a sectional view showing a semiconductor device according to an eighth embodiment of the present invention, FIG. 10 is a sectional view showing a method of manufacturing a wiring according to the prior art in the order of steps, and FIG. It is sectional drawing which showed the method in order of process. 10,50,60,80,90,104… Semiconductor substrate 13,16,32,35,41,51,63,64,7,74,89,811,818,93,102,112
… Insulation layer 14,31,34,52,66,72,75,810,813,95… Seed plate 18,33,36,67,73,76,812,814,815,816,817,101,114… Wiring layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Shirai 1 Komagi Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (72) Inventor Yasushi Itabashi Komukai Toshiba-cho 1, Kochi-ku, Kawasaki-shi, Kanagawa (56) References JP-A-63-11668 (JP, A) JP-A-63-176476 (JP, A)

Claims (1)

(57) [Claims] A first insulating layer formed on and adjacent to the first conductive layer; a first insulating layer formed on and adjacent to the first conductive layer; Forming a second insulating layer on the two regions on the semiconductor substrate having a region where a wiring layer is to be formed and a region where a wiring layer is not to be formed; and Removing the second insulating layer formed on the formation planned region; forming an electrically conductive seed plate on the wiring layer formation planned region and on the surface of the second insulating layer; Removing the seed plate on the second insulating layer; and growing a wiring layer connecting the first conductive layer and the second conductive layer from the seed plate to substantially the same height as the second insulating layer. A method for manufacturing a semiconductor device, comprising: