JPS5893223A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

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Publication number
JPS5893223A
JPS5893223A JP56190631A JP19063181A JPS5893223A JP S5893223 A JPS5893223 A JP S5893223A JP 56190631 A JP56190631 A JP 56190631A JP 19063181 A JP19063181 A JP 19063181A JP S5893223 A JPS5893223 A JP S5893223A
Authority
JP
Japan
Prior art keywords
layer
substrate
semiconductor layer
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56190631A
Other languages
Japanese (ja)
Inventor
Kenji Shibata
健二 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56190631A priority Critical patent/JPS5893223A/en
Publication of JPS5893223A publication Critical patent/JPS5893223A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To easily realize three dimensional integration by depositing a semiconductor layer by the vacuum-deposition method on an oxide film of a semiconductor substrate, continuously irradiating energy beams to the desired area of semiconductor layer under the same vacuum condition and single-crystallizing a layer through the annealing under the vacuum condition. CONSTITUTION:An SiO2 film 102 is formed in the specified thickness on the surface of a single crystal Si substrate 101 and an SiN film 103 is then formed over such film 102. The patterning is then carried out to these films 102, 103 by the specified method and these films are partly provided with a window by the etching. Then, such substrate is placed into evaporation apparatus and a polycrystalline silicon layer 104 is vacuum deposited thereon under a pressure of 10<-5>-10<-11> Torr. Moreover, energy beams (e) are irradiated to the desired region of layer 104 under the same vaccum condition during continuous scanning, thereby the layer 104 is annealed and the signale crystallized silicon layer 104' can be formed. In such energy beam irradiation, the substrate is heated up to 200-500 deg.C and a continuous electron beam is accelerated up to 5-30keV under a pressure of 10<-5>-10<-11> Torr, and the scanning rate is set to 0.5-500cm/sec.

Description

【発明の詳細な説明】 発明の属する技術分野 本発明は半導体装置の製造方法に係り、特に絶縁膜上に
単結晶化した半導体１＠を形成する手段を改良した半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a means for forming a single crystal semiconductor 1@ on an insulating film is improved.

従来技術とその問題鑞 周知の妬く、半導体基板上（以下ンリコ／基板を用いる
）に素子を形成する半導体装＋ｔ　Ｉ／Ｃ’Ｆ＋・いて
は、酸化、拡散、イオン注入、写真−刻など公知の技術
を用いて、シリコン基板上に平面的（二次元的）に素子
を配列するが４虜で、ニー以上の多１−に素子を形成す
ることばは吉／１５．どなかった。そのため従来よりも
素子を微細化して、半導体装置を高゛集積化、高速化す
るためには限界があり、この限界を越える手段として、
多層に素子を形成する、いわゆる三次元半導体装置が提
案され、これを実現するために、絶縁膜上の多結晶また
は非晶質半導体＋１１ｉ１にエネルギービームを照射し
て単結晶半導体層（以下シリコン層を用いる）を形成す
る方法が提案されている。例えば、シリコン基板をｓｉ
ｏ＊＊たは８ｉＮ等の絶縁膜でおおってその上に多結晶
シリコン層を被着し、これを連続ビームのレーザー元ま
たは電子線により照射アニールすることにより単結晶７
１Ｊコン層となし、核層中に素子を形成することにより
、三次元半導体装置を製造することができる。しかし、
従来の方法では、直径が加μｍ程度の粗大粒多結晶シリ
コンにしかならず、単結晶シリコンＩ−を得ることはき
わめてむずかしい。また実現した単結晶中には多数の転
位、双晶、積層欠陥、等が含まれ、シリコ／層の結晶性
はきわめて悪いものであった。またそのシリコンｊ−の
表面には、かなり大きな凹凸ができ、そのため該ｌ−中
に素子を叩る際にはリソグラフィーヒ多くの難曳かあり
、出来−ヒがった素子の％性はＳ　ＯＳ（サファイア基
板上のンリコ／Ｉ−）に形成されたものより悪いもので
あった。Prior art and its problems It is well known that semiconductor devices for forming elements on semiconductor substrates (hereinafter referred to as "substrate") include oxidation, diffusion, ion implantation, photo-engraving, etc. Using this technique, devices are arranged planarly (two-dimensionally) on a silicon substrate. What happened? Therefore, there is a limit to miniaturizing elements and increasing the integration and speed of semiconductor devices than before, and as a means to overcome this limit,
A so-called three-dimensional semiconductor device in which elements are formed in multiple layers has been proposed, and in order to realize this, an energy beam is irradiated onto a polycrystalline or amorphous semiconductor +11i1 on an insulating film to form a single crystal semiconductor layer (hereinafter referred to as a silicon layer). A method has been proposed to form a For example, if a silicon substrate is
A single crystal 7
A three-dimensional semiconductor device can be manufactured by forming a 1J conductor layer and forming elements in the core layer. but,
The conventional method produces only coarse-grained polycrystalline silicon with a diameter of about micrometers, and it is extremely difficult to obtain single-crystal silicon I-. Furthermore, the single crystal that was realized contained many dislocations, twins, stacking faults, etc., and the crystallinity of the silicon/layer was extremely poor. In addition, the surface of the silicon J- has quite large irregularities, so when hitting the element during the l-lithography process, there are many difficulties in lithography, and the % of the cracked element is S. It was worse than that formed on OS (Nrico/I- on sapphire substrate).

現在最も有望と考えられている。シリコンｆ−の単結晶
化法はｒ、　ｇ　ｓ　ｓ法である。４１図はこの方法の
概略を示すものである。まず、シリコン基板ｌ上の絶縁
膜２の一部を開孔し、その上に多結晶または非晶質シリ
コン層３を被着したのちエネルギービーム４を照射して
、上記開孔部において下地車結晶シリコン基板との接触
部全種結晶としてエピタキシャル成長させ、引き続き横
方向へ結晶成長させるというものである。この方法の特
徴は基板と同一面万位の単結晶領域を希望する場所に作
り得る薇にあり、この技術をくりかえしてゆけば二次元
半導体装１ｔは可能であると考えられる。currently considered the most promising. The single crystallization method for silicon f- is the r, gss method. Figure 41 shows an outline of this method. First, a hole is made in a part of the insulating film 2 on the silicon substrate 1, a polycrystalline or amorphous silicon layer 3 is deposited thereon, and an energy beam 4 is irradiated to form a base layer in the hole. The entire contact area with the crystalline silicon substrate is epitaxially grown as a seed crystal, and then the crystal is subsequently grown in the lateral direction. The feature of this method is that it is possible to produce a single crystal region on the same plane as the substrate at a desired location, and it is thought that by repeating this technique, it will be possible to produce a two-dimensional semiconductor device.

しかし、現実には横方向に単結晶化できる長さは最大で
も１００μｍ程度であり、表面の凹凸も大きい。この原
因としては、いろいろ考えられるが、一つにはシリコ／
層の中に不純物が多く含まれてお・す、それが結晶粒成
長や単結晶化を阻害していると考えられる。特に問題と
なるのは水素、酸素等である。現在のシリコンＩｉｉは
減圧ＣＶＤ法にて被着するが、この方法によるとこれら
の不純物はさけがたいというのが一般的である。。However, in reality, the maximum length that can be made into a single crystal in the lateral direction is about 100 μm, and the surface irregularities are large. There are many possible reasons for this, but one is silicone/
The layer contains many impurities, which are thought to inhibit grain growth and single crystal formation. Particularly problematic are hydrogen, oxygen, and the like. Current silicon III is deposited by a low pressure CVD method, but these impurities are generally unavoidable with this method. .

そこで、このような欠へを解決する手段としてはＣＶＤ
法にかわり、蒸着法にてシリコ／層を被着させることで
ある１、こうすることに［つで不純物の官有量は減少す
るが、蒸着後試＃＋全空気中に置くと、空気中の酸素、
窒素、水等を吸収して、やはり単結晶化を阻害１〜てし
まうＱ 発明の目的 本発明はこのような点に鑑み′Ｃなされたもので良質の
単結晶膜金容易に得る事を目的とする。Therefore, as a means to solve this shortage, CVD is
Instead of using the evaporation method, the silicon/layer can be deposited using the evaporation method. oxygen inside,
It absorbs nitrogen, water, etc. and also inhibits single crystallization.Objective of the Invention The present invention was made in view of the above points, and the purpose is to easily obtain a high quality single crystal film of gold. shall be.

発明のｇ要 本発明はＩＪＳＳ法においてシリコン）−を蒸層法にて
被着し、真空を破ることなく同−真空内で試料を搬送し
てアニール装置中に移し、ここでアニールして単結晶化
するようにしたものである。Summary of the invention In the IJSS method, the present invention deposits silicon by a vapor layer method, transports the sample in the same vacuum without breaking the vacuum, and transfers it to an annealing device, where it is annealed and single-layered. It is made to crystallize.

発明の効果 本発明により良質の半導体ｌ−を形成して、素子の三次
元的集積化を実用上十分な特性をもたせて第２図（ａ）
〜（ｅ）は一実施例の製造工程を示す断面図である。Effects of the Invention According to the present invention, a high-quality semiconductor l- is formed and has sufficient characteristics for practical three-dimensional integration of elements, as shown in FIG. 2(a).
-(e) are cross-sectional views showing the manufacturing process of one example.

まず第２図（ａ）で示すように、たとえばｐ型（１００
）面方位の単結晶シリコン基板１０１の表面に絶縁膜と
して約１μｍの５ＩＯｓ膜１０２を形成する。その上に
ＳＩＮ膜１０３を形成する。このＳｉＮ膜は後の工程で
多結晶あるいは非晶質シリコン層を単結晶化させやすく
するために形成するものである。またシリコン基板１０
１は既に所望の素子が周知の工程を経て形成されている
とする。次に第２図（１））で示すように、ＳＩＯ鵞膜
１０２、ＳｉＮ膜１０３を公知の方法にてパターニング
して、エツチングすることにより一部を開孔する。その
後、シリコン基板を蒸着装置に入れ、ｌｏ’Ｔｏｒｒの
圧力下で全面にたとえば５０００＾のシリコン層１０４
を蒸着する。次に７リコン基板を同−真空内にて搬送し
・で、アニール装置中に移し、第２図（Ｃ）で示すよう
に電子ビームを上部から照射して上記シリコン層１０４
をアニールする。First, as shown in FIG. 2(a), for example, p-type (100
) A 5IOs film 102 having a thickness of approximately 1 μm is formed as an insulating film on the surface of a single-crystal silicon substrate 101 having a plane orientation of 1 μm. A SIN film 103 is formed thereon. This SiN film is formed to facilitate single crystallization of a polycrystalline or amorphous silicon layer in a later step. Also, the silicon substrate 10
1 assumes that a desired element has already been formed through a well-known process. Next, as shown in FIG. 2(1), the SIO film 102 and the SiN film 103 are patterned by a known method and etched to partially open holes. After that, the silicon substrate is placed in a vapor deposition apparatus, and a silicon layer 104 of, for example, 5000^ is deposited on the entire surface under a pressure of lo' Torr.
Deposit. Next, the silicon substrate 7 is transferred in the same vacuum and transferred to an annealing device, and as shown in FIG. 2(C), an electron beam is irradiated from above to form the silicon layer 104
anneal.

アニール条件としては電子線の加速磁圧１０ＫＶ、シリ
コン基板に到達するビーム電流としては＋０ｍ人とした
。またビームスポット径は２００μｒｎφであり、１１
００Ｃ／ＳｅＣの走査速度で走査した。さらに電子ピー
ｌ−アニールの際の基板温度は４５０℃、真空度は１０
　’ＴＯｒｒ以上とした。The annealing conditions were an electron beam acceleration magnetic pressure of 10 KV and a beam current reaching the silicon substrate of +0 m. Also, the beam spot diameter is 200 μrnφ and 11
Scanning was performed at a scanning speed of 00C/SeC. Furthermore, the substrate temperature during electronic peel annealing was 450°C, and the degree of vacuum was 10°C.
'Torr or more.

第３図は本実施例で用いたシリコン１−蒸着及びアニー
ル装置である。まず左側の蒸着装置にてシリコンｌ−を
蒸着する。２０１はチェ／バー、２０２は基板ホルダー
、２０３はシリコン蒸着源、２０４は蒸着用Ｈ−ｇｕｎ
、２０５は真空用ポンプ、２０６は試料そう入口、２０
７は半導体基鈑である。２０８は半導体基板搬入路、２
０９，２１０はゲートバルブである。FIG. 3 shows a silicon 1-evaporation and annealing apparatus used in this example. First, silicon l- is vapor deposited using the left vapor deposition apparatus. 201 is a chamber/bar, 202 is a substrate holder, 203 is a silicon evaporation source, and 204 is an H-gun for evaporation.
, 205 is a vacuum pump, 206 is a sample inlet, 20
7 is a semiconductor substrate. 208 is a semiconductor substrate loading path;
09,210 is a gate valve.

蒸着後、基板は右側のアニール装置に搬入されアニール
される。本実施例では電子ビームを用いてアニールして
いる。２１１ハチエンｌバー、　２１２ハ半導体基板ホ
ルダー、２１３は加熱ヒーター、２１４は電力線、２１
５は水冷パイプ、２１６は基板粗動ステージ、２１７は
電子銃、２１８は真空ポンプ、２１９は試料取り出し口
である。After vapor deposition, the substrate is carried into the annealing device on the right side and annealed. In this embodiment, annealing is performed using an electron beam. 211 Hachien l bar, 212 C semiconductor substrate holder, 213 heating heater, 214 power line, 21
5 is a water cooling pipe, 216 is a substrate coarse movement stage, 217 is an electron gun, 218 is a vacuum pump, and 219 is a sample extraction port.

を子ビームアニール条件において、本実施列でハ５００
０＋のシリコン４１０４　、ｒアニールするためυロ速
イ圧は低い方がよく、ｌ０ＫＶの時には、エネルキーデ
ポジションのピークは０．３μｍ程度である。従って、
もしより厚いシリコン層をアニールする時にはより加速
′屯田を上げる必要がある。また真空度はよい程よく今
回は１０８ＴＯｒｒで行なったが、できれば１「１０以
上が望ましい。しかも真空の質も問題で、・・イドロカ
ーボンなどは出来る限り減らすことが望ましい。ビーム
の走査速量↓ビームのスポット径との兼ね合いによって
決まるがビーム径は大きければ一枚のウニ・・−をアニ
ールする時間が短縮できる。望ましいビーム径は１００
μｍ−１０００μｍ８度である。ア＝−ν１の基板可熱
温度は高い程アニールには向いているが、余り高すぎる
と先に製、１１ 作したデバイスに悪影響を与えるため５００　’０以下
が望ましい。Under the child beam annealing conditions, in this implementation column, HA500
Since 0+ silicon 4104 is annealed, the lower the pressure, the better, and at 10 KV, the peak of energy deposition is about 0.3 μm. Therefore,
If thicker silicon layers are to be annealed, a higher acceleration rate is required. In addition, the degree of vacuum is good, and this time we used 108 TOrr, but preferably 108 TOrr or higher.Moreover, the quality of the vacuum is also an issue, and it is desirable to reduce hydrocarbons as much as possible.Beam scanning speed ↓ Beam The beam diameter is determined by the balance with the spot diameter, but if the beam diameter is large, the time to anneal one sea urchin can be shortened.
μm-1000 μm 8 degrees. The higher the substrate heatable temperature of A=-ν1 is, the more suitable it is for annealing, but if it is too high, it will have an adverse effect on the previously manufactured device, so it is preferably 500'0 or less.

アニール手段としては電子ビーム以外、たとえはレーザ
ービームでもかまわない。この場合にはアニールチェン
バー内にレーザー光を導入しアニールする事ができる。The annealing method may be other than an electron beam, for example a laser beam. In this case, laser light can be introduced into the annealing chamber for annealing.

このような装置を用いてシリコン層の蒸着、アニールを
行なうことにより本発明の効果を充分に発揮させること
ができる。本発明によれば横方向への単結晶成長長さを
数朋にすることかり能で、従来数百μｍしか成長しない
のに比べて１〜２桁向大向大変で、各チップ毎にエビ成
長のための開孔部を設ければ１枚のウェハー全面を単結
晶化することも可能である。その意味で本発明を用いて
単結晶シリコン層を形成したということは非常に重要で
ある。By performing vapor deposition and annealing of the silicon layer using such an apparatus, the effects of the present invention can be fully exhibited. According to the present invention, the length of single crystal growth in the lateral direction can be reduced to several lengths, which is one to two orders of magnitude more difficult than the conventional method where the single crystal grows only a few hundred μm. By providing an opening for growth, it is also possible to form a single crystal over the entire surface of one wafer. In this sense, it is very important that the present invention was used to form a single crystal silicon layer.

次に第２図（ｄ）で示すように、電子ビームアニールに
よって単結晶化したシリコン層１０４′をパターニング
して素子形成領域とし、その後公知の技術にて素子間分
離絶縁膜１０５を形成し、素子領域にゲート酸化ｍ　１
０６を介して例えば多結晶シリコンからなるゲート電極
１０７を形成し、ソース・ドレイン領域１０８．１０９
を形成してＭＯ８）ランラスタとする。次に第２図（ｅ
）で示すように全面を絶縁膜１１０でおおった後、Ａｌ
ｌによる亀＋１！、１１１−１１３を形成して三次元に
集積した半導体装置を完成する。Next, as shown in FIG. 2(d), the silicon layer 104', which has been single-crystalized by electron beam annealing, is patterned to form an element formation region, and then an element isolation insulating film 105 is formed using a known technique. Gate oxidation m 1 in the element area
A gate electrode 107 made of, for example, polycrystalline silicon is formed through the source/drain regions 108 and 109.
to form a MO8) run raster. Next, Figure 2 (e
), after covering the entire surface with an insulating film 110, Al
Turtle +1 by l! , 111-113 are formed to complete a three-dimensionally integrated semiconductor device.

なお、上記実施例ではＭＯ８）ランラスタについて説明
したが、本発明によるシリコン層にはＣ−ＭＯＳ　）ラ
ンラスタ、バイポーラトランジスタ、ダイオードなどあ
らゆる素子を形成できることはいうまでもなく、本発明
の効果を用いて、これらの素子を三次元的に配列するこ
とにより、従来より高集積、高性能、多機能な四次元集
積回路装置を実現することが可能となった。In the above embodiment, the MO8) run raster was explained, but it goes without saying that all kinds of elements such as C-MOS) run raster, bipolar transistors, diodes, etc. can be formed in the silicon layer according to the present invention. By arranging these elements three-dimensionally, it has become possible to realize a four-dimensional integrated circuit device with higher integration, higher performance, and more functionality than ever before.

本発明の効果はシリコン以外の半導体たとえばゲルマニ
ウムや、ＧａＡＳ、ＧａＰなどの三−五族化合物半導体
、　　ＩｎＰ、Ｉｎ８ｂなどのニー五族化合物半導体に
おいても期待でき、これらを組合せることにより、−チ
ップに従来の記憶回路、論理回路と共に表示。The effects of the present invention can also be expected in semiconductors other than silicon, such as germanium, III-V compound semiconductors such as GaAS and GaP, and N-V compound semiconductors such as InP and In8b. Displayed together with conventional memory circuits and logic circuits.

感知機能などを同時に備えた多機能素子を作りあげるこ
とができる。また本実施例の第２図（ｅ）の工程におけ
るＡ／による電極は他の金属でもかまわない。その他、
この発明の主旨を逸脱しない限り種々の応用例が期待で
きる。It is possible to create multifunctional devices that have sensing functions and other functions at the same time. Further, the electrode made of A/ in the step of FIG. 2(e) of this embodiment may be made of other metals. others,
Various applications can be expected without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図はエネルギービーム照射によるＬＥｓｓ構造の単
結晶膜の形成過程を説明する断面図、第２図（ａ）〜（
ｅ）はこの発明の一実施例の製造工程を示す断面図、第
３図は本発明で用いたシリコン層蒸着及びアニール装置
である。 図に於いて、 １０１・・・単結晶シリコン基板、　　１０２・・ｓＩ
ｏｔｇ、１０３・・・ＳＩＮ膜、　　１０４・・多結晶
シリコン層。 １０４′・・・単結晶化したシリコン層、１０５・・絶
縁膜、　　　１０６・・ゲート酸化膜、１０７　・・ゲ
ート成極、　ｌｏｇ、ｌｏ９・・ソース・ドレイン領域
、１１０・・絶縁膜、　　１１１−１１３・・・Ａ／？
電甑。 ２０１・・・蒸着装置チェンバー、２０２・・・基板ホ
ルダー、２０３　・・シリＶ蒸着源、　　２０４・・・
蒸着用Ｅ　−ｇｕｎ、２０５　　・真空用ポンプ、　　
２０６・・・試料そう入口、２０７・・半導体基板、２
０８・・・半導体基板搬入路、２０９　、２１０　　・
・ゲートバルブ、２１１　　・・アニールナエノパー、
２１２　・・半導体基板ホルダー、２１３　・・加熱ヒ
ーター、２１４−力線、　　２１５・・・水冷パイプ、
２１６・・基板粗動ステージ、　　２１７・・・遜子銃
、２１８・・真空ポンプ、２１９・試料取り出し口。 代理人　弁理士　　則　近　憲　佑 （他１名） １：１・ 第１図 ／−−ｌ 第　　２　図 （６２ （Ｃ） エキルギー・　ビーム@ Figure 1 is a cross-sectional view explaining the formation process of a single crystal film with an LEss structure by energy beam irradiation, and Figures 2 (a) to (
e) is a sectional view showing the manufacturing process of an embodiment of the present invention, and FIG. 3 is a silicon layer deposition and annealing apparatus used in the present invention. In the figure, 101...single crystal silicon substrate, 102...sI
otg, 103... SIN film, 104... polycrystalline silicon layer. 104'...Single crystal silicon layer, 105...Insulating film, 106...Gate oxide film, 107...Gate polarization, log, lo9...Source/drain region, 110...Insulating film, 111- 113...A/?
Electric oven. 201... Vapor deposition device chamber, 202... Substrate holder, 203... SiliV vapor deposition source, 204...
E-gun for vapor deposition, 205 ・Vacuum pump,
206...Sample entrance, 207...Semiconductor substrate, 2
08... Semiconductor substrate loading path, 209, 210 ・
・Gate valve, 211 ・・Annealer enopar,
212...Semiconductor substrate holder, 213...Heating heater, 214-line of force, 215...Water cooling pipe,
216: Substrate coarse movement stage, 217: Shoko gun, 218: Vacuum pump, 219: Sample extraction port. Agent Patent attorney Noriyuki Chika (and 1 other person) 1:1・Figure 1/--l Figure 2 (62 (C) Ekirugi Beam

Claims (5)

【特許請求の範囲】[Claims] （１）単結晶半導体基板が露出した大領域と該基板上の
所望部分に絶縁膜を液層したＢ領域とを備え、上記へ領
域の少なくとも一部とＢ領域を連続して覆うよりに蒸着
によジ″４導体層を被着し、同一真空内にてこの半導体
層の所望部分にエネルギービームを連続的に走査しなが
ら照射してアニールを施して、該半導体層の少なくとも
一部を単結晶としだ半導体層を得、この半導体層に所望
の素子を形成することを特徴とする半導体装置の製造方
法、。(1) A single-crystal semiconductor substrate is provided with a large exposed area and a B area in which an insulating film is formed as a liquid layer on a desired part of the substrate, and is vapor-deposited to continuously cover at least a part of the area and the B area. A four conductor layer is deposited on the semiconductor layer, and a desired portion of this semiconductor layer is annealed by continuously scanning and irradiating a desired portion of this semiconductor layer in the same vacuum, so that at least a portion of the semiconductor layer is isolated. A method for manufacturing a semiconductor device, which comprises obtaining a crystalline semiconductor layer and forming a desired element in this semiconductor layer. （２）半導体層の蒸着は１０−５〜１Ｏ−１１ＴＯｒｒ
の圧力下にて行なうものである前記特許請求の範囲第１
項記載の半導体装置の製造方法。(2) Vapor deposition of semiconductor layer is 10-5 to 1O-11 TOrr
Claim 1 is carried out under the pressure of
A method for manufacturing a semiconductor device according to section 1. （３）エネルギービーム照射は基板を２００〜５００　
’０に加熱し１０−５〜１Ｏ−１１ＴＯｒ「の圧力下Ｋ
　テ５〜；ＩＩ）　ＫｅＶの加速エネルギーの連続電子
ビーム？　０．５〜５００ｂｙ／ｓｅｃの速度にて走査
しながら行なうものである前記特許請求の範囲第１項記
載の半導体装置の製造方法。(3) Energy beam irradiation targets the substrate at 200 to 500
Heated to '0 K under pressure of 10-5~1O-11 Tor'
Te5~;II) Continuous electron beam with KeV acceleration energy? The method for manufacturing a semiconductor device according to claim 1, wherein the manufacturing method is performed while scanning at a speed of 0.5 to 500 by/sec. （４）絶縁膜Ｖよ７リコン酸化膜、シリコン窒化膜、シ
リコン炭化ｄ、アルミニウム酸化膜、タンタル酸化膜、
カーボン、リンガフス、砒素ガラス、ボロンガラスから
なる群から選ばれる前記特許請求の範囲第１項記載の半
導体装置の製造方法。(4) Insulating film V7 silicon oxide film, silicon nitride film, silicon carbide d, aluminum oxide film, tantalum oxide film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is selected from the group consisting of carbon, phosphorous glass, arsenic glass, and boron glass. （５）半導体層の１漠厚は０．０５〜２μｍである前記
特許請求の範囲第１項記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer has a rough thickness of 0.05 to 2 μm.
JP56190631A 1981-11-30 1981-11-30 Preparation of semiconductor device Pending JPS5893223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190631A JPS5893223A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190631A JPS5893223A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5893223A true JPS5893223A (en) 1983-06-02

Family

ID=16261274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190631A Pending JPS5893223A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5893223A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235512A (en) * 1985-08-09 1987-02-16 Agency Of Ind Science & Technol Manufacture of single crystal thin film of semiconductor
US4965219A (en) * 1984-07-19 1990-10-23 Sgs Microelettronica Spa Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits
US5424241A (en) * 1992-08-21 1995-06-13 Smiths Industries Aerospace & Defense Systems, Inc. Method of making a force detecting sensor
US5753542A (en) * 1985-08-02 1998-05-19 Semiconductor Energy Laboratory Co., Ltd. Method for crystallizing semiconductor material without exposing it to air

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965219A (en) * 1984-07-19 1990-10-23 Sgs Microelettronica Spa Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits
US5753542A (en) * 1985-08-02 1998-05-19 Semiconductor Energy Laboratory Co., Ltd. Method for crystallizing semiconductor material without exposing it to air
JPS6235512A (en) * 1985-08-09 1987-02-16 Agency Of Ind Science & Technol Manufacture of single crystal thin film of semiconductor
US5424241A (en) * 1992-08-21 1995-06-13 Smiths Industries Aerospace & Defense Systems, Inc. Method of making a force detecting sensor
WO1995034912A1 (en) * 1994-06-14 1995-12-21 Smiths Industries Aerospace & Defense Systems, Inc. Force detecting sensor and method of making

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