JP2515301B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having an insulated gate transistor, and more particularly to a method for manufacturing a semiconductor device in which an insulated gate transistor is formed on an insulator surface. Regarding

[Prior Art and Its Problems] An integrated circuit device in which single crystal silicon is formed on an insulating substrate to form an integrated circuit has a higher parasitic capacitance than the integrated circuit formed on the silicon substrate. It becomes possible to operate. Further, even if a complementary MOS (C-MOS) integrated circuit is formed, the parasitic bipolar transistor does not form a thyristor, so that there is no possibility of causing a latch-up phenomenon. There is.

Conventionally, a sapphire substrate has been used as an insulating substrate used in such an integrated circuit device.

However, the sapphire substrate is much more expensive than the silicon substrate, and can be applied only to limited integrated circuits.

In recent years, the silicon substrate is covered with an insulator,
After forming a polycrystalline silicon thin film on it, a method of forming a single crystal thin film by melting and recrystallizing with a laser beam, or by implanting oxygen ions into the silicon substrate and forming an insulating layer in the silicon substrate , A method of obtaining a structure in which a single crystal silicon layer exists on an insulating layer, and the like have been proposed.

However, whichever method is used, a very low production efficiency process such as a melting process of polycrystalline silicon by a laser beam and a high dose ion implantation process by an ion implantation device is required. For this reason, it is difficult to reduce the cost of the integrated circuit device, and it is difficult to obtain a high quality single crystal silicon film, so that a high performance integrated circuit cannot be formed.

[Means for Solving the Problems] In the semiconductor device according to the present invention, in a method for manufacturing a semiconductor device having an insulated gate transistor, a substrate having an insulating layer on its surface is prepared, and a part of the surface of the insulating layer is provided. A surface made of an amorphous dissimilar material having a higher nucleation density than that of the insulating layer and sufficient to grow into a single crystal and form a single nucleus. A single-crystal semiconductor region is formed by growing nuclei formed on the surface of the substrate, and the source, drain, and channel regions of the insulated gate transistor are formed in the semiconductor region.

[Operation] In order to form a single crystal layer on the insulating material by the selective crystal growth method in which a single crystal is grown around the nucleation base as described above, this insulating material is used regardless of the material of the base substrate. A good quality single crystal layer can be formed only by forming it on the surface. Therefore, an insulated gate transistor with a small source and drain stray capacitance can be manufactured, high-speed operation is possible, and an integrated circuit without a latch-up phenomenon can be provided at a low price.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention.

In the figure, the substrate 101 is formed of a desired material such as a semiconductor material or an insulating material such as quartz or ceramics.

An insulating layer 102 made of a material having a low nucleation density when forming silicon is formed on the substrate 101 as described later. In this embodiment, SiO ₂ is used as the material of the insulating layer 102, and is formed by oxidation or CVD.

An n-channel MOS transistor 103 and a p-channel MOS transistor 104 are formed on the insulating layer 102, and a C-MOS is formed in this embodiment. Below, transistor 103
The manufacturing steps of 104 and 104 will be described.

First, a material (here, silicon nitride) having a higher nucleation density than SiO ₂ is formed on the insulating layer 102, and then about 1.0 μm is formed.
The nucleation base 105 is formed by patterning into a sufficiently minute shape of about a corner. The nucleation base 105 may be formed by ion implantation as described later.

Next, using H ₂ gas as a carrier, single crystal silicon centered on the nucleation base 105 is grown using SiHCl ₄ , SiHCl ₃ or the like at a temperature of about 700 to 1000 ° C. The single crystal silicon thus grown is planarized to form an island-shaped single crystal silicon layer 10
Forming 6

Next, p-type impurity ions are implanted into the single crystal silicon layer 106 where the transistor 103 is to be formed, and n-type impurity ions are implanted into the single crystal silicon layer 106 where the transistor 104 is to be formed.

Next, the gate insulating film 1 is formed on each single crystal silicon layer 106.
07 is formed, and the gate electrode 108 of polycrystalline silicon is further patterned. Next, using the gate electrode 108 as a mask, n-type impurity ions are implanted into the transistor 103 side and p-type impurity ions are implanted into the transistor 104 side, respectively, and the subsequent heat treatment is performed to use the n-diffused region and the p-diffused region as source / drain regions, respectively. Form.

Finally, the source / drain electrodes 109 and 110 and the wiring are formed, and the n-channel MOS transistor 103 and the p-channel MOS transistor 104 that form a C-MOS are manufactured.

The MOS transistor thus manufactured has a source and drain stray capacitance much smaller than that of a general pn junction type. Also, the channel mobility was 400 cm ² / V · sec or more for the n-channel MOS transistor 103 and 200 cm ² / V · sec or more for the p-channel MOS transistor 104, which was the same value as the transistor formed on the silicon wafer. This indicates that good quality single crystal silicon was obtained by the selective crystal growth method.

In this embodiment, the MOS transistor is manufactured to form the C-MOS, but the present invention is not limited to this, and the MOS transistor may be manufactured independently. Further, it is not limited to MOS, and may be an insulated gate type suitable for high integration.

FIG. 2 is a schematic sectional view of a second embodiment according to the present invention.

As in this embodiment, the interlayer insulating layer 111 of SiO ₂ is formed on the lower layer on which the MOS transistor is formed, and the MOS transistor can be formed on it by the same process. Further, a contact hole is opened in the interlayer insulating layer 111, and the MOS transistor 103 is connected to the MOS transistor 104 in the lower layer by wiring. By repeating such steps, three-dimensional integration of two or more layers can be easily achieved.

In the case of a multi-layer structure, n-channel and p-channel transistors can be formed in different layers.

In addition, since the single crystal silicon layer can be formed at a low temperature of about 700 to 1000 ° C., there is no deterioration in the characteristics of the underlying element.

Next, the MOS transistors 103 and 10 in this embodiment.
A method for forming a single crystal layer for producing a device such as 4 will be described in detail.

First, a selective deposition method for selectively forming a deposition film on a deposition surface will be described. The selective deposition method uses the difference between materials, such as surface energy, adhesion coefficient, desorption coefficient, and surface diffusion rate, which influences nucleation during thin film formation.
In this method, a thin film is selectively formed on a substrate.

FIGS. 3A and 3B are explanatory views of the selective deposition method. First, as shown in FIG.
And a thin film 2 made of a material having different factors described above is formed in a desired portion. Then, when a thin film made of an appropriate material is deposited under appropriate deposition conditions, the phenomenon that the thin film 3 grows only on the thin film 2 and does not grow on the substrate 1 can occur. By utilizing this phenomenon, the thin film 3 formed in a self-aligned manner can be grown, and a conventional lithography process using a resist can be omitted.

Examples of materials that can be deposited by the selective formation method include SiO ₂ as the substrate 1, Si, GaAs, and silicon nitride as the thin film 2, and Si, W, GaAs, InP as the thin film 3 to be deposited. .

FIG. 4 is a graph showing the change over time in the nucleation density of the deposition surface of SiO _{2 and} the deposition surface of silicon nitride.

As the graph shows, the SiO ₂
The nucleation density above saturates below 10 ³ cm ^-2 , and its value hardly changes after 20 minutes.

On the other hand, on silicon nitride (Si ₃ N ₄ ), ~ 4 × 1
0 ⁵ cm ^{-2 It} saturates once and then does not change for about 10 minutes, but it increases rapidly after that. In this measurement example, SiCl
_The figure shows the case where ₄ gases are diluted with H ₂ gas and deposited by the CVD method under the conditions of a pressure of 175 Torr and a temperature of 1000 ° C. Besides SiH
₄ , SiH ₂ Cl ₂ , SiHCl ₃ , SiF ₄ etc. as reaction gas,
The same effect can be obtained by adjusting the pressure, temperature and the like. Also, vacuum deposition is possible.

In this case, nucleation on SiO ₂ is hardly a problem, but by adding HCl gas to the reaction gas, nucleation on SiO ₂ is further suppressed, and Si is not deposited on SiO _2. Can be

This phenomenon is largely due to the difference in the adsorption coefficient, desorption coefficient, surface diffusion coefficient, etc. of Si on the material surfaces of SiO ₂ and silicon nitride, but SiO ₂ reacts with the Si atoms themselves and the vapor pressure is high. The fact that SiO ₂ itself is etched by the generation of silicon oxide and such an etching phenomenon does not occur on silicon nitride is also considered to be the cause of selective deposition (T. Yoneha
ra, S.Yoshioka, S.Miyazawa Journal of Applied Physic
s 53,6839,1982).

If SiO ₂ and silicon nitride are selected as the material of the deposition surface and silicon is selected as the deposition material, a sufficiently large difference in nucleation density can be obtained as shown in the graph. Note that, here, SiO ₂ is desirable as the material of the deposition surface, but the present invention is not limited thereto, and a difference in nucleation density can be obtained even with SiOx.

Of course, the invention is not limited to these materials, it is sufficient if 10 ³ times or more in a density of nuclei as shown by the difference the graph of nucleation density, also deposited by a material exemplified later film Can be formed selectively.

As another method for obtaining this difference in nucleation density, Si or N or the like may be locally ion-implanted into SiO ₂ to form a region having excessive Si or N or the like.

By using such a selective deposition method, a nucleation base having a nucleation density sufficiently higher than that of the material of the deposition surface is formed fine enough so that only a single nucleus grows. It is possible to selectively grow a single crystal only in the existing portion.

Since the selective growth of a single crystal is determined by the electronic state of the surface of the deposition surface, especially the state of dangling bonds, the material with low nucleation density (for example, SiO ₂ ) does not need to be a bulk material. It suffices that it is formed only on the surface of an arbitrary material or substrate to form the above-mentioned deposition surface.

FIGS. 5 (A) to 5 (D) are process charts showing a first example of a method for manufacturing a multilayer structure, and FIGS. 6 (A) and 6 (B).
FIG. 6 is a perspective view of the substrate in FIGS. 5A and 5D.

In FIGS. 5 and 6, the substrate 4'shows the substrate 101 shown in FIG. 1 or the substrate 101 having the transistor 104 shown in FIG. 2 formed thereon.

First, as shown in FIGS. 5 (A) and 6 (A), a deposition surface material layer 5 (for example, SiO ₂ or the like) having a low nucleation density is formed on a substrate 4 ′ so as to enable selective deposition. Then, a material having a high nucleation density is thinly deposited thereon, and patterned by lithography or the like to form the nucleation base 6 fine enough to form each single nucleation base 6 as described later. Further, as described above, each forming base 6 also includes an altered region having excessive Si, N, etc. formed by ion-implanting Si, N, etc. into the deposition surface material layer 5.

Then, by properly setting the deposition conditions, a single nucleus of deposited material is formed only in each forming base 6. That is, the nucleation base 6 needs to be formed fine enough so that only a single nucleus is formed. The size of the nucleation base 6 depends on the type of material, but may be several microns or less. Furthermore, the nuclei grow while maintaining the single crystal structure to form island-shaped single crystal grains 7 as shown in FIG. 5 (B). In order to form the island-shaped single crystal grains 7, as described above, it is necessary to determine conditions so that nucleation does not occur at all on the deposition surface material layer 5.

The island-shaped single crystal grains 7 further grow around the nucleation base 6 while maintaining the single crystal structure, and cover the deposition surface material layer 5 as shown in FIG.

Subsequently, the single crystal grains 7 are flattened by etching or polishing, and as shown in FIGS. 5 (D) and 6 (B), the single crystal layer 8 capable of forming a desired element is a deposition surface material. Formed on layer 5.

Thus, the substrate 4'on which the transistor 101 and the like are formed
A single crystal layer 8 is formed on top of the deposited material layer 5, which is also an insulating layer, and an electronic element such as a transistor 102 is formed on the single crystal layer 8. Further, wiring and contact holes with lower layers are formed in a normal semiconductor. A two-layer integrated circuit can be formed by forming it by a process. Of course, by repeating the above steps, a three-dimensional integrated circuit having a multilayer structure can be easily manufactured.

7 (A) to 7 (D) are process charts showing a second example of the method for manufacturing a multilayer structure, and FIGS. 8 (A) and 8 (B).
FIG. 7 is a perspective view of the substrate in FIGS. 7A and 7D.

As shown in FIG. 7 (A) and FIG. 8 (A), the deposition surface material layer 5 is formed on the substrate 4 ′ on which the electronic element is formed.
(Here, an SiO ₂ layer which is also an insulating layer) is formed, and a nucleation base 12 that enables the above selective deposition is arranged sufficiently small thereon with a distance 1 therebetween. This distance 1 is set to be equal to or larger than the size of a single crystal region required for forming a semiconductor element, for example.

A single nucleus of deposited material is then formed only on the nucleation base 12 by suitable deposition conditions. That is, the nucleation base 12 needs to be formed fine enough so that only a single nucleus is formed. The size of the nucleation base 12 depends on the type of material, but may be several microns or less. Further, the nuclei grow while maintaining the single crystal structure to form island-shaped single crystal grains 13 as shown in FIG. 7 (B). In order to form the island-shaped single crystal grains 13, as described above,
It is necessary to determine the conditions so that no nucleation occurs on the deposition surface material layer 5.

The crystal orientation of the island-shaped single crystal grains 13 in the substrate normal direction is determined so as to minimize the interfacial energy between the deposition surface material and the deposited material. This is because the surface or interface energy has anisotropy depending on the crystal plane. However, as described above, the in-plane crystal orientation on the amorphous plane is not determined.

The island-shaped single crystal grains 13 grow further and come into contact with the adjacent single crystal grains 13 as shown in FIG. 7 (C), but the crystal orientation in the deposition plane is not constant. A grain boundary 14 is formed at an intermediate position of 12.

Subsequently, the single crystal grains 13 grow three-dimensionally, but since the crystal planes with a slow growth rate appear as facets, the surface is flattened by etching or polishing, and further the portion of the grain boundaries 14 is removed. As shown in FIGS. 7 (D) and 8 (B), a single crystal thin film 15 containing no grain boundaries is formed in a lattice shape. The size of the single crystal thin film 15 is determined by the interval 1 of the nucleation base 12 as described above.
That is, by appropriately defining the formation pattern of the nucleation base 12, the position of the grain boundary can be controlled, and a single crystal having a desired size can be formed in a desired arrangement.

Thus, the deposited material layer 5 which is also an insulating layer on the substrate 4 '
A single crystal layer 15 is formed so as to sandwich the semiconductor element between them, and electronic elements such as the MOS transistors 103 and 104 are formed in the single crystal layer 15 by a normal semiconductor process as in the present embodiment.
The integrated circuit shown in FIG. 2 or FIG. 2 can be constructed. Of course, by repeating the above steps, an integrated circuit having a multilayer structure can be easily manufactured.

FIGS. 9 (A) to 9 (C) are formation process diagrams showing a third example of the method for manufacturing a multilayer structure, and FIGS. 10 (A) and 10 (B).
FIG. 9 is a perspective view of the substrate in FIGS. 9 (A) and 9 (C).

First, as shown in FIGS. 9 (A) and 10 (A), a deposition surface material layer 18 (here, an SiO ₂ layer which is also an insulating layer) is formed on the substrate 4 ′, and the deposition surface material layer is formed. A recess 16 of the required size and shape is formed in 18 and a sufficiently fine nucleation base 12 is formed therein.

Then, as shown in FIG. 9B, island-shaped single crystal grains 13 are grown in the same manner as in the first embodiment.

Then, as shown in FIG. 9 (C) and FIG. 10 (B), the single crystal grains 13 are grown until they fill the recesses 16 to form a single crystal layer 17.

In this embodiment, since the single crystal grains 13 grow in the concave portions 16, the steps of flattening and removing the grain boundary portion are not required.

Thus, the deposited material layer 18 which is also an insulating layer on the substrate 4 '
The single crystal layer 17 is formed in an island shape with the single crystal layer 17 interposed therebetween.
Then, an electronic element such as a transistor is formed by an ordinary semiconductor process.

(Specific Example) Next, a specific method of forming the single crystal layer in the above-described embodiment will be described focusing on the second example shown in FIG.

The SiO ₂ layer 5 is formed on the Sit single crystal substrate 4 ′. Of course,
The SiO ₂ layer may be formed on the surface of the substrate by sputtering, CVD, vacuum deposition, or the like on any substrate such as metal, semiconductor, magnetic substance, piezoelectric substance, or insulator. As the deposition surface material is SiO ₂ is desirable it may be those obtained by changing the value of x as SiO _x.

A silicon nitride layer (here, a Si ₃ N ₄ layer) 5 is deposited as a different material on the SiO ₂ layer 5 thus formed by a low pressure vapor phase epitaxy method, and an ordinary lithography technique or X-ray, electron beam or ion beam is applied. The silicon nitride layer is patterned by the used lithographic technique to form a fine nucleation base 12 having a size of several microns or less, preferably ˜1 μm or less.

Then, HCl and H ₂ , SiH ₂ Cl ₂ , SiCl ₄ , SiH Cl ₃ , SiF ₄
Or, using a mixed gas of SiH ₄ and Si on the SiO ₂ layer 5,
Grow selectively. The substrate temperature at that time is 700-1000
C, pressure is about 100 Torr.

The single crystal Si grains 13 grow around the fine nucleation base 12 of silicon nitride on SiO _{2 in} about several tens of minutes. Ten μ
Grows to m or more.

Then, by reactive ion etching (RIE) in which there is a difference in etching rate between Si and SiO ₂ , only Si is flattened by etching, and further grain boundary portions are removed to form an island-shaped single crystal silicon layer 15 Is formed. If the surface of the single crystal grain 13 has large irregularities, etching is performed after mechanical polishing.

The MOS transistor 103 is formed in the single crystal silicon layer 15 having a size of several tens of μm or more and including no grain boundary formed in this way.
And 104 were shown to be as good as those formed on the single crystal silicon wafer. Further, even when a large number of elements are arranged, the single crystal silicon layer 15 can be formed in the already arranged state, so that the manufacturing process is simplified.

Further, since it is electrically separated from the adjacent single crystal silicon layer 15 by SiO ₂ , even if a complementary field effect transistor (C-MOS) is formed, there is no mutual interference.
Further, since the thickness of the active layer of the element is smaller than that of the case where a Si wafer is used, malfunction due to electric charges in the wafer generated when the radiation is applied is eliminated. Further, since the parasitic capacitance is reduced, the speed of the device can be increased. Further, since an arbitrary substrate can be used, a single crystal layer can be formed on a large-area substrate at a lower cost than when a Si wafer is used. Furthermore, since a single crystal layer can be formed over another substrate such as a semiconductor, a piezoelectric substance, or a dielectric substance, a multifunctional three-dimensional integrated circuit can be realized.

(Silicon Nitride Composition) In order to obtain a sufficient nucleation density difference between the deposition surface material and the nucleation base as described above, the composition is not limited to Si ₃ N _4. It may be changed.

In the plasma CVD method of decomposing SiH ₄ gas and NH ₃ gas in RF plasma to form a silicon nitride film at low temperature, SiH
By changing the flow rate ratio between the ₄ gas and the NH ₃ gas, the composition ratio of Si and N in the deposited silicon nitride film can be changed significantly.

FIG. 12 is a graph showing the relationship between the flow ratio of SiH ₄ and NH ₃ and the composition ratio of Si and N in the formed silicon nitride film.

The deposition conditions at this time were an RF output of 175 W and a substrate temperature of 380 ° C., the SiH ₄ gas flow rate was fixed at 300 cc / min, and the NH ₃ gas flow rate was changed. As shown in the graph, when the gas flow ratio of NH ₃ / SiH ₄ was changed from 4 to 10, Si in the silicon nitride film was changed.
Auger electron spectroscopy revealed that the / N ratio varied from 1.1 to 0.58.

Further, the composition of the silicon nitride film formed by introducing SiH ₂ Cl ₂ gas and NH ₃ gas by a low pressure CVD method under the condition of a pressure of 0.3 Torr and a temperature of about 300 ° C. is almost stoichiometric. ₃ N ₄ (S
It was close to i / N = 0.75).

Further, the silicon nitride film formed by heat-treating Si in ammonia or N ₂ at about 1200 ° C. (thermal nitriding method) is closer to the stoichiometric ratio because the forming method is performed under thermal equilibrium. The composition can be obtained.

Using silicon nitride formed by various methods as described above as a deposition surface material with a higher nucleation density of Si than SiO _2,
When a Si nucleus is grown, the composition ratio causes a difference in nucleation density.

FIG. 13 is a graph showing the relationship between the Si / N composition ratio and the nucleation density. As shown in the graph, by changing the composition of the silicon nitride film, the nucleation density of Si grown on it changes significantly. The nucleation conditions at this time are SiCl ₄
The gas is depressurized to 175 Torr and reacted with H ₂ at 1000 ° C. to generate Si.

The phenomenon that the nucleation density changes depending on the composition of silicon nitride affects the size of silicon nitride as a nucleation base that is finely formed to the extent that a single nucleus is grown. That is, silicon nitride having a composition with a high nucleation density cannot form a single nucleus unless it is formed very finely.

Therefore, it is necessary to select the nucleation density and the optimum silicon nitride size with which a single nucleus can be selected. For example, under deposition conditions that yield nucleation densities of ~ 10 ⁵ cm ^-2 , single nuclei can be selected if the size of silicon nitride is less than about 4 μm.

(Formation of Nucleation Base by Ion Implantation) As a method for realizing a difference in nucleation density with respect to Si, S is locally formed on the surface of SiO ₂ which is a deposition surface material having a low nucleation density.
i, N, P, B, F, Ar, He, C, As, Ga, and Ge, such as ion implantation to form an affected region in the deposition surface of the SiO _2, high deposition surface of nucleation density The affected region Good as a material.

For example, a desired portion of the SiO ₂ surface is covered with a resist, and a desired portion is exposed, developed, and dissolved to partially expose the SiO ₂ surface.

Then, SiF ₄ gas is used as a source gas, and Si ions are implanted into the SiO ₂ surface at a density of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^-2 at 10 keV. The projected range is 114Å, and the Si concentration reaches ~ 10 ²² cm ^-3 on the SiO ₂ surface. Since SiO ₂ is originally amorphous, the region where Si ions are implanted is also amorphous.

In addition, in order to form the altered region, ion implantation can be performed using a resist as a mask, but the focused ion beam technique was used to narrow down without using a resist mask.
Si ions may be implanted on the SiO ₂ surface.

After the ion implantation is performed in this manner, the resist is peeled off, so that an altered region having excessive Si is formed on the SiO ₂ surface. Si is vapor-phase grown on the SiO ₂ deposition surface where such altered regions are formed.

FIG. 14 is a graph showing the relationship between the implantation amount of Si ions and the nucleation density.

As shown in the graph, it can be seen that the nucleation density increases as the Si ⁺ implantation amount increases.

Therefore, by forming the altered region fine enough,
A single nucleus of Si can be grown using this quality region as a nucleation base, and a single crystal can be grown as described above.

Note that forming the altered region in a fine enough size to grow a single nucleus can be easily achieved by patterning the resist or narrowing the beam of the focused ion beam.

(Si deposition method other than CVD) Single crystal growth by selective nucleation of Si is not limited to the CVD method, but Si is evaporated in an electron gun in a vacuum (<10 ^-6 Torr) and deposited on a heated substrate. Methods are also used. In particular, MBE (Mol), which is vapor deposition in ultra-high vacuum (<10 ^-9 Torr)
In the ecular Beam Epitaxy method, the substrate temperature is 900 ° C or higher.
It is known that the beam and SiO ₂ begin to react, and there is no nucleation of Si on SiO ₂ (T.Yonehara, S, Yoshioka).
and S. Miyazawa Journal of Applied Physics 53,10, p6
839,1983).

Utilizing this phenomenon, a single nucleus of Si is formed with complete selectivity on minute silicon nitride scattered on SiO ₂ .
It was possible to grow single crystal Si there. At this time, the deposition conditions are vacuum degree of 10 ^-8 Torr or less, Si beam intensity of 9.7 × 10
¹⁴ atoms / cm ² · sec, substrate temperature 900 ℃ ~ 1000 ℃.

In this case, the reaction of SiO ₂ + Si → 2SiO ↑ results in SiO
A reaction product having a remarkably high vapor pressure is formed, and this evaporation causes the etching of SiO ₂ itself by Si.

On the other hand, the above-mentioned etching phenomenon does not occur on silicon nitride, but nucleation and deposition occur.

From this, as a deposition surface material with high nucleation density,
Similar effects can be obtained by using tantalum oxide (Ta ₂ O ₅ ), silicon nitride oxide (SiON) or the like other than silicon nitride. Therefore, a single crystal can be similarly grown by finely forming these materials as the nucleation base.

It should be noted that the combination of the deposition surface material, the nucleation base, and the deposition material described above is not limited to those shown in each of the above-described examples, and it is clear that a combination of materials having a sufficient nucleation density difference may be used. Is. Therefore, even in the case of a compound semiconductor such as GaAs or InP that can be selectively deposited, a single crystal or a single crystal group can be formed by the crystal growth method.

[Effects of the Invention] As described in detail above, in the method for manufacturing a semiconductor device according to the present invention, a high-quality single crystal layer is formed on an insulating material by a selective crystal growth method in which a single crystal is grown around a nucleation base. Therefore, a high performance insulated gate transistor can be manufactured. Therefore, an integrated circuit can be configured regardless of the material of the base substrate, and the floating capacitance is small, high-speed operation is possible, and an integrated circuit without a latch-up phenomenon can be provided at a low price.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a schematic sectional view of a second embodiment of a semiconductor device according to the present invention, FIGS. 3 (A) and (B). ) Is an explanatory view of the selective deposition method, FIG. 4 is a graph showing changes over time in nucleation density between the SiO ₂ deposition surface and the silicon nitride deposition surface, and FIGS. 5 (A) to 5 (D) are multilayers. FIG. 6 (A) and FIG. 6 (B) are perspective views of the substrate in FIGS. 5 (A) and (D), and FIGS. 7 (A) to 7 (). D) is a forming process diagram showing a second example of the manufacturing method of the multilayer structure, FIGS. 8A and 8B are perspective views of the substrate in FIGS. 7A and 7D, and FIG. (A)-(C) is a process chart showing a third example of a method for producing a multilayer structure, and FIGS. 10 (A) and (B) are the substrates in FIGS. 9 (A) and (C). FIG. 11 is a graph showing the relationship between the flow rate ratio of SiH ₄ and NH ₃ and the composition ratio of Si and N in the formed silicon nitride film. FIG. 12 is the Si / N composition ratio. And FIG. 13 is a graph showing the relationship between the implantation amount of Si ions and the nucleation density. 101 ... Substrate 102 ... Insulating layer 103 ... N-channel MOS transistor 104 ... P-channel MOS transistor 105 ... Nucleation base 106 ... Monocrystalline silicon layer 107 ... Gate insulating film 108 ... Gate electrode 111. Interlayer insulating layer 4 '... Desired substrate 5, 18, 20 ... Deposition surface material layer 6, 12 ... Nucleation base 8, 15, 17 ... Single crystal layer 14 ... Grain boundary

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/00 301 H01L 27/12 Z 27/08 331 29/78 618A 27/092 613A 27/12 27/08 321G 29/786

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device having an insulated gate transistor, wherein a substrate having an insulating layer on its surface is prepared, and a part of the surface of said insulating layer has a higher nucleation density than that of said insulating layer. A surface composed of an amorphous dissimilar material that is fine enough to form only a single nucleus that grows into a single crystal is formed, and the nuclei formed on the surface composed of the amorphous dissimilar material are grown by vapor phase growth. A single crystal semiconductor region is formed, and the source of the insulated gate transistor is formed in the semiconductor region.
A method of manufacturing a semiconductor device, which comprises forming a drain and a channel region. 2. A method of manufacturing a semiconductor device including a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor, wherein one of the p-channel and n-channel MOS transistors is formed on an insulating surface of a substrate. An insulating layer is formed on the surface of the substrate on which the one transistor is formed, and nuclei having a higher nucleation density than the insulating layer and growing into a single crystal are formed on a part of the surface of the insulating layer. A single-crystal semiconductor region is formed by providing a single plane of amorphous heterogeneous material that is sufficiently fine to be formed and growing the nuclei formed on the surface of the amorphous heterogeneous material by vapor phase growth. A contact in which the other source, drain, or channel region of the p- or n-channel MOS transistor is formed in the semiconductor region, and the one transistor and the other transistor are provided in the insulating layer. A method for manufacturing a semiconductor device, which comprises connecting through a hole.