JP4858671B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor element whose characteristics can be changed by receiving light.

  As a semiconductor element whose characteristics can be changed by receiving light, a MOS transistor, a nonvolatile memory having a floating gate electrode, and the like can be given. These semiconductor elements are exposed to light, particularly when mounted by a COG mounting method such as a bare chip, etc., and if a MOS transistor, on-off characteristics change, and if a non-volatile memory, the floating gate electrode. The injected electrons may escape. In order to prevent such fluctuations in the characteristics of the semiconductor element, a light shielding layer for preventing light from being irradiated is provided above the region where these devices are provided.

As one of the light shielding techniques, a technique disclosed in Japanese Patent Laid-Open No. 2003-124363 can be cited. In Japanese Patent Laid-Open No. 2003-124363, a memory cell array effective region and a light shielding region are provided so as to surround the outside, and the light shielding region has a via layer and a contact layer provided at different levels. Yes. The via layer and the contact layer are arranged in a zigzag pattern to suppress the entrance of light from the lateral and oblique directions.
JP 2003-124363 A

  However, even if a light shielding region is provided so as to surround the memory cell array effective region in order to reduce the ingress of light from the oblique direction and the horizontal direction, wiring such as a signal line from the memory cell array effective region is arranged outside the light shielding region. There is a need to extend it. Therefore, there are cases where the periphery of the memory cell array effective region cannot be completely surrounded by via layers and contact layers arranged in a staggered manner.

  In particular, an object of the present invention is to provide a semiconductor device that can reduce the ingress of light from a lateral direction and an obliquely upward direction and suppresses fluctuations in characteristics.

The semiconductor device of the present invention is
A semiconductor layer having a light-shielded region;
A semiconductor element provided in the semiconductor layer in the light shielding region;
A first interlayer insulating layer provided above the semiconductor element;
A plurality of first light shielding layers provided above the first interlayer insulating layer;
A second interlayer insulating layer provided at least above the first light shielding layer;
A second light-shielding layer having a predetermined pattern so as to be provided between the first light-shielding layers adjacent to each other and provided above the second interlayer insulating layer;
A via layer provided in an overlapping portion between the first light shielding layer and the second light shielding layer,
The via layer is provided with a groove-like opening continuous in a region where the first light shielding layer and the second light shielding layer overlap in the second interlayer insulating layer, and a conductive material is embedded in the opening.

  According to the semiconductor device of the present invention, the semiconductor element is covered with the first light-shielding layer provided thereabove and the second light-shielding layer provided at a different level from the first light-shielding layer. Therefore, the semiconductor element is not exposed to light from above, and a highly reliable semiconductor device can be provided without causing a change in characteristics. In particular, when the area to be shielded from light is large, it may not be covered with a single metal layer. However, according to the semiconductor device of the present invention, it is possible to sufficiently cover even a light-shielded region having a large area by arranging a plurality of metal layers of different levels alternately and having high reliability. An improved semiconductor device can be provided. Furthermore, since the via layer is provided in the groove-shaped hole provided in the overlapping portion of the first light-shielding layer and the second light-shielding layer, it is possible to reduce the entrance of light from an obliquely upward direction. As a result, a semiconductor device with higher reliability can be provided.

  The semiconductor device of the present invention can further take the following aspects.

  (A) In the semiconductor device of the present invention, the groove may be provided extending in a direction along a side surface facing the adjacent first light-shielding layer.

  According to this aspect, the via layer is provided at a position intersecting the direction in which the light enters in the overlapping portion of the first light shielding layer and the second light shielding layer. Therefore, it is possible to improve the light shielding property against light entering from the lateral direction and the obliquely upward direction, and to improve the reliability.

  (B) In the semiconductor device of the present invention, the semiconductor element may be a nonvolatile memory having a floating gate electrode.

  According to this aspect, it is possible to reduce the irradiation of light to the nonvolatile memory, and it is possible to provide a semiconductor device with improved charge retention characteristics.

  (C) In the semiconductor device of the present invention, the nonvolatile memory may be a one-layer gate type nonvolatile memory.

  According to this aspect, it is possible to provide a semiconductor device that is a gate-type nonvolatile memory and has improved charge retention characteristics.

  (D) The semiconductor device of the present invention may further include a light shielding wall provided around the light shielded region.

  According to this aspect, the light-shielded region is covered with the light-shielding wall at the periphery thereof, so that not only the upward direction but also the ingress of light from the lateral direction or the obliquely upward direction can be reduced. Therefore, it is possible to provide a semiconductor device in which variation in characteristics is suppressed and reliability is improved.

  (E) In the semiconductor device of the present invention, the light shielding wall is formed by embedding a groove-like opening provided in an interlayer insulating layer disposed around the semiconductor element and a conductive layer embedded in the opening. Can be.

(F) In the semiconductor device of the present invention, the light shielding region includes
Including a memory cell area and a logic area,
The overlapping portion may not be provided above the memory cell region.

  According to this aspect, the upper portion of the memory cell region is covered with the one light shielding layer. In a non-volatile memory having a floating gate electrode, charge may be lost due to light exposure (that is, data is erased). For this reason, it may be necessary to take strict measures against light shielding. In the present invention, since there is no overlapping region above the memory cell region, the probability of light reaching the memory cell array can be further reduced.

1. First Embodiment First, a semiconductor device according to a first embodiment will be described with reference to FIGS. FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view taken along the line II in FIG. FIG. 1 is a plan view showing the positional relationship between the light-shielded region 10A and a plurality of light-shielding layers provided above the light-shielded region 10A.

  As shown in FIG. 1, the semiconductor device of the present embodiment has a light-shielded region 10A in which various semiconductor elements (not shown) such as MOS transistors and nonvolatile memories are formed. Note that the light-shielded region 10A does not have to include all of the elements constituting the semiconductor element, and receiving the light among the elements constituting the semiconductor element affects the fluctuation of the characteristics of the semiconductor element. It is only necessary to include at least a portion to be provided (for example, when the semiconductor element is a MOS transistor, a gate electrode). Further, an element whose characteristics are not changed by light may be included.

  Above the light shielding region 10A, light shielding layers 44 and 54 provided in layers having different levels are provided. The light shielding area 10A is covered with at least one of the light shielding layer 44 and the light shielding layer 54. The light shielding layer 44 and the light shielding layer 54 are provided so as to partially overlap each other, and a continuous via layer 52 is provided in the overlapping portion instead of the hole shape.

  Next, a cross-sectional structure of the semiconductor device illustrated in FIG. 1 is described.

  As shown in FIG. 2, in the semiconductor device of the present embodiment, a light shielding region 10A is defined. Various semiconductor elements (not shown) are provided in the light-shielded region 10A. Interlayer insulating layers 20, 30, 40 and 50 are sequentially provided above the semiconductor layer 10 which is the light shielding region 10 </ b> A. As the interlayer insulating layers 20, 30, 40, 50, known insulating films such as oxide films and nitride films can be used. A plurality of light shielding layers 44 are provided between the interlayer insulating layer 40 and the interlayer insulating layer 50, and a plurality of light shielding layers 54 are provided above the interlayer insulating layer 50. That is, the light shielding layer 44 and the light shielding layer 54 are provided on the interlayer insulating layers 40 and 50 at different levels. The light shielding layer 54 is located between the adjacent light shielding layers 44 and has a pattern such that the light shielding layer 44 and the light shielding layer 54 partially overlap.

  As shown in FIG. 2, in the semiconductor device of the present embodiment, the light shielding region 10 </ b> A is covered with at least one of the light shielding layer 44 and the light shielding layer 54.

  A line-shaped via layer 52 provided in the interlayer insulating layer 50 is provided in an overlapping portion between the light shielding layer 44 and the light shielding layer 54. The via layer 52 is formed by embedding a conductive layer in a groove-shaped opening 52 a provided at a position where the light shielding layer 44 and the light shielding layer 54 overlap. In the semiconductor device of the present embodiment, as shown in FIG. 2, the light shielding layer 44 and the light shielding layer 54 are provided at all the overlapping portions. Further, the groove-shaped opening 52a extends in a direction along a side surface where one light shielding layer 44 and another light shielding layer 44 adjacent to the light shielding layer 44 are opposed to each other.

  According to the semiconductor device of the present embodiment, the light shielding layer 44 and the light shielding layer 54 provided at a different level from the light shielding layer 44 complement each other and cover the entire light shielding region 10A. Therefore, a semiconductor device with high reliability can be provided without exposing the semiconductor element to light and without causing fluctuations in characteristics. In particular, when the area to be shielded from light is large, it may not be covered with a single metal layer. However, according to the semiconductor device of the present embodiment, the light shielding layers 44 and 54 of different levels are used and alternately arranged when viewed in plan, thereby covering the entire surface even when the light shielded region 10A is large. be able to. Furthermore, since the via layer 52 is provided between the light shielding layer 44 and the light shielding layer 54, in addition to the light entering from above, the light entering from the lateral direction can be prevented. As a result, the light shielding effect can be further increased, and a semiconductor device with improved reliability can be provided.

2. Second Embodiment Next, a second embodiment will be described with reference to FIGS. The second embodiment is a case where a cell array of nonvolatile memory cells (hereinafter referred to as “memory cells”) is formed in the light-shielded region 10A. 3 and 4 are diagrams showing memory cells that are semiconductor elements provided in the light-shielded region 10A in the semiconductor device of the present embodiment. In the following description, first, the memory cell 120 provided in the light shielding region 10A will be described, and then the light shielding structure will be described.

  In the memory cell 120 included in the semiconductor device of the present embodiment, the control gate is an N-type impurity region in the semiconductor layer 10, and the floating gate electrode is formed of a conductive layer such as a single polysilicon layer (hereinafter, referred to as “a gate electrode”) It is sometimes called “a single-layer gated nonvolatile memory device”). 3 is a perspective view showing the memory cell, FIG. 4A is a cross-sectional view taken along the line II in FIG. 3, and FIG. 4B is taken along the line II-II in FIG. FIG. 4C is a cross-sectional view taken along line III-III in FIG.

  As shown in FIG. 3, the memory cell 120 in the present embodiment is provided in the P-type semiconductor layer 10. The semiconductor layer 10 is separated and defined by a device isolation insulating layer 12 into a first region 10X, a second region 10Y, and a third region 10Z. The first region 10X and the second region 10Y are provided in the P-type well 14. The third region 10 </ b> Z is provided in the N-type well 16. The first area 10X is a control gate section, the second area 10Y is a writing section, and the third area 10Z is an erasing section.

  An insulating layer 124 is provided on the semiconductor layer 10 in the first region 10X to the third region 10Z. On the insulating layer 124, a floating gate electrode 126 provided over the first to third regions 10X to 10Z is provided.

  Next, the cross-sectional structure of each region will be described. As shown in FIG. 4A, in the first region 10X, an insulating layer 124 provided on the well 14, a floating gate electrode 126 provided on the insulating layer 124, and a floating gate electrode 126 below the floating gate electrode 126. It has an N-type impurity region 134 provided in the semiconductor 10 and an N-type impurity region 128 provided adjacent to the impurity region 134. The N-type impurity region 134 serves as a control gate, and the impurity region 128 is electrically connected to the control gate line and serves as a contact portion for applying a voltage to the control gate.

  As shown in FIG. 4B, an N-channel MOS transistor 100B is provided in the second region 10Y in order to write to the memory cell 120. The N-channel transistor 100B includes an insulating layer 124 provided on the well 14, a floating gate electrode 126 provided on the insulating layer 124, and an impurity region 130 provided on the semiconductor layer 10. The impurity region 130 becomes a source region or a drain region.

  As shown in FIG. 4C, a P-channel transistor 100C is provided in the third region 10Z. The P-channel transistor 100C includes an insulating layer 124 provided on the N-type well 16, a floating gate electrode 126 provided on the insulating layer 124, and an impurity region 132 provided on the N-type well 16. And have. The impurity region 132 becomes a source region or a drain region.

  A plurality of memory cells 120 are arranged to form a memory cell array. FIG. 5 is a plan view schematically showing the semiconductor device according to the present embodiment, and FIG. 6 is a cross-sectional view taken along the line II of FIG.

  As shown in FIG. 5, in the semiconductor device according to the present embodiment, the light-shielded region 10A has two memory cell regions 10M and a logic region 10L provided at a position between the memory cell regions 10M. . A light shielding region 10B is provided around the light shielded region 10A so as to surround the light shielded region 10A.

  Two light shielding layers 34 and 44 are provided above the light shielding region 10A. The light shielding layers 34 and 44 are provided on the interlayer insulating layers 30 and 40 at different levels, respectively. As shown in FIG. 5, the light shielding region 10 </ b> A is covered with at least one of the light shielding layer 34 and the light shielding layer 44.

  Next, a cross-sectional structure of the semiconductor device of the present embodiment will be described with reference to FIG. As shown in FIG. 6, the light shielded area 10A includes a memory cell area 10M and a logic area 10L. A plurality of memory cells 120 are provided in the memory cell region 10M. The logic region 10L is provided with a MOS transistor (not shown) for forming a logic circuit.

  Interlayer insulating layers 20, 30, 40, and 50 are sequentially provided above the memory cell 120 and the MOS transistor (not shown). Wiring layers 24, 34, and 44 are provided on the interlayer insulating layers 20, 30, and 40, respectively. A plurality of wiring layers 34 are provided at regular intervals, and the wiring layer 44 provided thereon is positioned at least between the adjacent wiring layers 34 and further has a partially overlapping pattern. .

  In a region where the wiring layers 34 and 44 overlap, a line-shaped via layer 42 is provided in the interlayer insulating layer 40. At this time, the via layer 42 forms a line shape in a direction parallel to the side surfaces of the adjacent light shielding layers 44 facing each other. The via layer 42 is provided in the entire region where the wiring layers 34 and 44 overlap.

  Next, the light shielding region 10B provided around the light shielding region 10A will be described. FIG. 5 shows only a part of the memory cell array, and thus only a part of the light shielding region 10B is shown. The light shielding region 10B is provided so as to surround the light shielding region 10A. Can be. In the present embodiment, a case will be described in which a light shielding wall 70 is provided in the light shielding region 10B as a light shielding structure for suppressing the entrance of light from the lateral direction and the obliquely upward direction.

  As shown in FIGS. 5 and 6, interlayer insulating layers 20, 30, 40, and 50 are sequentially provided on the semiconductor layer 10 in the light shielding region 10 </ b> B. On the interlayer insulating layers 20, 30, 40, 50, metal layers 28, 38, 48 having a predetermined pattern are provided, respectively. The metal layers 28, 38, and 48 are formed in the same process as the wiring layer provided on the same interlayer insulating layer in the light shielded region 10A. In the present embodiment, even in the same metal layer, a different reference numeral is used for a portion located in the light-shielded region 10A and a portion located in the light-shielded region 10B. For example, as shown in FIG. 6, the wiring layer 44 and the metal layer 48 are continuous layers, but different reference numerals are given depending on the positions. The metal layer 28 and the semiconductor layer 10 are connected by a contact layer 26, and via layers 36 and 46 are provided between the metal layers 28 and 38 and between the metal layers 38 and 48, respectively. . At this time, the contact layer 26 and the via layers 36 and 46 form a ring shape. That is, a continuous groove provided so as to surround the light-shielded region 10A is formed, and the conductive layer is embedded in this groove. Therefore, the light shielding wall 70 is constituted by the contact layer 26, the via layers 36, 46, and the metal layers 28, 38, 48.

(Modification)
Next, a modification of the semiconductor device according to the second embodiment will be described with reference to FIG. The semiconductor device according to the modification is an example in which the total number and pattern of each wiring layer formed above the light-shielded region 10A are different. FIG. 7 shows a cross section corresponding to FIG. 6, and in the following description, differences from the above-described embodiment will be described.

  As shown in FIG. 7, the semiconductor device according to this modification includes a light-shielded region 10A including a memory cell region 10M and a logic region 10L. A light shielding region 10B is provided outside the light shielding region 10A.

  On the semiconductor element such as the memory cell 120, interlayer insulating layers 20, 30, 40, 50, and 60 are sequentially formed. In the light shielding region 10A, wiring layers 34, 44, and 54 having predetermined patterns are provided on the interlayer insulating layers 30, 40, and 50, respectively. These three wiring layers 34, 44, 54 have patterns that complement each other so that one of the wiring layers covers the upper side of the light shielded region 10 </ b> A when viewed in plan. For example, the wiring layer 34 has a pattern that complements a gap generated by arranging two wiring layers 44 next to each other.

  Via layers 42 and 52 are provided in regions where the wiring layer 34 and the wiring layer 44 and the wiring layer 44 and the wiring layer 54 overlap, respectively. The via layers 42 and 52 are similar to the above-described embodiment and have a continuous line shape. That is, the via layers 42 and 52 are formed by groove-shaped openings 42a and 52a provided in the interlayer insulating layers 40 and 50, and a conductive layer embedded in the openings 42a and 52a.

  Next, advantages of the semiconductor device of this embodiment will be described below.

  (1) In the semiconductor device of this embodiment, the entire upper surface of the light-shielded region 10A is covered by controlling the patterns of the wiring layer 34 and the wiring layer 44. The single-layer gate type nonvolatile memory provided in the light-shielded region 10A of the present embodiment has a floating gate electrode area of the control gate portion (first region) and write and erase regions (in order to obtain a capacitance ratio). The pattern has such a large difference from the area of the floating gate electrode in the second and third regions). Therefore, the floating gate electrode 126 has a portion where the width and length are locally small or large. In such a case, the entire floating gate electrode 126 may not be covered even if the pattern of the wiring layer is simply increased within the allowable design rule range. However, in this embodiment, the entire surface of the floating gate electrode 126 having a non-uniform shape can be covered by controlling the patterns of the wiring layers 34 and 44 at different levels. As a result, a semiconductor device with improved charge retention characteristics and improved reliability can be provided.

  In addition, when a region requiring a large area is covered with a single metal layer, uniform etching may not be performed during etching. By forming the light shielding structure using the wiring layers 34 and 44 at different levels as in the semiconductor device of the present embodiment, the entire light shielding region 10A having a large area can be covered. As a result, the light shielding effect can be further improved, and a semiconductor device with improved reliability can be provided.

  (2) Further, since the via layer 42 is provided in the overlapping region with the metal layers 34 and 44, it is possible to suppress the entrance of light from the lateral direction or obliquely upward direction, and the light shielding effect is further improved. A semiconductor device can be provided. When it is desired to obtain a light shielding effect in the horizontal direction or obliquely upward direction with only the light shielding layer provided above, the entire size of the light shielding layer provided above must be larger than the light shielding region. The device may not be sufficiently miniaturized. However, according to this aspect, by providing the via layer 42 between the light shielding layers 34 and 44, the same light shielding effect can be obtained even if the area to be extended is smaller than the size of the light shielding region 10A. . In other words, a semiconductor device with improved reliability while miniaturization can be provided.

  (3) Further, by providing the light shielding region 10B outside the light shielded region 10A, it is possible to further improve the suppressive force of light entering from the lateral direction. As a result, a semiconductor device with improved reliability can be provided.

  The present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention. For example, in the first embodiment, the light-shielding layers provided at two different levels are illustrated, but the present invention is not limited to this, and three or more types of layers are provided alternately when viewed in plan. May be realized. In the above-described embodiment, the case where the contact layer 26 and the via layers 36 and 46 are provided in the respective interlayer insulating layers in order to form the light shielding wall 70 has been described. However, the present invention is not limited to this. For example, the light shielding wall 70 may be formed by providing a groove-shaped opening penetrating the interlayer insulating layers 20, 30, 40 around the light-shielded region 10A and embedding a conductive layer in the opening.

FIG. 2 is a plan view schematically showing the semiconductor device according to the first embodiment. Sectional drawing along the II line | wire of FIG. The perspective view which shows typically the structure of the non-volatile memory provided in the semiconductor device concerning 2nd Embodiment. (A) is sectional drawing along the II line of FIG. 3, (B) is sectional drawing along the II-II line, (C) is sectional drawing along the III-III line It is. The top view which shows typically the semiconductor device concerning 2nd Embodiment. Sectional drawing along the II line | wire of FIG. Sectional drawing which shows typically the semiconductor device concerning a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10A ... Light-shielding area | region, 10B ... Light-shielding area | region, 10M ... Memory cell area | region, 10L ... Logic area | region, 12 ... Element isolation insulating layer, 14 ... P-type well, 16 ... N-type well, 26 ... Contact layer, 28, 38, 48 ... metal layer, 36, 42, 46, 52 ... via layer, 34, 44, 54 ... light shielding layer (wiring layer), 20, 30, 40, 50, 60 ... interlayer insulating layer, 70: light shielding wall, 120: memory cell, 124: insulating layer, 126: floating gate electrode, 128, 130, 132, 134 ... impurity region

Claims (7)

A semiconductor layer having a light-shielded region;
A semiconductor element provided in the semiconductor layer in the light shielding region;
A first interlayer insulating layer provided above the semiconductor element;
A plurality of first light shielding layers provided above the first interlayer insulating layer;
A second interlayer insulating layer provided at least above the first light shielding layer;
A second light-shielding layer having a predetermined pattern so as to be provided between the first light-shielding layers adjacent to each other and provided above the second interlayer insulating layer;
A via layer provided in an overlapping portion between the first light shielding layer and the second light shielding layer,
The via layer, of the second interlayer insulating layer, the continuous groove-like opening between the first light-shielding layer in the region where the overlap second light-shielding layer provided, Ri Na and conductive material is embedded in the opening ,
The semiconductor device , wherein the via layer and the overlapping portion of the first light shielding layer and the second light shielding layer extend in the same direction . In claim 1,
The said groove | channel is a semiconductor device extended | stretched and provided in the direction along the opposing side surface in the said 1st light shielding layer adjacent. In claim 1 or 2,
The semiconductor device is a non-volatile memory having a floating gate electrode. In claim 3,
The non-volatile memory is a semiconductor device which is a one-layer gate type non-volatile memory. In any of claims 1 to 4,
The semiconductor device further includes a light shielding wall provided around the light shielded region. In claim 5,
The light shielding wall includes a groove-like opening provided in an interlayer insulating layer disposed around the semiconductor element, and a contact layer or via layer formed by embedding a conductive layer in the opening. . In any of claims 3 to 6,
In the light shielding area,
Including a memory cell area and a logic area,
The semiconductor device, wherein the overlapping portion is not provided above the memory cell region.

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