JP5029844B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor element whose characteristics can be changed by receiving light.

  As a semiconductor element whose characteristics can be changed by receiving light, a MOS transistor, a nonvolatile memory having a floating gate electrode, and the like can be given. These semiconductor elements are exposed to light, particularly when mounted by a COG mounting method such as a bare chip, etc., and if a MOS transistor, on-off characteristics change, and if a non-volatile memory, the floating gate electrode. The injected electrons may escape. In order to prevent such fluctuations in the characteristics of the semiconductor element, a light shielding layer for preventing light from being irradiated is provided above the region where these devices are provided.

As one of the light shielding techniques, a technique disclosed in Japanese Patent Laid-Open No. 2003-124363 can be cited. In Japanese Patent Laid-Open No. 2003-124363, a memory cell array effective region and a light shielding region are provided so as to surround the outside, and the light shielding region has via layers and contact layers provided at different levels. ing. The via layer and the contact layer are arranged in a zigzag pattern to suppress the entrance of light from the lateral and oblique directions.
JP 2003-124363 A

  However, even if a light shielding region is provided so as to surround the memory cell array effective region in order to reduce the ingress of light from the oblique direction and the horizontal direction, wiring such as a signal line from the memory cell array effective region is arranged outside the light shielding region. There is a need to extend it. Therefore, there are cases where the periphery of the memory cell array effective region cannot be completely surrounded by via layers and contact layers arranged in a staggered manner.

  In particular, an object of the present invention is to provide a semiconductor device that can reduce the ingress of light from a lateral direction and an oblique direction and suppresses fluctuations in characteristics.

The semiconductor device of the present invention is
A first light-shielded region including a first semiconductor element and defined by a first light-shielding wall provided around the first semiconductor element;
A second light-shielded region that includes a second semiconductor element, is defined by a second light-shielding wall provided around the second semiconductor element, and is provided at a position adjacent to the first light-shielded region;
A first opening provided in the first light shielding wall;
A second opening provided on the second light shielding wall and positioned opposite to the first opening is connected to the first semiconductor element, and is drawn out of the first light shielding region from the first opening. A first wiring layer;
A second wiring layer connected to the second semiconductor element and led out of the second light-shielded region from the second opening;
And at least a light-shielding film provided above a region sandwiched between the first light-shielded region and the second light-shielded region.

  According to the semiconductor device of the present invention, it is possible to provide a semiconductor device with further improved light shielding properties. Usually, a semiconductor element whose characteristics can be changed by light is provided with a light shielding film above the semiconductor element, or a contact layer or a via layer is arranged around the semiconductor element in order to prevent exposure to light. It has a light shielding structure such as blocking light from the lateral direction. However, wirings, signal lines, and the like are connected to various semiconductor elements, and it is necessary to draw these wirings to the outside of the light shielding structure. In that case, a region (opening) where a part of the via layer or contact layer is not provided around the semiconductor element is secured, and the wiring may be drawn out from the opening, but light enters from the opening. This may affect the characteristics of the semiconductor element. However, according to the semiconductor device of the present invention, the respective apertures (the first aperture and the second aperture) of the adjacent light-shielded regions are provided at positions facing each other, and the first aperture and the second aperture are provided. A light shielding film is provided above the region sandwiched between the two. Therefore, the area where the light shielding film is required can be reduced to efficiently provide the light shielding film, and the entrance of light from the aperture can be suppressed. As a result, variation in characteristics can be reduced and a semiconductor device with improved reliability can be provided.

  The semiconductor device of the present invention can further take the following aspects.

  (A) In the semiconductor device of the present invention, the light shielding film may be further provided above the first light shielding region and the second light shielding region.

  (B) In the semiconductor device of the present invention, the light shielding wall includes a groove-shaped opening provided in an interlayer insulating layer disposed around the semiconductor element, and a contact in which a conductive layer is embedded in the opening. Layers or via layers can be included.

  (C) In the semiconductor device of the present invention, the first wiring layer may be a plurality of wiring layers, and the opening may be provided for each wiring layer.

  (D) In the semiconductor device of the present invention, the second wiring layer may be a plurality of wiring layers, and the opening may be provided for each wiring layer.

  According to this aspect, since it is sufficient to provide an opening having a minimum width according to each wiring layer, it is possible to reduce the entry of light.

  (E) In the semiconductor device of the present invention, the first opening may be provided on one side surface of the first light shielding region.

  (F) In the semiconductor device of the present invention, the second opening may be provided on one side surface of the second light shielding region.

  According to this aspect, even when there are a plurality of apertures, the positions can be combined on one side. Therefore, the area of the light shielding film covering the upper part of the opening can be reduced.

  (G) In the semiconductor device of the present invention, the semiconductor element may be a nonvolatile memory having a floating gate electrode.

  According to this aspect, a semiconductor device with improved charge retention characteristics can be provided.

  (H) In the semiconductor device of the present invention, the nonvolatile memory may be a one-layer gate type nonvolatile memory.

  Next, an example of an embodiment of the semiconductor device of the present invention will be described. A semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 1 is a perspective view schematically showing a nonvolatile memory cell (hereinafter also referred to as “memory cell”) provided in a light-shielded region of the semiconductor device according to the present embodiment. 2A is a cross-sectional view taken along line II in FIG. 1, FIG. 2B is a cross-sectional view taken along line II-II in FIG. 1, and FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. 3 is a plan view schematically showing the semiconductor device according to the present embodiment, FIG. 4 is a cross-sectional view taken along the line II in FIG. 3, and FIG. It is sectional drawing along the II line.

  In the following description, first, the memory cell 120 provided in the light shielding region 10A will be described, and then a specific light shielding structure will be described.

  In the memory cell 120 included in the semiconductor device of the present embodiment, the control gate is an N-type impurity region in the semiconductor layer 10, and the floating gate electrode is formed of a conductive layer such as a single polysilicon layer (hereinafter, referred to as “a gate electrode”) It is sometimes called “a single-layer gated nonvolatile memory device”).

  As shown in FIG. 1, the memory cell 120 in this embodiment is provided in a P-type semiconductor layer 10. The semiconductor layer 10 is separated and defined by a device isolation insulating layer 12 into a first region 10X, a second region 10Y, and a third region 10Z. The first region 10X and the second region 10Y are provided in the P-type well 14. The third region 10 </ b> Z is provided in the N-type well 16. The first area 10X is a control gate section, the second area 10Y is a writing section, and the third area 10Z is an erasing section.

  An insulating layer 124 is provided on the semiconductor layer 10 in the first region 10X to the third region 10Z. On the insulating layer 124, a floating gate electrode 126 provided over the first to third regions 10X to 10Z is provided.

  Next, the cross-sectional structure of each region will be described. As shown in FIG. 2A, in the first region 10X, an insulating layer 124 provided on the well 14, a floating gate electrode 126 provided on the insulating layer 124, and a floating gate electrode 126 below the floating gate electrode 126. It has an N-type impurity region 134 provided in the semiconductor 10 and an N-type impurity region 128 provided adjacent to the impurity region 134. The N-type impurity region 134 serves as a control gate, and the impurity region 128 is electrically connected to the control gate line and serves as a contact portion for applying a voltage to the control gate.

  As shown in FIG. 2B, an N-channel MOS transistor 100B is provided in the second region 10Y in order to write to the memory cell 120. The N-channel transistor 100B includes an insulating layer 124 provided on the well 14, a floating gate electrode 126 provided on the insulating layer 124, and an impurity region 130 provided on the semiconductor layer 10. The impurity region 130 becomes a source region or a drain region.

  As shown in FIG. 2C, a P-channel transistor 100C is provided in the third region 10Z. The P-channel transistor 100C includes an insulating layer 124 provided on the N-type well 16, a floating gate electrode 126 provided on the insulating layer 124, and an impurity region 132 provided on the N-type well 16. And have. The impurity region 132 becomes a source region or a drain region.

  Next, the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 3 shows the arrangement of the floating gate electrode 126 and the impurity regions 128, 130, and 132 among the components of the memory cell 120. If necessary, the lower layer is indicated by a dotted line, the upper layer is indicated by a solid line, and the reference numerals of the lower members are indicated by parentheses.

  As shown in FIG. 3, in the semiconductor device according to the present embodiment, the first light-shielded region 10A and the second light-shielded region 10A ′ are arranged adjacent to each other. The first light shielding area 10 </ b> A includes the memory cell 120 and is an area defined by the light shielding wall 50 provided around the memory cell 120. Similarly, the second light-shielded region 10A ′ is a region that includes the memory cell 120 ′ and is defined by the light-shielding wall 50 ′. Various wirings connected to the drive circuit are provided in a region sandwiched between the first light-shielded region 10A and the second light-shielded region 10A ′. In the following description, a region sandwiched between the first light-shielded region 10A and the second light-shielded region 10A ′ will be referred to as a wiring region 10B.

  First, the first light-shielded region 10A and the second light-shielded region 10A ′ will be described. The structures of the memory cells 120 and 120 'provided in each are as described above. Next, the structure of the light shielding walls 50 and 50 'will be described with reference to FIG. As shown in FIG. 4, an insulating layer 124 and a floating gate electrode 126 are sequentially provided on the semiconductor layer 10, and an impurity region 134 is provided in the semiconductor layer 10. Interlayer insulating layers 20, 30, and 40 are sequentially provided on the memory cell 120. A first metal layer 28 is provided on the interlayer insulating layer 20 and around the memory cell 120. The first metal layer 28 and the semiconductor layer 10 are connected by a contact layer 26. The contact layer 26 serves to block light from entering the memory cell 120 from the lateral direction and obliquely upward. That is, in the semiconductor device of the present embodiment, the light shielding wall 50 is constituted by the contact layer 26.

  As shown in FIG. 3, the light shielding walls 50 and 50 ′ are provided around the memory cells 120 and 120 ′, but do not completely cover the periphery. Specifically, there is a portion around the memory cells 120 and 120 ′ where the first metal layer 28 and the contact layer 26 are not provided, and these portions become the openings 52 and 52 ′. It is.

  The opening 52 of the first light-shielded region 10A and the opening 52 ′ of the second light-shielded region 10A ′ are provided at opposing positions. That is, the side surface in which the opening 52 of the first light-shielded region 10A is provided and the side surface in which the opening 52 ′ is provided in the second light-shielded region 10A ′ are opposed to each other. In addition, a plurality of signal lines 24a, 24b, and 24c are led out from the first light-shielded region 10A, and all of the plurality of signal lines 24a, 24b, and 24c are led out in the same direction. The same direction means that it is drawn out from the opening 52 provided on one side surface of the light shielding region 10A. Similarly, a plurality of signal lines 24a ′, 24b ′, and 24c ′ are also drawn from the second light-shielded region 10A ′ through an opening 52 provided on one side surface of the second light-shielded region 10A.

  At this time, since the opening 52 and the opening 52 ′ are provided to face each other, the plurality of wiring layers drawn out from the respective light-shielded regions 10A and 10A ′ are eventually connected to the wiring region 10B. Will be placed together.

  In FIG. 3, each of the signal lines 24a, 24b, and 24c has an opening, but the present invention is not limited to this. One large opening 52 is provided, and all three signal lines are formed from the opening 52. It is also possible to take a form that draws out.

  A light shielding film 60 is provided above the first light shielded region 10A, the wiring region 10B, and the second light shielded region 10A ′ so as to cover the entire surface. The light shielding film 60 is preferably a single continuous film.

  Next, the cross-sectional structure will be described with reference to FIG. 5 while focusing on the portion from which the signal line is drawn. As described above, the semiconductor device according to the present embodiment includes the first light-shielded region 10A, the second light-shielded region 10A ′, and the wiring region 10B provided between them. Memory cells 120 are provided in the semiconductor layer 10 in the first light-shielded region 10A and the second light-shielded region 10A ′. In the first light-shielded region 10 </ b> A and the second light-shielded region 10 </ b> A ′, the interlayer insulating layer 20 is provided on the memory cell 120. A first metal layer 24 a is provided on the interlayer insulating layer 20. The first metal layer 24 a is a signal line of the memory cell 120 and is electrically connected to the impurity region 132 of the memory cell 120 via the contact layer 22.

  In the wiring region 10B, wiring layers 42 and 44 are provided on the wiring layer 40 formed in the same process as the formation of the floating gate electrode 126 and the interlayer insulating layers 20 and 30, respectively. The wiring layers 40, 42 and 44 are wirings connected to the memory cell 120 and connected to a control circuit (not shown) of the memory cell array. As shown in FIG. 5, in the semiconductor device of the present embodiment, the signal line 24a is led out to the wiring region 10B and connected to the wiring layer 40 through the via layer 41a. The wiring layer 40 is connected to the wiring layer 42 via the via layer 41b, and this wiring layer 42 is finally connected to the control circuit.

  According to the semiconductor device of the present embodiment, it is possible to provide a semiconductor device with improved light shielding properties. In general, a nonvolatile memory having a floating gate electrode has a problem in that charge retention characteristics are deteriorated, for example, the charge injected into the floating gate electrode 126 is lost by receiving light. Therefore, in order to prevent the memory cell 120 from being exposed to light, a light-shielding film is provided above the memory cell 120, or a contact layer or a via layer is disposed around the memory cell 120 so that light from the lateral direction can be obtained. It has a light shielding structure such as blocking light. However, various signal lines need to be connected to the memory cell, and these signal lines need to be drawn to the outside of the light shielding structure. In that case, a region (opening) where a part of the via layer or contact layer is not provided around the semiconductor element is secured, and the wiring may be drawn out from the opening, but light enters from the opening. This may affect the charge retention characteristics. However, according to the semiconductor device of the present embodiment, the openings (the first opening 52 and the second opening 52 ') of the adjacent first light-shielded region 10A and the second light-shielded region 10A' are adjacent to each other. A light shielding film 60 is provided above the region (wiring region 10B) that is provided at the opposing position and sandwiched between the first opening 52 and the second opening 52 ′. Therefore, the area where the light shielding film 60 is required can be reduced, the light shielding film 60 can be efficiently provided, and entry of light from the openings 52 and 52 'can be suppressed. As a result, variation in characteristics can be reduced and a semiconductor device with improved reliability can be provided.

  Further, in the semiconductor device of the present embodiment, the three signal lines 24a, 24b, and 24c are led out to the outside of the light-shielded region 10A, but an opening 52 is provided in each of the signal lines 24a, 24b, and 24c. Yes. Therefore, the gap through which light can enter can be made as small as possible, and the entry of light can be reduced. As a result, it can contribute to the improvement of reliability.

  Note that the present invention is not limited to the above-described embodiment, and can be appropriately modified within the scope of the gist of the present invention. For example, in the present embodiment, the case where one memory cell 120, 120 ′ is provided in each of the first light-shielded region 10A and the second light-shielded region 10A ′ is illustrated, but the present invention is not limited to this. A plurality of memory cells 120 may be provided in the light-shielded regions 10 </ b> A and 10 </ b> A ′, and other devices such as a selection transistor may be included in addition to the memory cells 120. Moreover, although the case where the opening 52 was provided in each of signal wire | line 24a, 24b, 24c was shown, it is not limited to this. For example, the signal lines 24a, 24b, and 24c may be pulled out from one large opening 52. In this case, there is an advantage that it is not necessary to provide a plurality of apertures 52 finely, and the pattern of the light shielding wall 50 can be simplified.

The perspective view which shows typically the structure of the non-volatile memory provided in the semiconductor device concerning this Embodiment. (A) is sectional drawing along the II line of FIG. 1, (B) is sectional drawing along the II-II line of FIG. 1, (C) is III-III of FIG. It is sectional drawing along a line The top view which shows typically the semiconductor device concerning this Embodiment. Sectional drawing along the II line | wire of FIG. Sectional drawing along the II line | wire of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10A ... Light-shielded area | region, 10B ... Wiring area | region, 12 ... Element isolation insulation layer, 14 ... P-type well, 16 ... N-type well 20, 30, 40 ... Interlayer insulation layer, 22, 26 ... contact layer, 24, 28 ... metal layer, 24a, 24b, 24c ... signal line, 40, 42, 44 ... wiring layer, 41a, 41b ... via layer, 50 ... light shielding wall, 52 ... aperture, 60 ... light shielding film , 120 ... memory cell, 124 ... insulating layer, 126 ... floating gate electrode, 128, 130, 132, 134 ... impurity region,

Claims (14)

A first semiconductor element;
A first conductive layer provided around the first semiconductor element and having a plurality of apertures;
A plurality of wiring layers electrically connected to the first semiconductor element and led out of the first region defined by the first conductive layer from each of the plurality of openings;
A second semiconductor element;
A second conductive layer provided around the second semiconductor element and having a plurality of apertures;
A plurality of wiring layers electrically connected to the second semiconductor element and led out from a second region defined by the second conductive layer from each of the plurality of openings ;
Each of the plurality of openings of the first conductive layer is opposed to each of the plurality of openings of the second conductive layer;
A semiconductor device, wherein a light shielding film is provided at least above the entire surface of the third region between the first region and the second region. A first semiconductor element;
A first conductive layer provided around the first semiconductor element and having a first opening, a second opening, and a third opening;
A first wiring layer electrically connected to the first semiconductor element and drawn out of the first region defined by the first conductive layer from the first opening;
A second wiring layer electrically connected to the first semiconductor element and led out of the first region from the second opening;
A third wiring layer electrically connected to the first semiconductor element and led out of the first region from the third opening;
A second semiconductor element;
A second conductive layer provided around the second semiconductor element and having a fourth opening, a fifth opening, and a sixth opening;
A fourth wiring layer electrically connected to the second semiconductor element and drawn out of the second region defined by the second conductive layer from the fourth opening;
A fifth wiring layer electrically connected to the second semiconductor element and led out of the second region from the fifth opening;
A sixth wiring layer electrically connected to the second semiconductor element and led out of the second region from the sixth opening,
The first opening is opposed to the fourth opening,
The second opening is opposed to the fifth opening,
The third opening is opposed to the sixth opening,
A semiconductor device, wherein a light shielding film is provided at least above the entire surface of the third region between the first region and the second region. In claim 1 or 2 ,
The semiconductor device , wherein the light shielding film is further provided over the entire surface of the first region. In claim 3 ,
The semiconductor device , wherein the light shielding film is further provided above the entire surface of the second region. In any one of Claims 1 thru | or 4 ,
The first conductive layer has a first via layer;
The semiconductor device, wherein the second conductive layer has a second via layer. In claim 5 ,
The first conductive layer further includes a first metal layer provided on the first via layer,
The second conductive layer further includes a second metal layer provided on the second via layer. In any one of Claims 1 thru | or 4 ,
The first conductive layer has a first contact layer;
The semiconductor device, wherein the second conductive layer has a second contact layer. In claim 7 ,
The first conductive layer further includes a first metal layer provided on the first contact layer,
The semiconductor device, wherein the second conductive layer further includes a second metal layer provided on the second contact layer. In any one of Claims 1 thru | or 8 .
The semiconductor device, wherein the light shielding film is a continuous film. In any one of Claims 1 thru | or 9 ,
The first semiconductor element is a first nonvolatile memory;
The semiconductor device, wherein the second semiconductor element is a second nonvolatile memory. In claim 10 ,
The first nonvolatile memory has a first floating gate electrode,
The second non-volatile memory is a semiconductor device having a second floating gate electrode. In any one of Claims 1 thru | or 9 ,
The first semiconductor element is a first gate-type first nonvolatile memory,
The semiconductor device, wherein the second semiconductor element is a single gate type second nonvolatile memory. A first semiconductor element;
A first conductive layer provided around the first semiconductor element and having a first opening;
A plurality of wiring layers electrically connected to the first semiconductor element and led out of the first region defined by the first conductive layer from the first opening;
A second semiconductor element;
A second conductive layer provided around the second semiconductor element and having a fourth opening;
A plurality of wiring layers electrically connected to the second semiconductor element and led out of the second region defined by the second conductive layer from the fourth opening,
The first opening of the first conductive layer is opposed to the fourth opening of the second conductive layer,
A semiconductor device, wherein a light shielding film is provided at least above the entire surface of the fourth region between the first opening and the fourth opening. A first semiconductor element;
A first conductive layer provided around the first semiconductor element and having a first opening, a second opening, and a third opening;
A first wiring layer electrically connected to the first semiconductor element and drawn out of the first region defined by the first conductive layer from the first opening;
A second wiring layer electrically connected to the first semiconductor element and led out of the first region from the second opening;
A third wiring layer electrically connected to the first semiconductor element and led out of the first region from the third opening;
A second semiconductor element;
A second conductive layer provided around the second semiconductor element and having a fourth opening, a fifth opening, and a sixth opening;
A fourth wiring layer electrically connected to the second semiconductor element and drawn out of the second region defined by the second conductive layer from the fourth opening;
A fifth wiring layer electrically connected to the second semiconductor element and led out of the second region from the fifth opening;
A sixth wiring layer electrically connected to the second semiconductor element and led out of the second region from the sixth opening,
The first opening is opposed to the fourth opening,
The second opening is opposed to the fifth opening,
The third opening is opposed to the sixth opening,
At least a fourth region between the first aperture and the fourth aperture; a fifth region between the second aperture and the fifth aperture; and the third aperture and the sixth aperture. A semiconductor device in which a light shielding film is provided above the entire surface of the sixth region.

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