JPH0945774A - Film semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise chemical resistance and insulation breakdown strength of crossed wiring and get a reliable film semiconductor device where the occurrence of defects is suppressed by making a composite insulating pad, which is interposed in the crossed lower wiring and upper wiring, contain at least a lower insulating film, a middle semiconductor film, and an upper insulating film, and doing other such like matters. SOLUTION: This is a film semiconductor device where at least a film transistor 2 and wiring part 3 are stacked on an insulating substrate 1, and the wiring part 3 has a lower wiring 4 and an upper wiring 5 patterned on the insulating substrate 1 and a composite insulating pad 6 interposed at least in the crossing of both wirings 4 and 5. And, the composite insulating pad 6 contains at least a lower insulating film 7, a middle semiconductor film 8, and an upper insulating film 9. For example, the film transistor 2 a gate electrode 11 contained in one part of the lower semiconductor film 8, a gate insulating film 12 in the same layer as the lower insulating film 7, an active layer 13 consisting of the middle semiconductor film 8, and a channel protective film 14 in the same layer as the upper insulating film 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device in which at least a thin film transistor and a wiring portion are integrally formed on an insulating substrate. More specifically, it relates to an electrically insulating structure at the intersection of the wiring structure.

[0002]

2. Description of the Related Art A thin film semiconductor device is suitable for, for example, a drive substrate of an active matrix type display device using a thin film transistor as a switching element, and has been actively developed in recent years. The liquid crystal display device of the active matrix system is rapidly spreading as a display of a notebook personal computer, a television, a car navigation display and the like. A thin film transistor used as a switching element generally has a bottom gate type (inverse stagger type) structure, in which a gate electrode is arranged on the substrate side of the gate insulating film, while the active layer of the semiconductor thin film, source electrode, and drain are arranged on the opposite side. The electrodes are arranged.

[0003]

Problems to be solved by the conventional thin film semiconductor device will be briefly described with reference to FIG.
4A shows an intersection of the wiring portions 101, and FIG. 4B shows a thin film transistor 102 having an inverted stagger structure.
On the transparent insulating substrate 103, the metal gate wiring 104 and the gate electrode 105 which is a part thereof are patterned. Plasma C overlaid on the metal gate wiring 104
The gate insulating film 106 and the semiconductor thin film 107 are formed by VD or the like.
Are continuously formed. The semiconductor thin film 107 is subjected to polycrystallization treatment or the like as necessary. Further, the semiconductor thin film 107 is patterned in an island shape, and the thin film transistor 10
Processed into two active layers. A channel protection film 108 is patterned on the active layer to protect the channel region of the thin film transistor 102. This channel protective film 1
The source region S and the drain region D of the thin film transistor are formed in the semiconductor thin film 107 by ion-doping impurities with high concentration using 08 as a mask. The implanted impurities are activated by laser annealing or the like.
Then, the signal wiring 109 connected to the source region S is patterned. The pixel electrode 110 is also patterned and electrically connected to the drain region D of the thin film transistor 102.

As shown in FIGS. 4A and 5, the lower gate wiring (lower wiring) 104 and the upper signal wiring (upper wiring) 109 intersect each other. However, only the gate insulating film 106 is present at the intersection of both wirings. Gate wiring 10 having a predetermined film thickness at the intersection
In general, the gate insulating film 106 formed on the gate wiring 4 is not faithfully deposited along the cross-sectional shape of the gate wiring 104, and the stepped portion covers the gate wiring 104 with some constriction. There is. When the signal wiring 109 crosses over such a shape, when a high voltage is applied during driving between the lower layer wiring and the upper layer wiring, the electric field concentrates on the thin constricted portion of the gate insulating film 106, and in some cases, This may lead to short circuit defects between the upper and lower wiring. In particular, when the gate insulating film 106 has many defects such as pinholes, short-circuit defects are likely to occur when exposed to wet treatment with a hydrofluoric acid-based etching solution or the like in a later step. When such a defect occurs in the screen area of the display thin film semiconductor device, a cross-shaped image defect is caused. Further, if a short circuit defect occurs in the peripheral drive circuit, it causes a signal transfer failure.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a thin film semiconductor device which is less likely to cause a short circuit failure of wiring between layers and has excellent reliability. The following measures have been taken in order to achieve this object. That is, in the thin film semiconductor device according to the present invention, at least a thin film transistor and a wiring portion are integrally formed on an insulating substrate as a basic configuration. The wiring portion has a lower layer wiring and an upper layer wiring which are pattern-formed on the insulating substrate, and a composite insulating pad interposed at least at an intersection of both wirings.
This composite insulating pad is characterized by including at least a lower insulating film, an intermediate semiconductor thin film, and an upper insulating film.

Preferably, each of the lower insulating film and the upper insulating film has a single layer structure or a multilayer structure. Further, preferably, the lower insulating film is continuously formed over each intersection, while the intermediate semiconductor thin film and the upper insulating film are separately patterned at each intersection. On the other hand, the thin film transistor includes a gate electrode included in a part of the lower wiring, a gate insulating film in the same layer as the lower insulating film, an active layer formed of the intermediate semiconductor thin film, and a layer in the same layer as the upper insulating film. It is a bottom gate type having a channel protective film. More preferably, the composite insulating pad has an additional insulating film overlaid on the upper insulating film. In this case, the thin film transistor is covered with a passivation film in the same layer as the additional insulating film.

The present invention also includes an active matrix type display device. That is, the display device according to the present invention basically has a panel structure including a pair of insulating substrates bonded to each other with a predetermined gap and an electro-optical material held in the gap. One of the insulating substrates has a pixel electrode, a thin film transistor that drives the pixel electrode for switching, a thin film transistor that forms a peripheral circuit that drives the pixel electrode, and a wiring portion that connects the thin film transistor. The other insulating substrate has a counter electrode. The wiring portion has a lower layer wiring and an upper layer wiring, which are patterned on the one insulating substrate, and a composite insulating pad interposed at least at the intersection of both wirings. Characteristically, the composite insulating pad includes at least a lower insulating film, an intermediate semiconductor thin film, and an upper insulating film.

In the thin film semiconductor device according to the present invention, a lower insulating film (gate insulating film) and an intermediate semiconductor thin film are sequentially formed on a lower layer wiring (gate wiring). When this intermediate semiconductor thin film is patterned and processed into an active layer of a thin film transistor, at the same time, the intermediate semiconductor thin film is patterned in an island shape with a pattern wider than the lower layer wiring to provide an insulating pad at the intersection of the wiring structure. Further, when the channel protection film of the thin film transistor is provided, the pad of the upper insulating film is left at the intersection at the same time. Further, after forming a passivation film (additional insulating film or interlayer insulating film), a contact hole is formed and an upper wiring (signal wiring) is provided. Since the intermediate semiconductor thin film included in the composite insulating pad interposed between the lower gate wiring and the upper signal wiring has excellent chemical resistance, a wet etching treatment using a hydrofluoric acid-based chemical or the like in the subsequent process. Even if it is performed, it does not attack the underlying gate insulating film. Furthermore, since the composite insulating pad includes the upper insulating film and the additional insulating film in addition to the intermediate semiconductor thin film, the electric interlayer withstand voltage between the gate wiring and the signal wiring becomes perfect.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic sectional view showing an embodiment of a thin film semiconductor device according to the present invention. The thin film semiconductor device according to this example is used as a drive substrate of an active matrix type display device. However, it goes without saying that the present invention is not limited to this. As shown in the figure, in this thin film semiconductor device, at least a thin film transistor 2 and a wiring portion 3 are integrally formed on an insulating substrate 1 made of glass or the like. (A) represents the intersection of the wiring portions 3. The wiring portion 3 includes a lower layer wiring (for example, a gate wiring) 4 and an upper layer wiring (for example, a signal wiring) 5 formed by patterning on the insulating substrate 1, and a composite insulating pad 6 interposed at least at an intersection of both wirings 4 and 5.
And The composite insulating pad 6 includes at least a lower insulating film (gate insulating film or the like) 7, an intermediate semiconductor thin film 8 and an upper insulating film 9. In this example, an additional insulating film (passivation film or the like) 10 is further formed on the upper insulating film 9. Generally, the lower insulating film 7, the upper insulating film 9, and the additional insulating film 10 have a single layer structure or a multilayer structure. The lower insulating film 7 is continuously formed over each intersection. The intermediate semiconductor thin film 8 is separated and formed in an island pattern at each intersection. Similarly, the upper insulating film 9 is also patterned in an island shape so as to be separated at each intersection.

As shown in FIG. 1B, the thin film transistor 2 has a bottom gate structure, and the gate electrode 11 and the lower insulating film 7 included in a part of the lower wiring (gate wiring) 4.
A gate insulating film 12 in the same layer, an active layer 13 made of the intermediate semiconductor thin film 8, and a channel protective film 14 in the same layer as the upper insulating film 9. The thin film transistor 2 having such a configuration is covered with the passivation film 15 in the same layer as the additional insulating film 10 stacked on the upper insulating film 9. A contact hole is opened in this passivation film 15,
The upper layer wiring (signal wiring) 5 is electrically connected to the source region S of the thin film transistor 2 through this contact hole. Further, the pixel electrode 16 made of a transparent conductive film such as ITO
Also through the contact hole to the thin film transistor 2
Is electrically connected to the drain region D.

Next, with reference to FIG. 1, a method of manufacturing the thin film semiconductor device according to the present invention will be described in detail. First, Mo is sputtered on the insulating substrate 1 made of glass or the like.
An alloy of / Ta is deposited to a thickness of 300 nm. This alloy film is patterned by isotropic chemical dry etching to process the gate wiring 4 and the gate electrode 11. As shown in the figure, the gate wiring 4 is provided with a taper angle of about 30 °, and the disconnection failure or the like of the wiring portion is suppressed by making the slope of the step portion gentle. Next, plasma CVD
SiN _x and SiO _x are continuously formed by the
(Gate insulating film 12) was formed. In this example, SiN _x has a thickness of 250 nm and SiO _x has a thickness of 100 nm.
Thus, the lower insulating film 7 and the gate insulating film 12 have a multi-layer structure, but the present invention is not limited to this, and a single-layer structure may be adopted. Further, an intermediate semiconductor thin film 8 made of amorphous silicon is continuously formed on the lower insulating film 7 and the gate insulating film 12 by plasma CVD. The thickness is set to 50 nm, for example. After that, the amorphous silicon is once melted by irradiating an excimer laser beam or the like, and then converted into polycrystalline silicon in the cooling process. Then plasma CVD
SiO _x is formed into a film having a thickness of 200 nm as the upper insulating film 9 by the method. The upper insulating film 9 is patterned so as to be left only at the intersections of the wiring portions 3 and the channel portions of the thin film transistors 2. The SiO _x left in the channel portion becomes the channel protective film 14 and has a desired impurity ion blocking property. Subsequently, the intermediate semiconductor thin film 8 is selectively patterned and left at the intersection of the wiring portions 3 to form the composite insulating pad 6. At this time, the intermediate semiconductor thin film 8 is simultaneously patterned so as to include the element region of the thin film transistor 2, and the active layer 13 is provided. Next, the source region S and the drain region D of the thin film transistor 2 are provided in the active layer 13 by plasma doping impurity ions such as phosphorus by self-alignment using the channel protective film 14 as a mask. Irradiation with excimer laser light activated the doped impurities by annealing. Further, SiO ₂ is added to 30 by atmospheric pressure CVD.
The additional insulating film 10 and the passivation film 15 were formed with a thickness of 0 nm. After that, a contact hole was opened in the passivation film 15 by etching, and aluminum was formed thereon with a thickness of 600 nm. This aluminum was patterned to form upper layer wiring (signal wiring) 5. As shown in the drawing, a part of the signal wiring 5 is provided in the thin film transistor 2 through a contact hole opened in the passivation film 15.
Is electrically connected to the source region S of. Finally, ITO was formed into a film with a thickness of 120 nm, patterned into a predetermined shape, and processed into the pixel electrode 16. The pixel electrode 16 is electrically connected to the drain region D of the thin film transistor 2 via a contact hole opened in the passivation film 15.
As described above, the thin film semiconductor device for display is completed.

FIG. 2 shows a plane pattern at the intersection of the wiring structure shown in FIG. As shown in the figure, a composite insulating pad 6 is interposed between the lower gate wiring 4 and the upper signal wiring 5. The pad 6 includes an island-shaped intermediate semiconductor thin film 8 and an upper insulating film 9 which are patterned wider than the gate wiring 4. The intermediate semiconductor thin film 8 arranged at the intersection has excellent chemical resistance. For example, even when a wet etching process using a hydrofluoric acid-based chemical is performed in a later step, the underlying gate insulating film is treated with a hydrofluoric acid-based chemical. Can effectively protect from chemicals. Furthermore, the upper insulating film 9 and the additional insulating film, which are overlaid on the intermediate semiconductor thin film 8, complete the electrical interlayer breakdown voltage of the composite insulating pad 6.

FIG. 3 is a schematic perspective view showing an example of an active matrix type display device assembled by using the display thin film semiconductor device shown in FIG. As shown in the figure, the display device has a panel structure including a pair of transparent substrates 101 and 102 and a liquid crystal 103 held between them. A screen portion 104 and a peripheral portion are integrally formed on the lower transparent substrate 101. Peripheral part is vertical drive circuit 105
And a horizontal drive circuit 106. Also, the transparent substrate 1
A terminal portion 107 for external connection is formed on the upper end of the peripheral portion of 01. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108.
The screen portion 104 includes gate wirings 109 and signal wirings 110 that intersect in a matrix. Pixel electrode 1 at each intersection
11 and a thin film transistor 1 for switching and driving the same
12 are formed. The gate wiring 109 is connected to the vertical drive circuit 105, and the signal wiring 110 is connected to the horizontal drive circuit 10.
6 is connected. The drain region of the thin film transistor 112 is connected to the corresponding pixel electrode 111, the source region is connected to the corresponding signal line 110, and the gate electrode is continuous to the corresponding gate line 109. As described above, the pixel electrode 111, the thin film transistor 112 for switching and driving the pixel electrode 111, the thin film transistor for forming the peripheral circuit for driving the pixel electrode 111, and the wiring portion for connecting the thin film transistor are formed on the one insulating substrate 101. A counter electrode is formed on the other insulating substrate 102. An electro-optical material such as liquid crystal 103 is held in the gap between the pair of insulating substrates 101 and 102. The wiring portion includes a gate wiring 109 and a signal wiring 110 which are patterned on the insulating substrate 101.
And a composite insulating pad interposed at least at the intersection of both wirings. This composite insulating pad is characterized by including at least a lower insulating film, an intermediate semiconductor thin film, and an upper insulating film.

In order to evaluate the short-circuit defect prevention ability at the intersection of the wiring structure, the invention sample shown in FIG. 2 and FIG.
The sample of the conventional product shown in was prepared. The invention sample has a composite insulating pad composed of an intermediate semiconductor thin film, an upper insulating film, and an additional insulating film at the intersection of wirings. On the other hand, in the conventional sample, only the gate insulating film is interposed between the lower wiring and the upper wiring. Each sample was immersed in a dilute hydrofluoric acid solution before the upper wiring (signal wiring) was formed by patterning. Samples having dilute hydrofluoric acid immersion treatment times of 1 minute, 5 minutes, and 15 minutes were prepared, assembled into the active matrix type liquid crystal display panel shown in FIG. 3, and actually driven to compare the image quality. No difference was observed between the invention sample and the conventional sample at the treatment time of 1 minute. At the treatment time of 5 minutes, one cross-shaped line defect was observed in the conventional sample. When the processing time was 15 minutes, cross-shaped line defects were generated at 4 places. On the other hand, in the invention sample, no line defect was observed regardless of the immersion time. Further, with respect to the sample having the immersion time of 1 minute, a probe was directly applied to the lower wiring and the upper wiring to measure the leak current. In the conventional sample, breakdown occurred at the applied voltage of 20 V, but in the invention sample, the current increased only by one digit at the applied voltage of 80 V. Thus, it can be seen that the present invention has extremely excellent effects in terms of both chemical resistance and dielectric strength.

[0015]

According to the present invention, the composite insulating pad is provided on the lower wiring with the gate insulating film, the intermediate semiconductor thin film, the upper insulating film and the additional insulating film interposed. By providing an upper layer wiring on this pad, the chemical resistance and dielectric strength at the intersection of the wiring can be remarkably enhanced, and a thin film semiconductor device for display with high reliability in which the occurrence of defects is suppressed is provided. provide.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film semiconductor device according to the present invention.

FIG. 2 is a schematic plan view showing an intersection of wirings formed in the thin film semiconductor device shown in FIG.

FIG. 3 is a perspective view showing an example of an active matrix display device assembled using the thin film semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view showing an example of a conventional thin film semiconductor device.

5 is a plan view showing an intersection of wirings formed in the conventional thin film semiconductor device shown in FIG.

[Explanation of symbols]

 1 Insulating Substrate 2 Thin Film Transistor 3 Wiring Part 4 Lower Layer Wiring (Gate Wiring) 5 Upper Layer Wiring (Signal Wiring) 6 Composite Insulating Pad 7 Lower Insulating Film 8 Intermediate Semiconductor Thin Film 9 Upper Insulating Film 10 Additional Insulating Film 11 Gate Electrode 12 Gate Insulating Film 13 active layer 14 channel protective film 15 passivation film 16 pixel electrode

Claims (6)

[Claims] 1. A thin film semiconductor device in which at least a thin film transistor and a wiring portion are integrated and formed on an insulating substrate, wherein the wiring portion includes a lower layer wiring and an upper layer wiring patterned on the insulating substrate, and at least both wirings. A composite insulating pad interposed at an intersection, wherein the composite insulating pad includes at least a lower insulating film, an intermediate semiconductor thin film, and an upper insulating film. 2. The thin film semiconductor device according to claim 1, wherein the lower insulating film and the upper insulating film each have a single-layer structure or a multi-layer structure. 3. The lower insulating film is continuously formed over each intersection, while the intermediate semiconductor thin film and the upper insulating film are separately formed by patterning at each intersection. The thin film semiconductor device according to claim 1, which is characterized in that. 4. The thin film transistor includes a gate electrode included in a part of the lower wiring, a gate insulating film in the same layer as the lower insulating film, an active layer made of the intermediate semiconductor thin film, and the upper insulating film. 2. The thin film semiconductor device according to claim 1, wherein the thin film semiconductor device is a bottom gate type device having a channel protective film of the same layer. 5. The composite insulating pad has an additional insulating film overlaid on the upper insulating film, and the thin film transistor is covered with a passivation film in the same layer as the additional insulating film. 4. The thin film semiconductor device according to 4. 6. A panel structure comprising a pair of insulating substrates bonded to each other with a predetermined gap and an electro-optical material held in the gap, one insulating substrate being a pixel electrode, and switching the pixel electrode. A thin film transistor that drives, a thin film transistor that forms a peripheral circuit that drives the thin film transistor, and a wiring portion that connects the thin film transistors, and the other insulating substrate is a display device that has a counter electrode, and the wiring portion is the one insulating film. It has a lower layer wiring and an upper layer wiring formed by patterning on the substrate, and a composite insulating pad interposed at least at the intersection of both wirings, wherein the composite insulating pad includes at least a lower insulating film, an intermediate semiconductor thin film and an upper insulating film. Display device characterized by including.