KR0161325B1 - Thin film transistor array and liquid crystal display device - Google Patents

Abstract

An object of the present invention is to improve the voltage application efficiency to the liquid crystal by the pixel electrode and to improve the yield in the manufacturing process, without damaging good contacts between the drain electrode and the pixel electrode.

The thin film transistor array of the present invention includes a gate electrode, a gate insulating film covering the gate electrode, a semiconductor film and an ohmic contact film formed over the gate electrode, a source electrode and a drain electrode connected to the ohmic contact film, A pixel electrode connected to a drain electrode, a thin film transistor array having a protective film formed thereon, wherein the source electrode and the drain electrode are composed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked on top of the lower layer. The pixel electrode formed on the protective film and the drain electrode upper layer are connected through a contact hole formed of a protective film covering the source electrode and the drain electrode.

Description

Thin Film Transistor Array and Liquid Crystal Display

1 is a side cross-sectional view showing an embodiment of the present invention.

2 is a cross-sectional view showing a state in which a first metal film is formed on the surface of a substrate in this embodiment.

3 is a cross-sectional view showing a state in which a gate electrode and a gate wiring are formed on a substrate by a first photolithography process in this embodiment.

4 is a cross-sectional view showing a state in which a first insulating film, a semiconductor film, and an ohmic contact film are formed on a substrate surface in this embodiment.

5 is a cross-sectional view showing a state in which a semiconductor portion is formed by a second photolithography step in the present embodiment.

6 is a cross-sectional view showing a state in which a second metal film is formed on the substrate surface in this embodiment.

7 is a cross-sectional view showing a state in which a source electrode, a drain electrode, a source wiring, and a channel portion are formed by a third photolithography step in this embodiment.

8 is a cross-sectional view showing a state in which a passivation film is formed on the substrate surface in this embodiment.

9 is a cross-sectional view showing a state where a contact hole is formed in a passivation film by a fourth photolithography process in this embodiment.

10 is a cross-sectional view showing a state in which a transparent conductive film is formed on a passivation film in this embodiment.

11 is a schematic configuration diagram showing a contact chain.

12 is a side cross-sectional view showing one unit of a contact chain.

Fig. 13 is a side sectional view showing one unit of a conventional example of a contact chain.

Fig. 14A is a side sectional view showing the construction of an embodiment of a liquid crystal display device of the present invention.

Figure 14 (b) is an equivalent circuit diagram.

15 is a graph showing a relationship between an applied voltage and an effective applied voltage.

FIG. 16 shows a driving circuit of a general active matrix liquid crystal display device.

17 is a plan view showing one structural example of a thin film transistor array.

18 is a sectional view of one structural example of a conventional thin film transistor array.

19 is a sectional view of one structural example of a conventional thin film transistor array.

20 is a cross-sectional view of one structural example of a conventional thin film transistor array.

Fig. 21A is a side sectional view showing the structure of a liquid crystal display element.

Figure 21 (b) is an equivalent circuit diagram.

Fig. 22A is a side sectional view showing the structure of a liquid crystal display element.

Figure 22 (b) is an equivalent circuit diagram.

FIG. 23 shows a partial outline of the structure of the liquid crystal display element, (a) shows a design thing, (b) shows a case where a manufacturing defect has occurred, and in each drawing, (I) shows a plan view and (II ) Shows the AB cross-sectional view of FIG.

* Explanation of symbols for main parts of the drawings

3: thin film transistor array 5: liquid crystal display

10: thin film transistor array 12: substrate

14 gate electrode 16 pixel electrode

18 gate insulating film 20 semiconductor film

22: ohmic contact film 24: contact hole

26: lower layer 28: upper layer

30 source electrode 31 drain electrode

34: protective film 36: thin film transistor array

38 thin film transistor array 40 lower layer

42: upper layer 44: source electrode

45 drain electrode 46 contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array in which a plurality of thin film transistors are arranged in a matrix on a substrate, and to a liquid crystal display device using the same, particularly to increase the voltage application efficiency thereof.

FIG. 16 shows an example of an equivalent circuit of an active matrix liquid crystal display device using a thin film transistor array as a switch element.

17. The method of claim 16 also, the plurality of gate wirings _{(G 1, G 2, ...} , G n) and a plurality of source lines _{(S 1, S 2, ...} , S m) are wired in a matrix phase, each of the gate wiring ( G) is connected to the scanning circuit 1, and each signal wiring S is connected to the signal supply circuit 2, respectively, and a thin film transistor (switch element) 3 is provided at the intersection of each line. The capacitor portion 4 and the liquid crystal display element 5, which are capacitors, are connected to the drain electrode of the transistor 3 to form a circuit.

17 and 18 show a thin film transistor array having a portion such as a gate wiring G, a source wiring S, and the like on a substrate in the conventional active matrix liquid crystal display device shown in FIG. 16 as an equivalent circuit. A structural example is shown.

In the thin film transistor array shown in Figs. 17 and 18, the gate wiring G and the source wiring S are wired in a matrix on a transparent substrate 12 such as glass. In addition, the thin film transistor 3 is provided near the intersection of the gate wiring G and the source wiring S. As shown in FIG.

The thin film transistor array 3 shown in FIG. 17 and FIG. 18 has a general configuration of an edge stopper type, and on the gate wiring G and the gate electrode 14 drawn out from the gate wiring G, A gate insulating film 18 made of SiN _X or the like is provided, and a semiconductor film 20 made of amorphous silicon (a-Si) is provided on the gate insulating film 18, and again on the semiconductor film 20. The drain electrode 31 and the source electrode 30 made of a conductive material are disposed to face each other.

In addition, an ohmic contact film 22 such as amorphous silicon, which is heavily doped with impurities such as phosphorus, is formed on the uppermost layer of the semiconductor film 20, and the drain electrode 31 and the source electrode 30 are formed thereon. The edge stopper 13 is formed in the state clamped by). In addition, a transparent pixel electrode 16 made of a transparent electrode material is formed from the top of the drain electrode 31 to the lateral direction of the drain electrode 31.

In the thin film transistor array 3 of this example, the gate electrode 14 has a double structure consisting of a gate insulating film 17 made of Ta ₂ O ₅ in the upper layer and a gate wiring 15 in the lower layer.

The passivation film 34 is provided on the gate insulating film 18, the transparent pixel electrode 16, the source electrode 30, and the like. On this passivation film 34, an alignment film omitted in the drawing is formed, a liquid crystal is provided on the alignment film, and an active matrix liquid crystal display device is constructed, and the transparent pixel electrode 16 applies an electric field to the molecules of the liquid crystal by applying an electric field to the liquid crystal. The molecules can be controlled in orientation.

Moreover, the thin film transistor array 10 as shown in FIG. 19 is also known. The thin film transistor array 10 is formed on a substrate 12 made of glass or the like with a gate electrode 14 made of a conductive metal such as Cr or Al spaced apart from the ITO pixel electrode 16. And on these, the gate insulating film 18 is laminated | stacked. In the gate insulating film 18, a contact hole 24 is formed on an end portion of the ITO pixel electrode 16. As shown in FIG.

In addition, on the gate insulating film 18, a semiconductor film 20 made of a-Si is formed on the gate electrode 14, and a-Si is formed on the upper part of the semiconductor film 20 except for the center portion. An ohmic contact film 22 made of (n ⁺ ) is formed. On the ohmic contact film 22 and its peripheral portion, and on the contact hole 24 formed in the gate insulating film 18 and on the gate insulating film 18 of its peripheral portion, the lower layer 26 made of Cr, Al, or the like A source electrode 30 and a drain electrode 31 made of an upper layer 28 are formed. At this time, a gate electrode 32 made of Cr or the like is interposed between the lower layer 26 and the ITO pixel electrode 16 at the bottom of the contact hole 24.

In addition, these top, there are laminated passivation protective film 34 made of SiN _X.

Further, a thin film transistor array 36 as shown in FIG. 20 is also known. In the thin film transistor array 36, a gate electrode 14 made of metal such as Cr is formed on the glass substrate 12, and the gate insulating film 18 is formed on the substrate 12 so as to cover the gate electrode 14. ) Are stacked. On the gate insulating film 18, a semiconductor film 20 made of a-Si is formed on the gate electrode 14, and the ITO pixel electrode 16 is spaced apart from the semiconductor film 20. ) Is formed. In addition, an ohmic contact film 22 made of a-Si (n ⁺ ) is formed on the upper portion of the semiconductor film 20 except for the center portion. The source electrode 30 and the drain electrode formed of a lower layer 26 of Cr and an upper layer 28 of Al on the ohmic contact film 22 and on the periphery thereof and above the end of the ITO pixel electrode 16 ( 31) is formed. At this time, the source electrode 30 and the drain electrode 31 are formed between the semiconductor film 20 and the ITO pixel electrode 16 so as to contact the gate insulating film 18. In addition, these top, there are laminated passivation protective film 34 made of SiN _X.

As for the thickness of each of these layers, the thing of the grade shown in Table 1 is suitable for actual use.

The thin film transistor array 3 is manufactured as follows. First, a transparent substrate 12 such as glass is prepared, which is initially cleaned by a brush cleaning device and an ultraviolet irradiation device, and then a surface made of TaO or the like using a film forming method such as reactive sputtering on the transparent substrate after the cleaning. A stabilization film is formed.

On the substrate 12 on which the surface stabilization film was formed, a gate wiring metal film made of a conductive material such as Al was coated on the substrate using a film forming method such as a direct current spatter, and the metal film was subjected to a method such as wet etching. The gate wiring 15 is formed by etching in the first photolithography process.

Next, a gate electrode forming metal film made of Ta or the like is pivoted on the gate wiring 15 by a film forming method such as direct current sputtering, and subsequently etched by a second photolithography process using a method such as dry etching. The electrode 14 is formed.

Next, the gate electrode 14 is subjected to anodization and the surface portion thereof is subjected to TaO to improve the insulating property of the gate electrode 14.

Subsequently, a gate insulating film 18 made of SiN, a semiconductor film 20 made of a-Si (amorphous silicon) or the like, and an edge stopper insulating film made of SiN are formed thereon by a film forming method such as plasma CVD.

Next, an edge stopper 13 is formed on the gate electrode by etching in a third photolithography process using a method such as wet etching.

Next, the surface of the substrate after the third photolithography process is subjected to a-Si (n) using a method such as plasma CVD. An ohmic contact film is formed.

Next, the semiconductor film or the ohmic contact film is patterned by the fourth photolithography step to form a semiconductor part separated from other parts on the gate electrode 14.

Next, a metal film such as Ti is formed on the surface of the substrate after the fourth photolithography process by using a film forming method such as direct current sputtering.

Next, the metal film is patterned by a fifth photolithography process using a method such as dry etching to form a source electrode 30 and a drain electrode 31.

Next, a transparent conductive film such as indium tin oxide (ITO) or the like is formed on the surface of the substrate after the fifth photolithography process by a film formation method such as reactive sputtering.

Next, the transparent conductive film is processed in a sixth photolithography process using a method such as wet etching to form a transparent pixel electrode 16.

Next, a protective film such as SiN is formed on the surface of the substrate after the sixth photolithography step is performed by plasma CVD or the like.

Next, the protective film is patterned by wet etching or the like to form a seventh photolithography process for forming a source terminal contact hole for connecting to the source electrode 30 and a drain terminal contact hole for connecting to the drain electrode 31. The thin film transistor array is then completed.

In the above-mentioned thin film transistor arrays 3, 10 and 36, any one of the small or small electrode 30 and the drain electrode 31 also forms an ohmic contact film 22 and a good ohmic contact layer. Further, in order to form good contact with the ITO pixel electrode 16, Cr is formed under the source electrode 30 and the drain electrode 31, and the wiring resistance of the source electrode 30 and the drain electrode 31 is applied. In order to reduce, Al is laminated | stacked on the Cr top.

However, in the case of the thin film transistor array 10, the gate insulating film 18 and the passivation protective film 34 are stacked on the ITO pixel electrode 16, and the ITO also in the thin film transistor arrays 3 and 36. Since the passivation protective film 34 is laminated on the pixel electrode 16, the voltage application efficiency from the ITO pixel electrode 16 to the liquid crystal is lowered.

That is, in the liquid crystal display device in which the thin film transistor array 10 is assembled, the ITO insulating film 18, the passivation protective film 34, and the alignment film 52 are formed on the glass substrate 12 as shown in FIG. 21 (a). The liquid crystal 50 and the alignment film 52 are interposed. Therefore, the equivalent circuit of this structure is shown in FIG. 21 (b).

Similarly, in the thin film transistor arrays 3 and 36, a passivation passivation film (I) is formed between the ITO pixel electrode 16 on the gate insulating film 18 and the pixel electrode 16 'facing the liquid crystal 50. 34, the alignment film 52, the liquid crystal 50, and the alignment film 52 are interposed. Therefore, the equivalent circuit of this structure is shown in FIG. 22 (b).

Therefore, in any of the thin film transistor arrays 3, 10 and 36, the relationship of the following formula is established between the voltage Vd applied from the drain electrode of the thin film transistor array and the effective voltage V related to the liquid crystal. do.

In addition, C _SIN in FIG. 22 (b) is the sum of C _P-SIN and C _G-SIN .

In this way, when the effective applied voltage is low, the contrast of the liquid crystal display cannot be effectively increased.

It is also conceivable to form the ITO pixel electrode 16 over the Al of the drain electrode 31, but if only this configuration is used, a layer having a high resistance value is formed between Al and the ITO pixel electrode 16. It will be impossible to obtain good electrical contact.

Therefore, in the thin film transistor array, a plurality of thin film transistor arrays are manufactured in a matrix as shown in Fig. 23 (a) by a thin film forming method using CVD or etching techniques.

However, in this manufacturing process, very high manufacturing precision is required. For example, if a defect occurs in the formation of the pixel electrodes 16, 16 ', ..., the source (gate) as shown in FIG. A significant coupling occurs, such as shorting of lines S⑤ and ⑥, which greatly hinders yield improvement.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and to improve the voltage application efficiency to the liquid crystal by the pixel electrode and to improve the yield in the manufacturing process without damaging the good contact between the drain electrode and the pixel electrode. It is an object of the present invention to provide a liquid crystal display device capable of increasing the voltage application efficiency from a thin film transistor array or a pixel electrode to a liquid crystal, thereby increasing the display contrast, and further improving the yield in the manufacturing process. .

The thin film transistor array of the present invention includes at least a gate electrode, a gate insulating film covering the gate electrode, a semiconductor film and an ohmic contact film formed on the gate electrode, and a source electrode and a drain electrode connected to the ohmic contact film; And a pixel electrode connected to the drain electrode and a protective film, wherein the source electrode and the drain electrode are formed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked on top of the lower layer. And a pixel electrode formed on the protective film covering the source electrode and the drain electrode and an upper layer of the drain electrode.

At this time, the metal forming the silicide of the lower layer is particularly preferably Cr.

In the liquid crystal display device of the present invention, a liquid crystal is sealed between a pair of substrates disposed to face each other, a gate insulating film covering at least a gate electrode and the gate electrode on one substrate opposing surface, and a semiconductor film formed over the gate electrode. An ohmic contact film, a source electrode and a drain electrode connected to the ohmic contact film, a pixel electrode and a protection film connected to the drain electrode, and a lower layer made of a metal forming the silicide of the source electrode and the drain electrode; And an upper layer made of copper stacked on top of the lower layer, wherein the pixel electrode formed on the protective film and the upper layer of the drain electrode are connected through a contact hole formed by a protective film covering the source electrode and the drain electrode. It is to be done.

It is particularly preferable that the metal forming the silicide of the lower layer is Cr.

In the thin film transistor array of the present invention, since the pixel electrode connected to the drain electrode is formed on the protective film through the contact hole formed in the protective film, no gate insulating film or protective film is interposed between the pixel electrode and the liquid crystal. Therefore, the voltage application efficiency from the pixel electrode to the liquid crystal can be increased.

At this time, since the drain electrode has a lower layer made of a metal forming silicide and an upper layer made of copper laminated thereon, the resistance value of the drain electrode is low and good electrical contact can be maintained.

In the thin film transistor array of the present invention, a gate insulating film or a protective film is interposed between the pixel electrode and the gate line or the source / drain line. An unnecessary occurrence such as a short circuit between the pixel electrode and the gate line or the source / drain line occurs. Can be suppressed.

In addition, in the liquid crystal display device of the present invention, since the voltage application efficiency from the pixel electrode to the liquid crystal is high, it is possible to apply a high voltage to the liquid crystal, the amount of change in transmittance is large, and the display contrast is high.

EXAMPLE

An embodiment of a thin film transistor array of the present invention and a liquid crystal display device using the same will be described with reference to FIG.

In the thin film transistor array 38 of the present embodiment shown in FIG. 1, each layer required as a transistor for liquid crystal display elements is stacked on the substrate 12, and the gate electrode 14 and the gate electrode 14 are stacked. A gate insulating film 18 covering the gap is formed. A conductive metal material is used for the gate electrode 14, and Cr or Al is suitable. SiN _X or the like is used for the gate insulating film 18.

On the gate insulating film 18, a semiconductor film 20 made of a-Si is formed on the gate electrode 14, and a-Si (n ⁺ is formed on the upper portion of the semiconductor film 20 except for the center portion. An ohmic contact film 22 made of () is formed.

The source electrode 44 and the drain electrode 45 are stacked on the ohmic contact film 22 and the peripheral portion of the semiconductor film 20 on the gate insulating film 18. The source electrode 44 and the drain electrode 45 each consist of a lower layer 40 and an upper layer 42 stacked thereon. The lower layer 40 is made of a metal forming silicide, and Cr, Ti, and the like may be applied, but Cr is suitable. Cu is used for the upper layer 42.

In addition, a passivation protective film 34 made of SiN _X is laminated on each of these layers. In the passivation protective film 34, a contact hole 46 is formed at a position in contact with the end portion of the drain electrode 45.

In the thin film transistor array 38 of this embodiment, an ITO pixel electrode 16 is stacked on the passivation protective film 34, and the ITO pixel electrode 16 is connected to the drain electrode 45 through the contact hole 46. ) Is connected to the upper layer 42.

As for the thickness of each of these layers, the thing of the grade shown in Table 2 is suitable for actual use.

This thin film transistor array 38 can be manufactured as follows.

First, in step 1, a first metal film 14 'formed from a conductive metal thin film made of a conductive material such as Cr, Ta, Mo, Al, or the like is formed on a transparent substrate 12 such as glass shown in FIG. do. Here, the thickness of the first metal film 14 'to be formed can be, for example, about 1000 kPa.

Next, in the first photolithography step 2, the substrate 12 with the first metal film 14 'is processed as follows. First, the substrate 12 is cleaned to apply a resist on the first metal film 14 ', and the photomask is transferred to the photoresist by exposing and developing all over the upper surface through the photomask.

Next, in the case where the first metal film 14 'is a film made of Cr, the wet etching treatment is performed using a compounding composition etching solution of (NH) [Ce (NO)] + HNO + HO, and then the resist is It peels and forms the gate electrode 14 and the gate wiring 19 shown in FIG. 3 on the board | substrate 12. As shown in FIG. Although only a portion of the gate electrode and the gate wiring are shown in the drawing, in practice, a plurality of gate electrodes 14 and the gate wiring 19 are formed on the substrate 12.

After the gate electrode 14 and the gate wiring 19 have been formed, the substrate 12 on which they are formed is cleaned in step 3, and the first insulating film 18 made of SiN is formed on the surface thereof as shown in FIG. The semiconductor film 20 made of a-Si and a-Si (n The ohmic contact film 22 made of () is laminated. The first insulating film 18 formed here may be, for example, about 3000 mW, the semiconductor film 20 about 1000 mW, and the ohmic contact film 22 about 200 mW.

Next, in the second photolithography step 4, similarly to the first photolithography step 2, the process of resist coating, exposure, development, etching, and resist peeling is performed to form the semiconductor film 20 and the ohmic contact film 22. By patterning, the semiconductor portion 21 is formed on the gate electrode 14 as shown in FIG. The etching liquid used at this process can use the compounding composition which becomes HF + HNO, for example.

After the second photolithography step 4 has been performed, the substrate 12 is cleaned in step 5, and the metal film 40 'made of Cr and the conductive material on the upper surface thereof and the Cu film 42' are sequentially made sixth. It is formed as shown in the figure.

When the Cu film 42 'is formed, in the third photolithography step 6, the metal film 40', the Cu film 42 'and the ohmic contact film 22 are patterned by a method such as wet etching. As shown in FIG. 7, the source electrode 44, the source wiring 47, the drain electrode 45, and the channel portion 49 are formed.

Moreover, the compounding composition which consists of HF + HNO can be used as an etching liquid used when performing the said wet etching.

Subsequently, in step 7, the substrate 12 having been treated is cleaned, and a passivation film 34 is formed on the surface thereof as shown in FIG. 8 by a method such as plasma CVD. The passivation film 34 formed here can be formed in thickness of about 4000 micrometers, for example.

After the passivation film 34 is formed, the passivation film 34 is patterned on the processed substrate 12 by dry etching using SF + O gas or the like in the fourth photolithography step 8. As shown in the figure, a contact hole 46 through the drain electrode 45, a contact hole 54 through the gate wiring 19, and a contact hole 56 through the source wiring 47 are formed.

In step 9, a transparent conductive film 16 'made of ITO is formed on the surface of the substrate 12 on which the contact holes are formed. The thickness of this transparent conductive film 16 'can be about 1500 kPa.

Finally, in the fifth photolithography process, a part of the transparent conductive film 16 'is removed by wet etching to form the transparent pixel electrode 16 and the source wiring connection terminal portion 21 as shown in FIG.

The etching liquid used at this time can use the thing which has a compounding composition of HCl + HNO + HO, for example.

Through the above steps, the thin film transistor array 38 having the structure shown in FIG. 1 can be obtained. According to the manufacturing method of this example, the photolithography step is good in five steps in all the steps, the number of steps is small, the production step can be simplified, the yield can be improved, and the manufacturing cost can be reduced.

This thin film transistor array 38 is used to form a liquid crystal display device shown in FIG. 14 by enclosing liquid crystal between conventional substrates and other substrates facing each other, and the transparent pixel electrode 16 is disposed thereon. Arrangement control of liquid crystal molecules provided in the display can be performed by liquid crystal.

According to the structure of the liquid crystal display device of the present embodiment, the gate insulating film 18 or the passivation protective film 34 is not laminated between the transparent pixel electrode 16 and the liquid crystal molecules, and voltage can be efficiently applied to the liquid crystal molecules. , The voltage application efficiency is improved.

In particular, since the source layer 44 and the drain electrode 45 have a two-layer structure of the upper layer 42 and the lower layer 40, the upper layer 42 is made of Cu, whereby the resistance is small and good electrical contact can be maintained.

In the thin film transistor array 38 of this embodiment, the gate line / pixel electrode or the source / drain line / pixel electrode is formed in a layer separated from the gate insulating film and the passivation protective film 34, respectively. For this reason, the short circuit of a gate line / pixel electrode or a source drain line / pixel electrode does not occur, and a yield improves.

[Test Example]

The pixel electrode and various metal terminals were connected in series, and the resistance thereof was measured. That is, in this test, as shown in FIG. 12, the pixel electrodes 16 are connected on various metal terminals 48 via contact holes formed of an insulating film such as SiN. As shown in the figure, the contact chain is formed by plural and continuous connections, and the resistance thereof is measured. Al, Cr, Ti, Cu were used as each metal provided for the test. For comparison, an equivalent of a conventional thin film transistor array, as shown in FIG. 13, by connecting an Al / Cr terminal 48 'on the pixel electrode 16 was also measured to form a contact chain.

As a result, if Al / Cr is formed on the conventional pixel electrode, the resistance value is 1 × 10. ～ 1 × 10 It was Ω. On the other hand, the measurement result of using Al, Cr, Ti, and Cu for the metal terminal 48 is shown in Table 3.

From this measurement result, when Al is used for the metal terminal, the resistance value is too large to be used, and Cr is a level that can be used but is not preferable. However, it was found that Ti or Cu can be used in comparison with the conventional ones, and Cu is particularly excellent.

This is considered to be attributable to the formation of an insulating film by oxidizing each metal when forming an oxide conductive film such as ITO as the pixel electrode.

In other words, Al, Cr, Ti, and Cu are oxidized to produce AlO, CrO, TiO, and CuO, but Cu is considered to be the most suitable among them because AlCr ≒ TiCuAu is easily oxidized.

[Calculation of effective voltage]

In the liquid crystal display device in which the thin film transistor array 38 of the present embodiment is assembled, as shown in FIG. 14 (a), the alignment film 52 and the liquid crystal ( 50) and the alignment film 52 is only interposed. Therefore, the equivalent circuit of this structure is shown in FIG. 14 (b). Therefore, the relationship of the following formula (ii) is established between the voltage Vd applied from the drain electrode and the effective voltage V related to the liquid crystal.

The area of the current pixel electrode is 10 × 10 ⁻⁸ m ² , and the thickness and dielectric constant of each layer are the values shown in Table 4 below.

In this condition, the capacity (C = ε S / d) of each layer is as follows.

C = 3.0 × 10 (F)

C = 1.85 × 10 (F)… Only protective film 34 (P-SIN)

C = 1.05 × 10 (F)… Passivation layer 34 (P-SIN) and gate insulating layer 18 (G-SIN)

C = 7.8 × 10 (F)… Vf2V

C _LC = 1.6 × 10 ⁻² (F). V _LC f3.5V

From this, the relationship shown in FIG. 15 between the present embodiment and the voltage Vd applied from the respective drain electrodes of the respective thin film transistor arrays 38, 10, and 36 and the effective voltage V _LC related to the liquid crystal. Is established.

For example, when Vg is set to 6 (V) from FIG. 15, the effective applied voltage by the thin film transistor array 38 of this embodiment is 12.5%, compared with the conventional thin film transistor array 10, and the thin film transistor array. It can be seen that the increase is 8% compared to (36).

Therefore, it can be seen that the thin film transistor array 38 of the present embodiment can increase the effective applied voltage, thereby increasing the contrast of the liquid crystal display.

The thin film transistor array of the present invention includes at least a gate electrode on the substrate, a gate insulating film covering the gate electrode, a semiconductor film and an ohmic contact film formed on the gate electrode, a source electrode connected to the ohmic contact film, and A thin film transistor array having a drain electrode, a pixel electrode connected to the drain electrode, and a protective film, wherein the source electrode and the drain electrode are formed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked thereon. And a pixel electrode formed on the protective film and an upper layer on the drain electrode are connected through a contact hole formed of a protective film covering the source electrode and the drain electrode.

In the thin film transistor array having this structure, the pixel electrode connected to the drain electrode is formed on the protective film through the contact hole formed by the protective film. Thus, no gate insulating film or protective film is interposed between the pixel electrode and the liquid crystal. Therefore, the voltage application efficiency from the pixel electrode to the liquid crystal can be increased, and the contrast of the liquid crystal display can be effectively increased when used as a liquid crystal display device.

At this time, since the drain electrode is composed of a lower layer made of a metal forming silicide and an upper layer made of copper stacked thereon, the resistance value of the drain electrode is small, and good electrical contact can be maintained.

In the thin film transistor array of the present invention, since a gate insulating film or a protective film is interposed between the pixel electrode and the gate line or the source / drain line, unnecessary generation such as a short circuit between the pixel electrode and the gate line or the source / drain line occurs. Can be suppressed. Therefore, manufacturing yield can be improved significantly.

Claims (4)

At least a gate electrode on the substrate, a gate insulating film covering the gate electrode, a semiconductor film formed on the gate electrode, an ohmic contact film, a source electrode and a drain electrode connected to the ohmic contact film, and connected to the drain electrode. A thin film transistor array in which a pixel electrode and a protective film are formed, wherein the source electrode and the drain electrode are composed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked on top of the lower layer. And a pixel electrode formed on the passivation layer and an upper layer of the drain electrode connected through a contact hole formed by a passivation layer covering the drain electrode. The thin film transistor array of claim 1, wherein the metal forming the silicide of the lower layer is Cr. A liquid crystal is sealed between a pair of substrates opposed to each other, a gate insulating film covering at least a gate electrode and the gate electrode on an opposite surface of one substrate, a semiconductor film and an ohmic contact film formed over the gate electrode, and the ohmic A source electrode and a drain electrode connected to the contact film, a pixel electrode and a protective film connected to the drain electrode, and a bottom layer made of a metal which forms the silicide, and the source electrode and the drain electrode are stacked on top of the bottom layer. And an upper layer of the drain electrode and the pixel electrode formed on the passivation layer through a contact hole formed of a top layer made of copper, the passivation layer covering the source electrode and the drain electrode. The liquid crystal display device according to claim 3, wherein the metal forming the silicide of the lower layer is Cr.