KR960001851A - Thin Film Transistor Array and Liquid Crystal Display - Google Patents

Thin Film Transistor Array and Liquid Crystal Display Download PDF

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Publication number
KR960001851A
KR960001851A KR1019950017014A KR19950017014A KR960001851A KR 960001851 A KR960001851 A KR 960001851A KR 1019950017014 A KR1019950017014 A KR 1019950017014A KR 19950017014 A KR19950017014 A KR 19950017014A KR 960001851 A KR960001851 A KR 960001851A
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South Korea
Prior art keywords
electrode
drain electrode
film
lower layer
gate
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KR1019950017014A
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Korean (ko)
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KR0161325B1 (en
Inventor
겐지 야마모또
마꼬또 사사끼
지사또 이와사끼
아사꼬 와가
Original Assignee
아베 아끼라
가부시끼가이샤 프론테크
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Publication of KR960001851A publication Critical patent/KR960001851A/en
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Publication of KR0161325B1 publication Critical patent/KR0161325B1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명의 목적은 드레인전극과 화소전극의 양호한 콘택트를 손상하는 일 없이, 그 화소전극에 의한 액정에의 전압인가효율을 높이고, 또, 제조과정에 있어서의 수율을 향상시키는데에 있다.An object of the present invention is to improve the voltage application efficiency to the liquid crystal by the pixel electrode and to improve the yield in the manufacturing process, without damaging good contacts between the drain electrode and the pixel electrode.

본 발명의 박막트랜지스터 어레이는, 기판상에 게이트전극과, 게이트전극을 덮은 게이트절연막과, 게이트전극 위쪽에 형성되는 반도체막 및 오믹콘택트막과, 오믹콘택트막에 접속된 소오스전극 및 드레인전극과, 드레인전극에 접속된 화소전극과, 보호막이 형성되어 있는 박막트랜지스터 어레이에 있어서, 소오스전극 및 드레인전극이 실리사이드를 형성하는 금속으로 이루어진 하부층과, 이 하부층의 상부에 적층된 구리로 이루어진 상부층으로 구성되고, 소오스전극 및 드레인전극을 덮는 보호막으로 형성된 콘택트홀을 통하여 보호막상에 형성된 화소전극과, 드레인전극 상부층이 접속되어 있다.The thin film transistor array of the present invention includes a gate electrode, a gate insulating film covering the gate electrode, a semiconductor film and an ohmic contact film formed over the gate electrode, a source electrode and a drain electrode connected to the ohmic contact film, A pixel electrode connected to a drain electrode, a thin film transistor array having a protective film formed thereon, wherein the source electrode and the drain electrode are composed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked on top of the lower layer. The pixel electrode formed on the protective film and the drain electrode upper layer are connected through a contact hole formed of a protective film covering the source electrode and the drain electrode.

Description

박막트랜지스터 어레이 및 액정표시장치Thin Film Transistor Array and Liquid Crystal Display

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일 실시예를 나타내는 측단면도.1 is a side cross-sectional view showing an embodiment of the present invention.

제2도는 본 실시예에 있어서, 기판표면에 제1금속막을 형성한 상태를 나타내는 단면도.2 is a cross-sectional view showing a state in which a first metal film is formed on the surface of a substrate in this embodiment.

제3도는 본 실시예에 있어서, 기판상에 제1포토리소공정에 의해 게이트전극과 게이트배선을 형성한 상태를 나타낸 단면도.3 is a cross-sectional view showing a state in which a gate electrode and a gate wiring are formed on a substrate by a first photolithography process in this embodiment.

Claims (4)

기판상에 적어도 게이트전극과, 상기 게이트전극을 덮은 게이트절연막과 상기 게이트전극 위쪽에 형성되는 반도체막 및 오믹콘택트막과 상기 오믹콘택트막에 접속된 소오스전극 및 드레인전극과, 상기 드레인전극에 접속된 화소전극과 보호막이 형성되어 이루어진 박막트랜지스터 어레이에 있어서, 상기 소오스전극 및 드레인전극이 실리사이드를 형성하는 금속으로 이루어진 하부층과, 이 하부층의 상부에 적층된 구리로 이루어진 상부층으로 구성되고, 상기 소오스전극 및 드레인전극을 덮은 보호막으로 형성된 콘택트홀을 통하여 보호막상에 형성된 화소전극과, 상기 드레인전극의 상부층이 접속되어 있는 것을 특징으로 하는 박막트랜지스터 어레이.At least a gate electrode on the substrate, a gate insulating film covering the gate electrode, a semiconductor film formed on the gate electrode, an ohmic contact film, a source electrode and a drain electrode connected to the ohmic contact film, and connected to the drain electrode. A thin film transistor array in which a pixel electrode and a protective film are formed, wherein the source electrode and the drain electrode are composed of a lower layer made of a metal forming silicide, and an upper layer made of copper stacked on top of the lower layer. And a pixel electrode formed on the passivation layer and an upper layer of the drain electrode connected through a contact hole formed by a passivation layer covering the drain electrode. 제1항에 있어서, 상기 하부층의 실리사이드를 형성하는 금속이 Cr인 것을 특징으로 하는 박막트랜지스터 어레이.The thin film transistor array of claim 1, wherein the metal forming the silicide of the lower layer is Cr. 대향하여 배치된 한쌍의 기판 사이에 액정이 봉해져 있고, 한쪽 기판의 대향면상에 적어도 게이트전극과 상기 게이트전극을 덮은 게이트절연막과 상기 게이트전극의 위쪽에 형성되는 반도체막 및 오믹콘택트막과, 상기 오믹콘택트막에 접속된 소오스전극 및 드레인전극과, 상기 드레인전극에 접속된 화소전극과 보호막이 형성되어 있고, 상기 소오스전극 및 드레인전극이 형성하는 금속으로 이루어진 하부층과, 이 하부층의 상부에 적층된 구리로 이루어진 상부층으로 구성되고, 상기 소오스전극 및 드레인전극을 덮은 보호막으로 형성된 콘택트홀을 통해 상기 보호막상에 형성된 화소전극과 상기 드레인전극의 상부층이 접속되어 있는 것을 특징으로 하는 액정표시장치.A liquid crystal is sealed between a pair of substrates opposed to each other, a gate insulating film covering at least a gate electrode and the gate electrode on an opposite surface of one substrate, a semiconductor film and an ohmic contact film formed over the gate electrode, and the ohmic A source electrode and a drain electrode connected to the contact film, a pixel electrode and a protective film connected to the drain electrode, and a lower layer made of a metal formed by the source electrode and the drain electrode, and copper stacked on top of the lower layer. And an upper layer of the drain electrode and the pixel electrode formed on the passivation layer through a contact hole formed of a passivation layer covering the source electrode and the drain electrode. 제3항에 있어서, 상기 하부층의 실리사이드를 형성하는 금속이 Cr인 것을 특징으로 하는 액정표시장치.The liquid crystal display device according to claim 3, wherein the metal forming the silicide of the lower layer is Cr. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017014A 1994-06-27 1995-06-23 Thin film transistor array and liquid crystal display device KR0161325B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-145140 1994-06-27
JP14514094A JPH0818058A (en) 1994-06-27 1994-06-27 Film transistor array and liquid crystal display

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Publication Number Publication Date
KR960001851A true KR960001851A (en) 1996-01-26
KR0161325B1 KR0161325B1 (en) 1999-01-15

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KR (1) KR0161325B1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW400556B (en) * 1997-02-26 2000-08-01 Samsung Electronics Co Ltd Composition for a wiring, a wiring using the composition, a manufacturing method thereof, a display using the wiring and a manufacturing method thereof
US6678017B1 (en) * 1998-06-08 2004-01-13 Casio Computer Co., Ltd. Display panel and method of fabricating the same
KR100653467B1 (en) * 1999-12-24 2006-12-04 비오이 하이디스 테크놀로지 주식회사 Method for manufacturing tft-lcd
JP2001343659A (en) * 2000-06-02 2001-12-14 Casio Comput Co Ltd Active matrix type liquid crystal display panel and method of manufacture
KR100646792B1 (en) * 2000-07-27 2006-11-17 삼성전자주식회사 Thin film transistor array panel and method manufacturing the same
WO2003088193A1 (en) * 2002-04-16 2003-10-23 Sharp Kabushiki Kaisha Substrate, liquid crystal display having the substrate, and method for producing substrate
KR100866976B1 (en) 2002-09-03 2008-11-05 엘지디스플레이 주식회사 Liquid Crystal Display and mathod for fabricating of the same
EP1724790A4 (en) 2004-03-09 2008-10-01 Idemitsu Kosan Co Thin-film transistor and thin-film transistor substrate and production methods for them and liquid crystal display unit using these and related device and method, and, sputtering target and transparent conductive film formed by using this and transparent electrode and related device and method
KR101054344B1 (en) 2004-11-17 2011-08-04 삼성전자주식회사 Thin film transistor array panel and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04253342A (en) * 1991-01-29 1992-09-09 Oki Electric Ind Co Ltd Thin film transistor array substrate
JPH04302436A (en) * 1991-03-29 1992-10-26 Casio Comput Co Ltd Thin-film semiconductor element and manufacture thereof
JPH04338730A (en) * 1991-05-16 1992-11-26 Fujitsu Ltd Active matrix type liquid crystal display element
JPH05267344A (en) * 1992-03-23 1993-10-15 Hitachi Ltd Thin-film semiconductor device and manufacture thereof

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JPH0818058A (en) 1996-01-19

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