KR970054520A - Method of manufacturing thin film transistor of liquid crystal display device - Google Patents

Method of manufacturing thin film transistor of liquid crystal display device Download PDF

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KR970054520A
KR970054520A KR1019950067005A KR19950067005A KR970054520A KR 970054520 A KR970054520 A KR 970054520A KR 1019950067005 A KR1019950067005 A KR 1019950067005A KR 19950067005 A KR19950067005 A KR 19950067005A KR 970054520 A KR970054520 A KR 970054520A
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South Korea
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pad
forming
electrode
layer pattern
gate insulating
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KR1019950067005A
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Korean (ko)
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KR100459682B1 (en
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권영찬
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Abstract

본 발명은 액정표시장치의 박막 트랜지스터 제조방법에 관한 것으로, 기판의 소정영역 상에 금속막으로 이루어진 게이트 전극 및 패드를 형성하는 단계; 상기 게이트 전극 및 상기 패드를 덮는 장벽금속막 패턴을 형성하는 단계; 상기 결과물 전면에 게이트 절연막을 형성하는 단계; 상기 게이트 전극 상부의 게이트 절연막 상에 채널층 패턴 및 불순물층 패턴을 차례로 적층시키어 형성하는 단계; 상기 불순물층 패턴의 중앙부분을 노출시키면서 그 양 가장자리 상에 각각 소오소/드레인 전극을 형성함과 동시에 상기 패드와 인접한 게이트 절연막 상에 패드접속용 전극을 형성하는 단계; 상기 노출된 불순물층 패턴의 중앙부분을 식각하여 상기 채널층 채널의 양 가장자리 위에 각각 소오소/드레인 영역을 형성하는 단계; 상기 결과물 전면에 보호층을 형성하는 단계; 상기 보호층 및 상기 게이트 절연막으로 연속적으로 패터닝하여 상기 드레인 전극, 상기 패드접속용 전극, 및 상기 패드를 덮는 장벽금속막 패턴을 노출시키는 콘택홀을 형성하는 단계; 및 상기 드레인 전극 상의 콘택홀을 덮는 화소전극 및 상기 패드접속용 전극과 상기 패드를 연결시켜주는 패드접속용 배선을 동시에 형성하는 단계를 포함하는 것을 특징으로 하는 액정표시장치의 박막 트랜지스터 제조방법을 제공한다. 본 발명에 의하면, 6회의 사진공정으로 박막 트랜지스터를 구현할 수 있어 제조단가를 낮출 수 있다.The present invention relates to a method of manufacturing a thin film transistor of a liquid crystal display device, comprising: forming a gate electrode and a pad made of a metal film on a predetermined region of a substrate; Forming a barrier metal film pattern covering the gate electrode and the pad; Forming a gate insulating film on the entire surface of the resultant product; Sequentially stacking a channel layer pattern and an impurity layer pattern on the gate insulating layer on the gate electrode; Exposing a center portion of the impurity layer pattern and forming a source / drain electrode on both edges thereof and simultaneously forming a pad connection electrode on a gate insulating film adjacent to the pad; Etching a central portion of the exposed impurity layer pattern to form a source / drain region on both edges of the channel layer channel; Forming a protective layer on the entire surface of the resultant product; Successively patterning the protective layer and the gate insulating layer to form a contact hole exposing the drain electrode, the pad connection electrode, and a barrier metal layer pattern covering the pad; And simultaneously forming a pixel electrode covering a contact hole on the drain electrode, and a pad connection wiring connecting the pad connection electrode and the pad simultaneously. do. According to the present invention, the thin film transistor can be implemented in six photographic processes, thereby reducing the manufacturing cost.

Description

액정표시장치의 박막 트랜지스터 제조방법Method of manufacturing thin film transistor of liquid crystal display device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명에 의한 박막 트랜지스터 제조방법을 설명하기 위한 단면도들이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.

Claims (4)

기판의 소정영역 상에 금속막으로 이루어진 게이트 전극 및 패드를 형성하는 단계; 상기 게이트 전극 및 상기 패드를 덮는 장벽금속 패턴을 형성하는 단계; 상기 결과물 전면에 게이트 절연막을 형성하는 단계; 상기 게이트 전극 상부의 게이트 절연막 상에 채널층 패턴 및 불순물층 패턴을 차례로 적층시키어 형성하는 단계; 상기 불순물층 패턴의 중앙부분을 노출시키면서 그 양 가장자리상에 각각 소오소/드레인 전극을 형성함과 동시에 상기 패드와 인접한 게이트 절연막 상에 패드접속용 전극을 형성하는 단계; 상기 노출된 불순물층 패턴의 중앙부분을 식각하여 상기 채널층 패턴의 양 가장자리 위에 각각 소오소/드레인 영역을 형성하는 단계; 상기 결과물 전면에 보호층을 형성하는 단계; 상기 보호층 및 상기 게이트 절연막을 연속적으로 패터닝하여 상기 드레인 전극, 상기 패드접속용 전극, 및 상기 패드를 덮는 장벽금속막 패턴을 노출시키는 콘택홀을 형성하는 단계; 및 상기 드레인 전극 상의 콘택홀을 덮는 화소전극 및 상기 패드접속용 전극과 상기 패드를 연결시켜주는 패드접속용 배선을 동시에 형성하는 단계를 포함하는 것을 특징으로 하는 액정표시장치의 박막 트랜지스터 제조방법.Forming a gate electrode and a pad made of a metal film on a predetermined region of the substrate; Forming a barrier metal pattern covering the gate electrode and the pad; Forming a gate insulating film on the entire surface of the resultant product; Sequentially stacking a channel layer pattern and an impurity layer pattern on the gate insulating layer on the gate electrode; Exposing a center portion of the impurity layer pattern and forming a source / drain electrode on both edges thereof and simultaneously forming a pad connection electrode on a gate insulating film adjacent to the pad; Etching a central portion of the exposed impurity layer pattern to form source and drain regions on both edges of the channel layer pattern, respectively; Forming a protective layer on the entire surface of the resultant product; Successively patterning the protective layer and the gate insulating layer to form a contact hole exposing the drain electrode, the pad connection electrode, and a barrier metal film pattern covering the pad; And simultaneously forming a pixel electrode covering the contact hole on the drain electrode and a pad connection wiring connecting the pad connection electrode and the pad. 제1항에 있어서, 상기 장벽금속막 패턴은 크롬막 또는 탄탈륨막으로 형성하는 것을 특징으로 하는 액정표시장치의 박막 트랜지스터 제조방법.The method of claim 1, wherein the barrier metal layer pattern is formed of a chromium layer or a tantalum layer. 제1항에 있어서, 상기 채널층 패턴은 실리콘막으로 형성하는 것을 특징으로 하는 액정표시장치의 박막 트랜지스터 제조방법.The method of claim 1, wherein the channel layer pattern is formed of a silicon film. 제1항에 있어서, 상기 화소전극은 ITO(indium tin oxide)막으로 형성하는 것을 특징으로 하는 액정표시장치의 박막 트랜지스터 제조방법.The method of claim 1, wherein the pixel electrode is formed of an indium tin oxide (ITO) film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950067005A 1995-12-29 1995-12-29 Thin film transistor of liquid crystal display and manufacturing method KR100459682B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100648846B1 (en) * 1999-05-14 2006-11-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Capacitor, semiconductor device, and manufacturing method thereof
KR100730064B1 (en) * 2000-08-30 2007-06-20 엘지.필립스 엘시디 주식회사 Fabricating Method of Thin Film Transistor Substrate For Detecting X-ray

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62285464A (en) * 1986-06-03 1987-12-11 Matsushita Electric Ind Co Ltd Thin-film transistor array substrate and manufacture thereof
JPH03227068A (en) * 1990-02-01 1991-10-08 Casio Comput Co Ltd Thin film transistor and manufacture thereof
JPH05323373A (en) * 1992-05-22 1993-12-07 Fujitsu Ltd Production of thin film transistor panel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100648846B1 (en) * 1999-05-14 2006-11-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Capacitor, semiconductor device, and manufacturing method thereof
KR100730064B1 (en) * 2000-08-30 2007-06-20 엘지.필립스 엘시디 주식회사 Fabricating Method of Thin Film Transistor Substrate For Detecting X-ray

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