KR970076026A - Manufacturing method of liquid crystal display device - Google Patents

Abstract

According to the manufacturing method for solving the contact resistance problem between the ITO used as the pixel electrode and the drain region of the TFT, a method of manufacturing a liquid crystal display device includes: forming an active layer on an insulating transparent substrate; Forming a photoresist on the active layer, performing patterning, and ion-implanting impurities; Removing the photoresist and forming a gate insulating film; Forming a plurality of conductive layers on the gate insulating layer; Implanting ions into the active layer to form a source region and a drain region; Forming a first interlayer insulating film on the entire surface of the substrate; Removing a portion of the first interlayer insulating film on the source region, the drain region, and the one conductive layer to form a plurality of first contact holes; Depositing a metal on the plurality of first contact holes to form a metal wiring for connecting the drain region to the source region and the plurality of conductive layers; Forming a second interlayer insulating film on the formed metal layer; Forming a second contact hole on the one conductive layer; Forming a pixel electrode connected to the gate electrode connected to the drain region through the contact hole on the second interlayer insulating film; And forming a protective film on the pixel electrode. [7] The method of manufacturing a liquid crystal display device according to claim 7,

Description

Manufacturing method of liquid crystal display device

Since this is a trivial issue, I did not include the contents of the text.

FIG. 4 is a cross-sectional view taken along line BB 'of FIG. 3 (A) to FIG. 5 (H) showing a pixel portion layout of a liquid crystal display device according to a first embodiment of the present invention. Drawing showing process sequence.

Claims (13)

Forming an active layer on the insulating transparent substrate; Depositing a photoresist on the active layer, patterning and implanting impurities; Removing the photoresist and forming a gate insulating film; Forming first, second, and third conductive layers on the gate insulating layer; Implanting ions into the active layer to form a source region and a drain region; Forming a first interlayer insulating film on the entire surface of the substrate; Forming a plurality of first contact holes by partially removing the first interlayer insulating film on the source region and the drain region and on the one gate electrode material; Depositing a metal on the plurality of first contact holes to form a data line in contact with the source region, and forming a metal wiring line connecting the drain region and the gate electrode material; Forming a second interlayer insulating film on the formed metal layer; Forming a second contact hole on the one gate electrode material; Forming a pixel electrode connected to the gate electrode connected to the drain region through the contact hole on the second interlayer insulating film; And forming a passivation layer on the pixel electrode. The method of claim 1, wherein the first conductive layer is a gate electrode. The method of claim 1, wherein the second conductive layer is an upper electrode line of the storage capacitor. The method of claim 1, wherein the third conductive layer is a connection line between the drain region of the TFT and the pixel electrode. Forming an active layer on the insulating transparent substrate; Depositing a photoresist on the active layer, patterning and implanting impurities; Removing the photoresist and forming a gate insulating film on the active layer; Forming a third contact hole exposing a predetermined region of the active layer by selectively etching the gate insulating film; Forming first, second and third conductive layers on the third contact hole and the gate insulating film; Implanting impurity ions into the active layer to form a source region and a drain region; Forming a first interlayer insulating film on the entire surface of the substrate; Removing a portion of the gate insulating film and the first interlayer insulating film to form a first contact hole; Depositing a metal on the first contact hole to form a data line in contact with the source region; and forming a metal interconnection connecting the drain region and the gate electrode material. Forming a second interlayer insulating film on the formed metal layer; Forming a second contact hole on the one gate electrode material; Forming a pixel electrode connected to the gate electrode connected to the drain region through the contact hole on the second interlayer insulating film; And forming a passivation layer on the pixel electrode. 6. The method of claim 5, wherein the first conductive layer is a gate electrode line. 6. The method of claim 5, wherein the first conductive layer is an upper electrode line of the storage capacitor. 6. The method of claim 5, wherein the third gate electrode material is a connection line between the drain region of the TFT and the pixel electrode. Forming an active layer on the insulating transparent substrate; Forming a photoresist on the active layer, performing patterning, and ion-implanting impurities; Removing the photoresist and forming a gate insulating film on the active layer; Forming a plurality of third contact holes exposing a predetermined region of the active layer by selectively etching a part of the gate insulating film; Forming first, second, third, and fourth conductive layers on the third contact hole and the gate insulating film; Implanting impurity ions into the active layer to form a source region and a drain region; Forming a first interlayer insulating film on the entire surface of the substrate; Removing a portion of the gate insulating film and the first interlayer insulating film to form a first contact hole; Depositing a metal on the first contact hole to form a metal wiring; Forming a second interlayer insulating film on the formed metal layer; Forming a second contact hole on the one gate electrode material; Forming a pixel electrode connected to the gate electrode connected to the drain region through the contact hole on the second interlayer insulating film; And forming a passivation layer on the pixel electrode. 10. The method of claim 9, wherein the first gate electrode material is a gate electrode line. 10. The method of claim 9, wherein the second gate electrode material is an upper electrode line of the storage capacitor. 10. The method of claim 9, wherein the third gate electrode material is a connection line between the drain region of the TFT and the pixel electrode. 10. The method of claim 9, wherein the fourth gate electrode material is a connection line between the source region of the TFT and the metal electrode. ※ Note: It is disclosed by the contents of the first application.