KR970054507A - Thin film transistor and method of manufacturing the same - Google Patents

Thin film transistor and method of manufacturing the same Download PDF

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KR970054507A
KR970054507A KR1019950061861A KR19950061861A KR970054507A KR 970054507 A KR970054507 A KR 970054507A KR 1019950061861 A KR1019950061861 A KR 1019950061861A KR 19950061861 A KR19950061861 A KR 19950061861A KR 970054507 A KR970054507 A KR 970054507A
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active layer
insulating film
data line
forming
thin film
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KR1019950061861A
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KR100212270B1 (en
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배병성
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Abstract

본 발명은 다결정 규소 박막 트랜지스터 및 그 제조방법에 관한 것으로서, 더욱 상세하게는, 공정을 단순화한 다결정 규소 박막 트랜지스터 및 그 제조방법에 관한 것이다. 본 발명은, 게이트 절연막, 층간 절연막 및 보호막을 모두 형성하고 나서 세 층을 한꺼번에 식각하여 활성층의 소스/드레인 영역을 형성한다. 따라서, 종래에 비하여 접촉구 형성 공정이 한번 줄어들어 공정이 단순해진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon thin film transistor and a method for manufacturing the same, and more particularly, to a polycrystalline silicon thin film transistor and a method for manufacturing the same. In the present invention, after the gate insulating film, the interlayer insulating film, and the protective film are all formed, the three layers are etched together to form the source / drain regions of the active layer. Therefore, compared with the prior art, the contact hole forming process is reduced once, thereby simplifying the process.

Description

박막 트랜지스터 및 그 제조방법Thin Film Transistor and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 박막 트랜지스터의 구조를 나타낸 단면도이다.2 is a cross-sectional view illustrating a structure of a thin film transistor according to an exemplary embodiment of the present invention.

Claims (17)

투명한 절연 기판, 상기 기판 위에 형성되어 있는 활성층, 상기 활성층 위에 형성되어 있으며, 상기 활성층을 드러내는 한 쌍의 제1접촉구를 가지고 있는 게이트 절연막, 상기 게이트 절연막 위에 형성되어 있는 게이트전극, 상기 게이트 전극을 덮으며 상기 게이트 절연막과 동일한 패턴의 한쌍의 제2접촉구를 가지고 있는 층간 절연막, 상기 층간 절연막 위에 형성되어 있는 데이터선, 상기 데이터선이 형성되어 있는 상기 층간 절연막위에 형성되어 있으며 상기 층간 절연막과 동일한 패턴의 한쌍의 제2접촉구 및 상기 데이터선을 드러내는 제4접촉구를 가지고 있는 보호막, 그리고 동일한 패턴의 상기 제1, 제2 및 제3접촉구를 통하여 상기 활성층과 연결되어 있고 상기 제4접촉구를 통하여 상기 데이터선과도 연결되어 있는 제1투명 전극, 상기 투명 전극이 형성되어있는 상기 접촉구가 아닌 상기 제1, 제2 및 제3접촉구를 통하여 상기 활성층과 연결되어 있는 제2투명 전극을 포함하는 박막 트랜지스터.A transparent insulating substrate, an active layer formed on the substrate, a gate insulating film formed on the active layer and having a pair of first contact holes exposing the active layer, a gate electrode formed on the gate insulating film, and the gate electrode An interlayer insulating film covering the interlayer insulating film having a pair of second contact holes of the same pattern as the gate insulating film, a data line formed on the interlayer insulating film, and formed on the interlayer insulating film on which the data line is formed; A protective film having a pair of second contact holes in a pattern and a fourth contact hole exposing the data line, and connected to the active layer through the first, second and third contact holes of the same pattern and the fourth contact. A first transparent electrode and the transparent electrode, which are also connected to the data line through a sphere It is formed thin film transistors and a second transparent electrode which are coupled to the active layer through the first, second, and third contact hole other than the contact hole. 제1항에서, 상기 데이터선은 알루미늄으로 형성하는 박막 트랜지스터.The thin film transistor of claim 1, wherein the data line is formed of aluminum. 제2항에서, 상기 제1투명 전극은 ITO로 형성하는 박막 트랜지스터.The thin film transistor of claim 2, wherein the first transparent electrode is formed of ITO. 제3항에서, 상기 데이터선과 상기 제1투명 전극의 사이에 형성되어 있는 접촉층을 더 포함하는 박막 트랜지스터.The thin film transistor of claim 3, further comprising a contact layer formed between the data line and the first transparent electrode. 제4항에서, 상기 접촉층은 질화티타늄으로 이루어져 있는 박막 트랜지스터.The thin film transistor of claim 4, wherein the contact layer is formed of titanium nitride. 제1항에서, 상기 게이트 전극 아래의 상기 활성층은 진성 반도체이고, 그 양 옆의 상기 활성층은 외성 반도체인 박막 트랜지스터.The thin film transistor of claim 1, wherein the active layer under the gate electrode is an intrinsic semiconductor, and the active layers adjacent to the active layer are external semiconductors. 제6항에서, 상기 활성층에서 상기 게이트 전극 아래 부분과 가까이 있는 부분은 저농도이고 멀리 있는 부분은 고농도인 박막 트랜지스터.The thin film transistor of claim 6, wherein a portion near the lower portion of the gate electrode in the active layer has a low concentration and a portion far away in the active layer has a high concentration. 제7항에서, 상기 활성층에서 상기 제1 및 제2투명 전극과 접하는 부분은 고농도인 박막 트랜지스터.The thin film transistor of claim 7, wherein a portion of the active layer contacting the first and second transparent electrodes is highly concentrated. 투명한 절연 기판 반도체로 활성층을 형성하는 단계, 절연 물질로 게이트 절연막을 형성하는 단계, 상기 게이트 절연막 위에 게이트를 형성하는 단계, 상기 활성층에 불순물을 주입하여 소스/드레인 영역을 형성하는 단계, 절연 물질로 층간 절연막을 형성하는 단계, 금속으로 데이터선을 형성하는 단계, 절연 물질을 적층한 후 상기 층간 절연막 및 상기 게이트 절연막과 함께 식각하여 접촉구를 형성하여 상기 활성층의 소스/드레인 영역 및 상기 데이터선을 드러내는 단계, 투명한 도전물질로 데이터선 및 한 쪽 소스/드레인 영역과 연결되는 제1투명 전극과 다른 한쪽 소스/드레인 영역과 연결되며 화소 전극을 겸하는 제2투명 전극을 형성하는 단계를 포함하는 박막 트랜지스터의 제조방법.Forming an active layer with a transparent insulating substrate semiconductor; forming a gate insulating film with an insulating material; forming a gate over the gate insulating film; implanting impurities into the active layer to form a source / drain region; with an insulating material Forming an interlayer insulating film, forming a data line with a metal, stacking an insulating material, and etching together with the interlayer insulating film and the gate insulating film to form a contact hole to form a source / drain region and the data line of the active layer Forming a first transparent electrode connected to the data line and one source / drain region and a second transparent electrode connected to the other source / drain region and serving as a pixel electrode with a transparent conductive material. Manufacturing method. 제9항에서, 상기 활성층은 다결정 규소로 형성하는 박막 트랜지스터의 제조방법.The method of claim 9, wherein the active layer is formed of polycrystalline silicon. 제9항에서, 상기 게이트 절연막은 열산화로 형성하는 박막 트랜지스터의 제조방법.The method of claim 9, wherein the gate insulating layer is formed by thermal oxidation. 제9항에서, 상기 게이트는 다결정 규소로 형성하는 박막 트랜지스터의 제조방법.The method of claim 9, wherein the gate is formed of polycrystalline silicon. 제9항에서, 상기 소스/드레인 영역을 형성하는 단계는, 상기 활성층에 저농도로 불순물을 주입하는 단계, 상기 게이트의 측면에 감광막을 형성하고 고농도로 주입하는 단계, 확산 공정을 통하여 저농도의 LDD 영역과 고농도의 소스/드레인 영역을 형성하는 단계를 포함하는 박막 트랜지스터의 제조 방법.The method of claim 9, wherein the forming of the source / drain regions comprises: injecting impurities into the active layer at low concentration, forming a photoresist film on the side of the gate and injecting them at a high concentration; And forming a high concentration source / drain region. 제9항에 있어서, 상기 데이터선은 알루미늄으로 형성하는 박막 트랜지스터의 제조 방법.The method of claim 9, wherein the data line is formed of aluminum. 제14항에서, 상기 제1 및 제2투명 전극은 ITO로 형성하는 박막 트랜지스터의 제조 방법.The method of claim 14, wherein the first and second transparent electrodes are formed of ITO. 제15항에 있어서, 상기 데이터선과 동일한 패턴으로 접촉층을 단계를 더 포함하는 박막 트랜지스터의 제조 방법.The method of claim 15, further comprising forming a contact layer in the same pattern as the data line. 제16항에서, 상기 접촉층은 질화티타늄으로 형성하는 박막 트랜지스터의 제조 방법.The method of claim 16, wherein the contact layer is formed of titanium nitride. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061861A 1995-12-28 1995-12-28 Thin film transistor and manufacture thereof KR100212270B1 (en)

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