WO2012133157A1 - Array substrate for liquid crystal panel and liquid crystal panel - Google Patents

Array substrate for liquid crystal panel and liquid crystal panel Download PDF

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Publication number
WO2012133157A1
WO2012133157A1 PCT/JP2012/057469 JP2012057469W WO2012133157A1 WO 2012133157 A1 WO2012133157 A1 WO 2012133157A1 JP 2012057469 W JP2012057469 W JP 2012057469W WO 2012133157 A1 WO2012133157 A1 WO 2012133157A1
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WIPO (PCT)
Prior art keywords
wiring
semiconductor layer
array substrate
liquid crystal
source wiring
Prior art date
Application number
PCT/JP2012/057469
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French (fr)
Japanese (ja)
Inventor
達朗 黒田
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シャープ株式会社
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Publication of WO2012133157A1 publication Critical patent/WO2012133157A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to an array substrate for a liquid crystal panel and a liquid crystal panel.
  • the present invention also relates to a liquid crystal display device including a liquid crystal panel. Note that this application claims priority based on Japanese Patent Application No. 2011-75310 filed on Mar. 30, 2011, the entire contents of which are incorporated herein by reference. .
  • the liquid crystal display device includes a liquid crystal panel in which liquid crystal is sealed between a pair of translucent substrates, and a backlight disposed on the back side of the liquid crystal panel.
  • a backlight disposed on the back side of the liquid crystal panel.
  • light emitted from the backlight is irradiated from the back side of the liquid crystal panel, so that an image displayed on the liquid crystal panel can be visually recognized (Patent Document 1).
  • FIG. 21 is a perspective view showing a configuration of the liquid crystal panel 1000 shown in Patent Document 1.
  • the liquid crystal panel 1000 shown in FIG. 21 includes an array substrate (lower substrate) 110 including thin film transistors (TFTs) 140 and a color filter substrate (upper substrate) 120 including color filter layers 122.
  • a liquid crystal layer 130 is disposed between the array substrate 110 and the color filter substrate 120.
  • a pixel electrode 111 is formed on the array substrate 110.
  • a pixel region 115 is defined by the pixel electrode 111.
  • gate wiring 112 and data wiring 114 are formed on the array substrate 110.
  • the TFT 140 is connected to the gate line 112 and the data line 114.
  • the TFT 140 is disposed adjacent to the intersection of the gate wiring 112 and the data wiring 114, and includes a gate electrode 141, a semiconductor layer 142, a source electrode 144, and a drain electrode 146.
  • the drain electrode 146 of the TFT 140 is connected to the pixel electrode 111.
  • the color filter substrate (CF substrate) 120 includes a color filter layer 122 including red (R), green (G), and blue (B) sub-color filter layers 122a, 122b, and 122c.
  • the sub color filter layers 122 a, 122 b, and 122 c are divided by the black matrix 123.
  • a common electrode 124 is formed on the liquid crystal layer 130 side of the CF substrate 120.
  • FIG. 22 is a schematic plan view of the array substrate 110 based on one pixel region.
  • a TFT 140 that is a switching element, a gate wiring 112, a data wiring 114, and a pixel electrode 111 are formed on a translucent substrate 150. More specifically, in the array substrate 110, the pixel electrodes 111 corresponding to the pixel regions are arranged in a matrix, and the TFT 140 is formed for each pixel region. A large number of gate lines 112 and a large number of data lines 114 are formed in order to apply signals to each TFT 140.
  • the gate wiring 112 and the data wiring 114 that transmit different signals to the TFT 140 cannot be formed in the same layer. Therefore, the gate wiring 112 and the data wiring 114 are formed in different layers with an insulating film interposed therebetween.
  • a defect in which the upper data wiring 114 is disconnected may occur due to a step of the lower gate wiring 112.
  • Patent Document 2 is proposed as a structure that alleviates a shortage of drain electrodes and coverage due to a stepped portion and reduces defects such as disconnection and point defects.
  • a buffer wiring is formed in the vicinity of the lower gate wiring 112 to prevent the data wiring 114 from being disconnected. That is, by forming a buffer wiring in the vicinity of the gate wiring, the slope of the portion where the source wiring crosses the pattern of the gate wiring is smoothed, thereby preventing disconnection of the source wiring at the jumping step.
  • the present invention has been made in view of such a point, and a main object thereof is to provide an array substrate for a liquid crystal panel and a liquid crystal panel capable of suppressing disconnection of a source wiring.
  • An array substrate for a liquid crystal panel according to the present invention is an array substrate for a liquid crystal panel in which pixels are arranged in a matrix having rows and columns, and an auxiliary capacitance wiring extending in a row direction and positioned above the auxiliary capacitance wiring. And a source wiring extending in the column direction.
  • the auxiliary capacitance wiring is formed on a substrate, and an insulating layer is formed on the substrate so as to cover the auxiliary capacitance wiring.
  • a semiconductor layer is formed on the insulating layer in an intersection region of the auxiliary capacitance wiring and the source wiring, and the source wiring is formed on the insulating layer so as to cover the semiconductor layer. Yes.
  • the semiconductor layer formed on the insulating layer has a step mitigation pattern for mitigating a step gradient of the source wiring in the intersection region.
  • the thickness of the semiconductor layer is smaller than the thickness of the auxiliary capacitance wiring.
  • the semiconductor layer has at least a two-step structure.
  • the semiconductor layer extends along a row direction which is a direction parallel to the storage capacitor wiring.
  • the semiconductor layer includes a first semiconductor layer extending along a first side of the storage capacitor line and a second semiconductor layer extending along a second side of the storage capacitor line. Yes.
  • a portion of the source wiring located on the semiconductor layer is a curved portion.
  • a portion of the source wiring located on the semiconductor layer is a curved portion.
  • the semiconductor layer is formed in all the intersecting regions of the storage capacitor line and the source line.
  • a thin film transistor is formed in each of the pixels arranged in the matrix.
  • the thin film transistor includes a source electrode extending from the source wiring and a drain electrode disposed opposite to the source electrode, and a drain wiring connected to the pixel electrode extends from the drain electrode. An end of the drain wiring is connected to the auxiliary capacitance wiring.
  • a liquid crystal panel according to the present invention includes the array substrate, a color filter substrate disposed to face the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. It is a liquid crystal panel.
  • a liquid crystal display device is a liquid crystal display device including the liquid crystal panel and a backlight unit that irradiates the liquid crystal panel with light.
  • the semiconductor layer is formed on the insulating layer in the intersection region between the storage capacitor line extending in the row direction and the source line extending in the column direction, and the source line covers the semiconductor layer. Therefore, the step difference over which the source wiring crosses the intersection region is moderated by the semiconductor layer. As a result, an array substrate for a liquid crystal panel that can suppress disconnection of the source wiring can be realized.
  • FIG. 6 is a partially enlarged view schematically showing the upper surface configuration of an array substrate 210 of a comparative example.
  • A) is an enlarged view of the intersection area
  • (b) is sectional drawing of the intersection area
  • FIG. 4 is a cross-sectional view schematically showing a state of a current of a source wiring 34 in an intersection region 40.
  • FIG. It is sectional drawing which shows typically the mode of the electric current of the source wiring 134 in the cross
  • (A) is a top view of the intersection region 40 in the array substrate 11, and (b) is a cross-sectional view of the intersection region 40. 4 is a cross-sectional view schematically showing a state of a current of a source wiring 34 in an intersection region 40.
  • FIG. 4 is a cross-sectional view showing a curved portion 34c of a source wiring 34 that covers a semiconductor layer 41 on an insulating layer 39.
  • FIG. 3 is a cross-sectional view of an intersecting region 40 in the array substrate 11.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 4 is a top view showing a semiconductor layer 41 in an intersecting region 40.
  • FIG. 2 is a schematic plan view of an array substrate 110 based on one pixel region.
  • FIG. 1 is an exploded perspective view schematically showing a configuration of a liquid crystal display device 100 according to an embodiment of the present invention.
  • the liquid crystal display device 100 of the present embodiment is a liquid crystal display device capable of displaying an image.
  • the liquid crystal display device 100 includes a liquid crystal panel 10 and a backlight unit 20 that irradiates the liquid crystal panel 10 with light.
  • the liquid crystal panel 10 of the present embodiment has a size of, for example, 20 inches to 110 inches (typically 32 inches to 60 inches).
  • the liquid crystal panel 10 of the present embodiment generally has a rectangular shape as a whole, and is composed of a pair of translucent substrates (glass substrates) 11 and 12. Both the substrates 11 and 12 are arranged to face each other, and a liquid crystal layer (not shown) is provided between them.
  • the liquid crystal layer is made of a liquid crystal material whose optical characteristics change with application of an electric field between the substrates 11 and 12.
  • a sealing agent (not shown) is provided on the outer edge portions of the substrates 11 and 12 to seal the liquid crystal layer. Further, polarizing plates 13 and 13 are attached to the outer surfaces of both the substrates 11 and 12, respectively.
  • the back side of the substrates 11 and 12 is the array substrate (TFT substrate) 11, while the front side is the color filter substrate (CF substrate) 12.
  • the array substrate 11 of this embodiment is an array substrate for a liquid crystal panel in which pixels are arranged in a matrix having rows and columns. Although details will be described later, in the configuration of the present embodiment, the gate wiring extends in the row direction and the source wiring extends in the column direction. Each pixel is provided with a thin film transistor (TFT). Since the row direction and the column direction are for convenience, the relationship may be reversed in addition to the case where the row direction means the horizontal direction and the column direction means the vertical direction.
  • TFT thin film transistor
  • the backlight unit 20 of the present embodiment is a light source unit that irradiates the liquid crystal panel 10 with light.
  • the backlight unit 20 in the example shown in FIG. 1 is an edge light type backlight unit.
  • the backlight unit 20 of the present embodiment includes a plurality of light emitting elements 23 and a light guide plate 22 that irradiates the liquid crystal panel 10 with light emitted from the light emitting elements 23.
  • the light emitting element 23 of the present embodiment is an LED element (point light source).
  • a plurality of LED elements 23 are mounted on a wiring board 25.
  • the LED element 23 is arranged to face one of the side surfaces (incident surface) 22b of the light guide plate 22, and light emitted from the LED element 23 enters the light guide plate 22 from the incident surface 22b of the light guide plate 22. Incident.
  • the light guide plate 22 is an optical member that irradiates light incident on the incident surface 22b in a planar shape from the light emitting surface (main surface) 22a.
  • the light guide plate 22 is made of, for example, an acrylic plate.
  • a dot pattern (not shown) serving as a reflective layer is formed on the bottom surface 22c of the light guide plate 22 of the present embodiment. This dot pattern is formed by printing using ink or the like that forms a reflection pattern or a diffusion pattern.
  • an optical sheet 21 (21a to 21c) is disposed between the light guide plate 22 and the liquid crystal panel 10.
  • the optical sheets 21a to 21c are, for example, a lens sheet, a prism sheet, and a diffusion plate, respectively. Note that the configuration of the optical sheet 21 is not limited to these, and other configurations may be adopted.
  • the backlight unit 20 of this embodiment includes a backlight chassis 28 that houses the light guide plate 22.
  • the backlight chassis 28 of the present embodiment is made of a metal material (for example, aluminum, iron, etc.), and is a sheet metal member that covers the entire back surface of the liquid crystal display device 100.
  • a reflective sheet 27 is disposed between the backlight chassis 28 and the light guide plate 22.
  • a bezel 29 is provided in the liquid crystal display device 100 of the present embodiment.
  • the bezel 29 is made of a metal material (for example, aluminum or iron), and is a frame member that presses and fixes the outer edge portion of the liquid crystal panel.
  • the liquid crystal panel 10, the optical sheet 21, the light guide plate 22, the wiring board (LED board) 25 on which the LED elements 23 are mounted, and the reflection sheet 27 are stored in the backlight chassis 28.
  • a bezel 29 is attached to the backlight chassis 28.
  • the edge light type backlight unit 20 using the LED element 23 is shown, but the configuration is not limited thereto.
  • an edge light type backlight unit 20 using another light emitting element for example, a cold cathode fluorescent lamp (CCFL)
  • CCFL cold cathode fluorescent lamp
  • an LED element, a cold cathode tube, or the like can be used as the light emitting element.
  • FIG. 2 is a partially enlarged view schematically showing the upper surface configuration of the array substrate 11 of the present embodiment.
  • the array substrate 11 of the present embodiment has pixels arranged in a matrix having rows and columns.
  • the gate wiring 33 extends in the row direction (arrow 51)
  • the source wiring 34 extends in the column direction (arrow 52 direction).
  • a TFT element 30 as a switching element is formed at the intersection of the gate wiring 33 and the source wiring 34.
  • the TFT element 30 includes a semiconductor layer 31 serving as a channel layer, a source electrode 32 s extending from the source wiring 34, and a drain electrode 32 d disposed to face the source electrode 32 s.
  • the semiconductor layer 31 is made of, for example, silicon (amorphous silicon, polycrystalline silicon, etc.).
  • a portion of the gate wiring 33 located below the semiconductor layer 31 is a gate electrode.
  • a gate insulating film is formed between the gate electrode and the semiconductor layer 31.
  • a source electrode 32s and a drain electrode 32d are disposed on the surface of the semiconductor layer 31, and a channel region is formed between the source electrode 32s and the drain electrode 32d.
  • a drain wiring 36 extends from the drain electrode 32d.
  • a part 36d of the drain wiring 36 is connected to the pixel electrode 37 at the connection portion 36e.
  • the pixel electrode 37 is an electrode that defines each pixel, and is composed of a transparent electrode (for example, ITO).
  • the pixel of this embodiment is an area corresponding to R (red), G (green), and B (blue). Note that when the three regions R, G, and B are collectively referred to as a pixel, the region where the pixel electrode 37 is located may be referred to as a sub-pixel region or a pixel region.
  • the pixels of the present embodiment have R (red), G (green), B (blue), and Y (yellow). It becomes the area corresponding to.
  • the pattern of the pixel electrode 37 is shown as an example in the configuration of the present embodiment, and a suitable specific pattern may be adopted as appropriate.
  • the auxiliary capacitance (Cs) is formed on the array substrate 11.
  • An auxiliary capacitance wiring (Cs wiring) 35 is formed on the array substrate 11.
  • the auxiliary capacitance (Cs) is formed by a Cs electrode, an insulating film (not shown), and a pixel electrode 37 that are located in a part of the Cs wiring 35.
  • the insulating film (dielectric layer) constituting the auxiliary capacitor (Cs) is located between the Cs electrode and the pixel electrode 37, and the auxiliary capacitor (Cs) is formed between the Cs wiring 35 and the pixel electrode 37. It is formed at the intersection.
  • the auxiliary capacitor (Cs) has a role of supplying charges to the liquid crystal layer and maintaining the luminance of the pixel in a period in which the gate signal is OFF.
  • the end portion 36 g of the drain wiring 36 is connected to the auxiliary capacitance wiring (Cs wiring) 35.
  • the drain wiring 36 is connected to the Cs wiring 35 through lead portions 36d and 36f.
  • the Cs wiring 35 extends in the row direction (arrow 51), similarly to the gate wiring 33.
  • the source wiring 34 is located above the Cs wiring 35, and the array substrate 11 has an intersection region 40 where the source wiring 34 and the Cs wiring 35 intersect each other.
  • 3A and 3B are a top view and a cross-sectional view schematically showing the configuration of the source wiring 34 and the Cs wiring 35 in the intersection region 40, respectively.
  • the Cs wiring 35 is formed on a substrate 38 (a glass substrate constituting the array substrate 11).
  • the substrate 38 is made of a glass substrate, another layer (insulating layer or the like) may be formed on the surface of the glass substrate.
  • An insulating layer 39 is formed on the substrate 38 so as to cover the Cs wiring 35.
  • the insulating layer 39 has a function of an interlayer insulating film between the Cs wiring 35 and the source wiring 34. Since the insulating layer 39 is formed so as to get over the Cs wiring 35, a step 45 is formed on both sides of the Cs wiring 35.
  • the semiconductor layer 41 is formed on the insulating layer 39 in the intersecting region 40 between the Cs wiring 35 and the source wiring 34.
  • the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41.
  • the semiconductor layer 41 of the present embodiment has a function as a step relief pattern that relaxes the gradient of the step 45 of the source wiring 34 in the intersecting region 40.
  • the semiconductor layer 41 of the present embodiment has a structure that is thinner than the thickness of the Cs wiring 35.
  • the semiconductor layer 41 of the present embodiment extends along the row direction 51 which is a direction parallel to the Cs wiring 35.
  • the semiconductor layer 41 includes the first semiconductor layer 41f extending along the first side (35f) of the Cs wiring 35 and the second semiconductor extending along the second side (35s) of the Cs wiring 35. Layer 41s.
  • the gate wiring 33 shown in FIG. 2 is formed in the same level layer as the Cs wiring 35. Therefore, the source wiring 34 is located in an upper layer than the gate wiring 33. In the array substrate 11 of this embodiment, there is an intersection region 47 where the source wiring 34 and the gate wiring 33 intersect each other.
  • the source wiring 34 has a main body 34 a extending in the column direction 52, and the main body 34 a of the source wiring 34 extends in the column direction in the intersecting regions 40 and 47 as well as the main body 34 a. ing.
  • the source wiring 34 is made of copper.
  • the Cs wiring 35 and the gate wiring 33 are also made of copper.
  • the source wiring 34, the Cs wiring 35, and the gate wiring 33 are not limited to the copper wiring, and may be composed of other metal materials (aluminum) or a multilayer film (for example, Cu ⁇ Mo, Cu ⁇ Ti). It may be configured as follows. Further, the source wiring 34 (for example, copper wiring) and the Cs wiring 35 / gate wiring 33 may be made of different materials.
  • the semiconductor layer 41 is formed on the insulating layer 39 in the intersection region 40 between the Cs wiring 35 extending in the row direction 51 and the source wiring 34 extending in the column direction 52.
  • the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41. Therefore, the step 45 over which the source wiring 34 crosses the intersection region 40 can be moderated by the semiconductor layer 41. As a result, the liquid crystal panel array substrate 11 capable of suppressing the disconnection of the source wiring 34 can be realized.
  • FIG. 4 is a partially enlarged view schematically showing the upper surface configuration of the array substrate 210 of the comparative example.
  • the TFT element 230 includes a semiconductor layer 231, a source electrode 232 s, and a drain electrode 232 d.
  • a drain wiring 236d extending from the drain electrode 232d is connected to the pixel electrode 237 at a connection portion 236e.
  • the end of the drain wiring 236d is connected to the Cs wiring 235.
  • FIG. 5A is an enlarged view of the intersection region 240
  • FIG. 5B is a cross-sectional view of the intersection region 240. As shown in FIG.
  • the Cs wiring 235 extends on the glass substrate 238.
  • An insulating layer 239 is formed on the glass substrate 238 so as to cover the Cs wiring 235.
  • a source wiring 234 is formed on the insulating layer 239. As shown in the drawing, the source wiring 234 extends so as to get over the step 245 formed by the Cs wiring 235 in the intersection region 240.
  • the source wiring 234 is formed by patterning a metal film by etching. Therefore, as shown in FIGS. 6A and 6B, disconnection (246) may occur at the portion where the source wiring 234 gets over the stepped portion 245 by the Cs wiring 235 due to the influence of erosion due to etching residue or the like. Increases nature. Furthermore, when the source wiring 234 is a copper wiring, disconnection (246) may occur in the stepped portion 245 due to oxidative corrosion of the copper wiring.
  • the semiconductor layer 41 that relaxes the gradient of the step 45 in the intersecting region 40 is formed, so that disconnection of the source wiring 34 can be suppressed.
  • the presence of the semiconductor layer 41 that reduces the gradient of the step 45 can smooth the flow of the current 50 of the source wiring 34 in the intersecting region 40.
  • the thickness of the semiconductor layer 41 is smaller than the thickness of the Cs wiring 35, it is easy to smooth the change in the step 45.
  • FIG. 8 shows a structure in which the buffer wiring 141 is formed on the glass substrate 38 in the intersecting region 240 shown in FIGS.
  • the presence of the buffer wiring 141 makes it possible to make the slope (slope) of the step (245a, 245b) over which the source wiring 134 gets over relatively smooth.
  • the flow of the current 150 of the source wiring 134 may not flow smoothly due to the influence of the step 245a at the location (150a) corresponding to the step 245a.
  • the step 245a is smoother than the structure of the present embodiment shown in FIG. It is difficult to make.
  • the thickness of the semiconductor layer 41 is made thinner than the thickness of the Cs wiring 35, so that the gradient of the step (45) can be smoothly changed compared to the structure shown in FIG. It becomes easy to make.
  • the buffer wiring 141 may be difficult to form on both sides of the Cs wiring 235.
  • the semiconductor layer 41 can be formed on the insulating layer 39, the problem as in the structure shown in FIG. 8, that is, the problem that the buffer wiring 141 is difficult to form can be avoided. Is easy.
  • the semiconductor layer 41 is formed in each of the intersecting regions 40 of the source wiring 34 and the Cs wiring 35. It is also possible to select the region 40 and form the semiconductor layer 41.
  • the semiconductor layer 41 is formed in the intersection region 47 with the gate wiring 33 in order to reduce the step gradient as in the intersection region 40 with the Cs wiring 35. It doesn't matter.
  • the semiconductor layer 41 is formed on both sides of the gate wiring 33 on the insulating layer 39 in the intersection region 47. In this way, it becomes easy to suppress disconnection of the source wiring 34 over the gate wiring 33.
  • the width of the source wiring 34 is, for example, 5 to 8 ⁇ m.
  • the width of the gate wiring 33 is, for example, 10 to 20 ⁇ m.
  • the width of the Cs wiring 35 is, for example, 10 to 20 ⁇ m.
  • the thickness of the source wiring 34 is, for example, 3000 to 4500 mm, and the thickness of the gate wiring 33 and the Cs wiring 35 is, for example, 3000 to 6000 mm (typically 6000 mm).
  • the width of the semiconductor layer 41 is, for example, 10 to 50 ⁇ m, and the thickness of the semiconductor layer 41 is, for example, 1800 to 2500 mm (typically 2300 mm).
  • the thickness of the insulating layer 39 is, for example, 2500 to 4100 mm.
  • the thickness of the semiconductor layer 41 (typically 2300 mm) is smaller than the thickness of the Cs wiring 35 (typically 6000 mm). In the configuration shown in FIG. 3, the thickness of the semiconductor layer 41 is smaller than the thickness of the insulating layer 39.
  • FIGS. 9A and 9B are a top view and a cross-sectional view, respectively, of the intersecting region 40 in the array substrate 11 of the modified example of the present embodiment.
  • the semiconductor layer 41 has at least a two-step structure (41a, 41b).
  • the semiconductor layer 41 includes a first stepped portion 41a close to the Cs wiring 35 side and a second stepped portion 41b continuous to the first stepped portion 41a.
  • the thickness of the second step portion 41b is smaller than the thickness of the first step portion 41a.
  • the thickness of the first step portion 41a is 2300 mm, for example, and the thickness of the second step portion 41b is 1000 mm, for example.
  • the semiconductor layer 41 has the step structure (41a, 41b)
  • the gradient of the step 45 can be more smoothly relaxed as shown in FIG.
  • disconnection of the source wiring 34 can be further suppressed.
  • the flow of the current 50 of the source wiring 34 in the intersecting region 40 can be made smoother by the semiconductor layer 41 having the step structure (41a, 41b).
  • the step structure is not limited to the two-step structure (41a, 41b), and may be a three-step or more step structure.
  • FIGS. 11A and 11B are a top view and a cross-sectional view, respectively, of the intersecting region 40 in the array substrate 11 according to the modified example of the present embodiment.
  • the semiconductor layer 41 is formed slightly apart from the Cs wiring 35.
  • the semiconductor layer 41 can be formed so as to be in contact with the raised insulating layer 39 over the Cs wiring 35 and at a position away from the raised insulating layer 39 as in the structure shown in FIG. Even if the semiconductor layer 41 is formed so as to be separated in this way, the gradient of the step 45 can be relaxed.
  • FIG. 12 shows a structure in which the source wiring 34 is formed so as to cover the semiconductor layer 41 of the present embodiment.
  • a curved portion 34c is formed at a portion over the semiconductor layer 41.
  • the gradient of the step 45 can be relaxed.
  • the semiconductor layer 41 thinner than the thickness of the Cs wiring 35 is formed, and when the source wiring 34 is deposited on the semiconductor layer 41 narrower than the width of the Cs wiring 35, A portion 34c of the source wiring 34 located on the source wiring 34 has a smooth curved surface. The disconnection of the source wiring 34 can be suppressed by the curved portion 34c having a smooth curved surface.
  • FIG. 13 shows a structure in which the slope of the step 45 is relaxed by using the curved portion 34 c of the source wiring 34.
  • the source wiring 34 is formed so as to get over the semiconductor layer 41, and the part that goes over becomes a curved portion 34 c so that the gradient of the step 45 is relaxed.
  • the shape of the upper surface of the semiconductor layer 41 is not limited to a rectangle, and various shapes can be employed.
  • 14 to 16 are top views schematically showing the shape of the semiconductor layer 41, respectively.
  • a recess 42 a is formed in a part of the semiconductor layer 41. Specifically, a recess (or notch) 42 a is formed in a portion located below the source wiring 34. In the structure shown in FIG. 14, the portion not covered with the source wiring 34 has a side 42 b extending obliquely with respect to the side 34 e of the source wiring 34.
  • a wavy shape portion 43 a is formed in a part of the semiconductor layer 41. Specifically, a portion 43 a having a waveform side is formed at a portion located below the source wiring 34. In the structure shown in FIG. 15, the portion not covered with the source wiring 34 has a side 43 b extending obliquely with respect to the side 34 e of the source wiring 34.
  • the shape of the portion of the semiconductor layer 41 located below the source wiring 34 is not limited to the concave portion 42a shown in FIG. 14 and the corrugated shape 43a shown in FIG. 15, but other shapes (for example, convex, It is also possible to use a triangular shape, an arc shape, an uneven shape, or the like.
  • the semiconductor layer 41 has a trapezoidal shape (44a, 44b). Specifically, the semiconductor layer 41 includes a side 44 a extending in parallel with the Cs wiring 35 and a side 44 b extending obliquely with respect to the side 34 e of the source wiring 34. In the illustrated example, a part of the side 44 a of the semiconductor layer 41 is located below the source line 34, and the other part extends outside the source line 34.
  • the semiconductor layer 41 in a trapezoidal shape (44a, 44b) as shown in FIG.
  • the semiconductor layer 41 having a trapezoidal shape (44a, 44b) is formed so as to be covered under the source wiring 34.
  • the trapezoidal shape (44a, 44b) so as to be covered under the source wiring 34, even if the source wiring 34 is formed off the center of the semiconductor layer, a region where the etching solution easily enters is generated. Can be difficult.
  • FIGS. 18A to 18D are process cross-sectional views for explaining the manufacturing method of the present embodiment.
  • an insulating layer 39 is formed so as to cover the Cs wiring 35, and then on the insulating layer 39, A semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited.
  • the Cs wiring 35 is formed by depositing a metal film (for example, Cu film) on the glass substrate 38 and then performing wet etching using a resist pattern (not shown) as a mask.
  • the gate wiring 33 is also formed by this wet etching.
  • the etching solution (etchant) is, for example, a solution containing a fluorinated compound.
  • the insulating layer 39 of the present embodiment is made of, for example, silicon nitride and has a thickness of, for example, 3000 to 4500 mm.
  • the semiconductor material 41c is made of, for example, silicon.
  • the same material as the semiconductor layer 31 (see FIG. 2) constituting the TFT element 30 can be used as the semiconductor material 41c. More specifically, in the step of forming the semiconductor layer 31 constituting the TFT element 30, it is preferable to deposit the semiconductor material 41 c in the intersecting region 40.
  • a resist pattern 41m that defines the pattern of the semiconductor layer 41 is formed on the semiconductor material 41c.
  • the resist pattern 41m is a resin pattern formed by photolithography.
  • the semiconductor layer 41 is obtained from the semiconductor material 41c by etching the semiconductor material 41c using the resist pattern 41m as a mask.
  • the semiconductor layer 41 is formed by patterning the semiconductor material 41c by dry etching.
  • the portion of the semiconductor material 41c sandwiched between the resist pattern 41m and the insulating layer 39 is less likely to be etched than the other portions, so that the semiconductor layer 41 often has a slight step 41d. .
  • the resist pattern 41m is removed after the dry etching.
  • a source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41.
  • a metal film for example, a Cu film
  • a resist pattern for example, a resist pattern
  • the etching solution is, for example, a solution containing a fluorinated compound.
  • the semiconductor layer 41 that reduces the gradient of the step 45 of the source wiring 34 is formed in the intersection region 40 between the Cs wiring 35 and the source wiring 34, disconnection of the source wiring 34 is also prevented. It becomes easy to suppress.
  • FIGS. 19A to 19D are process cross-sectional views for explaining another manufacturing method of the present embodiment.
  • a Cs wiring 35 and an insulating layer 39 are formed on a glass substrate 38, and then a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39. .
  • a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39.
  • a resist pattern 41n that defines the pattern of the semiconductor layer 41 having at least a two-stage structure is formed.
  • the resist pattern 41n shown in FIG. 19B is formed so as to have a step 41g by halftone photography. Note that the resist pattern 41n is removed after the dry etching.
  • the semiconductor material 41c is dry-etched, so that the first step portion 41a and the second step portion 41b are formed from the semiconductor material 41c.
  • a semiconductor layer 41 having the following is obtained.
  • a small step 41d is formed in the semiconductor layer 41 as in FIG.
  • the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41 having the step portions (41a, 41b). Specifically, a metal film (for example, a Cu film) serving as a material (source metal) of the source wiring 34 is stacked on the insulating layer 39 and then wet-etched using a resist pattern (not shown) as a mask. Is done.
  • a metal film for example, a Cu film
  • a resist pattern not shown
  • the semiconductor layer 41 having at least two step portions (41a, 41b) can be formed in the intersecting region 40 of the Cs wiring 35 and the source wiring 34. Therefore, since the step 45 can be changed more smoothly, disconnection of the source wiring 34 can be more effectively suppressed.
  • FIGS. 20A to 20D are process cross-sectional views for explaining another manufacturing method of the present embodiment.
  • a Cs wiring 35 and an insulating layer 39 are formed on a glass substrate 38, and then a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39. .
  • a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39.
  • a resist pattern 41m that defines the pattern of the semiconductor layer 41 is formed on the semiconductor material 41c at a position slightly separated from the semiconductor material 41c at a position over the Cs wiring 35.
  • the semiconductor layer 41 is obtained from the semiconductor material 41c by dry etching the semiconductor material 41c using the resist pattern 41m as a mask. Since the resist pattern 41m is formed slightly apart, the slight step 41d shown in FIG. 18C is not formed in the semiconductor layer 41. Further, after dry etching, the resist pattern 41m is removed.
  • the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41.
  • a metal film for example, a Cu film
  • a resist pattern not shown
  • the semiconductor layer 41 thinner than the thickness of the Cs wiring 35 can be formed in the intersection region 40 between the Cs wiring 35 and the source wiring 34, and as a result, the source wiring 34. Can be suppressed.
  • the liquid crystal display device 100 of the present embodiment shown in FIG. 1 can include a control device (not shown) that controls the driving of the liquid crystal panel 10 and / or the light emitting elements (for example, LED elements) 23.
  • a control device comprises a semiconductor integrated circuit.
  • the control device of the present embodiment includes a liquid crystal panel driving unit and an LED driving unit.
  • the liquid crystal panel driving unit is a part that displays an image on the liquid crystal panel 10 by driving the liquid crystal panel 10, and corresponds to a driver circuit such as a gate driver or a source driver.
  • the LED drive unit is a part for individually turning on / off each LED element 23 or changing the light emission intensity, and is configured by a driver circuit including, for example, a switch.
  • the light emitting element is a cold cathode fluorescent lamp (CCFL)
  • the LED driving unit is a CCFL driving unit (or a backlight driving unit).
  • a plurality of the LED elements 23 of the present embodiment are arranged so as to emit light to the light guide plate 22, and are made of, for example, white LEDs.
  • the LED elements 23 are arranged on one side of the light guide plate 22, but not limited thereto, the LED elements 23 are arranged on two sides or more (for example, three sides) of the light guide plate 22. Is also possible.
  • the LED element 23 can also be used in the configuration of a direct type LED backlight.
  • the image display unit is configured by using one liquid crystal panel 10, but one image display unit (multi-display) may be configured by combining a plurality of liquid crystal panels 10. Is possible.
  • the liquid crystal display device 100 in which such a plurality of liquid crystal panels 10 are combined can be used for a large-screen digital signage (for example, a display device of 100 inches or more).
  • an array substrate for a liquid crystal panel and a liquid crystal panel that can suppress disconnection of the source wiring.
  • Liquid crystal panel 11 Array substrate (TFT substrate) DESCRIPTION OF SYMBOLS 12 Color filter substrate 13 Polarizing plate 20 Backlight unit 21 Optical sheet 22 Light guide plate 23 Light emitting element 25 Wiring board 27 Reflective sheet 28 Backlight chassis 29 Bezel 30 TFT element 31 Semiconductor layer 32d Drain electrode 32s Source electrode 33 Gate wiring 34 Source wiring 34a body part 34c bending part 35 auxiliary capacity wiring (Cs wiring) 36 Drain wiring 37 Pixel electrode 38 Substrate (glass substrate) 39 Insulating layer 40 Crossing region 41 Semiconductor layer 41a First step portion 41b Second step portion 41c Semiconductor material 41f First semiconductor layer 41s Second semiconductor layer 41m, 41n Resist pattern 42a Recess 43a Waveform portion 45 Step 47 Crossing region 50 Current 100 Liquid crystal display device 1000 Liquid crystal panel

Abstract

Provided is an array substrate that is for a liquid crystal panel and that is able to suppress disconnection of source wiring. The array substrate (11) that is for a liquid crystal panel and that has pixels disposed in a matrix form having rows and columns is provided with: auxiliary capacitor wiring (35) extending in the row direction (51); and source wiring (34) disposed in a higher layer than the auxiliary capacitor wiring (35) and extending in the column direction (52). The auxiliary capacitor wiring (Cs wiring) (35) is formed on a substrate (38), and an insulating layer (39) is formed on the substrate (38) in a manner so as to cover the auxiliary capacitor wiring (35). In the region (40) of intersection of the auxiliary capacitor wiring (35) and the source wiring (34), a semiconductor layer (41) is formed on the insulating layer (39), and the source wiring (34) is formed on the insulating layer (39) in a manner so as to cover the semiconductor layer (41).

Description

液晶パネル用アレイ基板および液晶パネルArray substrate for liquid crystal panel and liquid crystal panel
　本発明は、液晶パネル用アレイ基板および液晶パネルに関する。本発明はまた、液晶パネルを備えた液晶表示装置に関する。
　なお、本出願は２０１１年３月３０日に出願された日本国特許出願２０１１－７５３１０号に基づく優先権を主張しており、その出願の全内容は本明細書中に参照として組み入れられている。 The present invention relates to an array substrate for a liquid crystal panel and a liquid crystal panel. The present invention also relates to a liquid crystal display device including a liquid crystal panel.
Note that this application claims priority based on Japanese Patent Application No. 2011-75310 filed on Mar. 30, 2011, the entire contents of which are incorporated herein by reference. .
　液晶表示装置は、一対の透光性基板の間に液晶が封止されてなる液晶パネルと、当該液晶パネルの背面側に配置されたバックライトとから構成されている。液晶表示装置では、バックライトから出射された光が液晶パネルの背面側から照射されることによって、液晶パネルに表示された画像が視認可能となる（特許文献１）。 The liquid crystal display device includes a liquid crystal panel in which liquid crystal is sealed between a pair of translucent substrates, and a backlight disposed on the back side of the liquid crystal panel. In the liquid crystal display device, light emitted from the backlight is irradiated from the back side of the liquid crystal panel, so that an image displayed on the liquid crystal panel can be visually recognized (Patent Document 1).
　図２１は、特許文献１に示した液晶パネル１０００の構成を示す斜視図である。図２１に示した液晶パネル１０００は、薄膜トランジスタ（ＴＦＴ）１４０を含むアレイ基板（下部基板）１１０と、カラーフィルタ層１２２を含むカラーフィルタ基板（上部基板）１２０とから構成されている。アレイ基板１１０とカラーフィルタ基板１２０との間には、液晶層１３０が配置されている。 FIG. 21 is a perspective view showing a configuration of the liquid crystal panel 1000 shown in Patent Document 1. As shown in FIG. The liquid crystal panel 1000 shown in FIG. 21 includes an array substrate (lower substrate) 110 including thin film transistors (TFTs) 140 and a color filter substrate (upper substrate) 120 including color filter layers 122. A liquid crystal layer 130 is disposed between the array substrate 110 and the color filter substrate 120.
　アレイ基板１１０には、画素電極１１１が形成されている。この画素電極１１１によって画素領域１１５が規定されている。また、アレイ基板１１０には、ゲート配線１１２とデータ配線１１４とが形成されている。ＴＦＴ１４０は、ゲート配線１１２およびデータ配線１１４に連結されている。また、ＴＦＴ１４０は、ゲート配線１１２およびデータ配線１１４の交差地点に隣接して配置され、ゲート電極１４１、半導体層１４２、ソース電極１４４、ドレイン電極１４６を含む。ＴＦＴ１４０のドレイン電極１４６は、画素電極１１１に連結されている。 A pixel electrode 111 is formed on the array substrate 110. A pixel region 115 is defined by the pixel electrode 111. Further, gate wiring 112 and data wiring 114 are formed on the array substrate 110. The TFT 140 is connected to the gate line 112 and the data line 114. The TFT 140 is disposed adjacent to the intersection of the gate wiring 112 and the data wiring 114, and includes a gate electrode 141, a semiconductor layer 142, a source electrode 144, and a drain electrode 146. The drain electrode 146 of the TFT 140 is connected to the pixel electrode 111.
　カラーフィルタ基板（ＣＦ基板）１２０は、赤色（Ｒ）、緑色（Ｇ）、青色（Ｂ）のサブカラーフィルタ層１２２ａ、１２２ｂ、１２２ｃを含むカラーフィルタ層１２２を含んでいる。サブカラーフィルタ層１２２ａ、１２２ｂ、１２２ｃは、ブラックマトリクス１２３によって区分けされている。また、ＣＦ基板１２０の液晶層１３０側には、共通電極１２４が形成されている。 The color filter substrate (CF substrate) 120 includes a color filter layer 122 including red (R), green (G), and blue (B) sub-color filter layers 122a, 122b, and 122c. The sub color filter layers 122 a, 122 b, and 122 c are divided by the black matrix 123. A common electrode 124 is formed on the liquid crystal layer 130 side of the CF substrate 120.
　画素電極１１１と共通電極１２４との間に電圧を印加すると、縦方向に電場が発生して、この電場によって、液晶層１３０の液晶が駆動する。これによって、異なる光の透過率によって画像を表現することができる。 When a voltage is applied between the pixel electrode 111 and the common electrode 124, an electric field is generated in the vertical direction, and the liquid crystal of the liquid crystal layer 130 is driven by this electric field. Thus, an image can be expressed by different light transmittances.
　図２２は、一つの画素領域を基準にしたアレイ基板１１０の概略的な平面図である。図２２に示したアレイ基板１１０では、透光性基板１５０の上に、スイッチング素子であるＴＦＴ１４０、ゲート配線１１２、データ配線１１４、画素電極１１１が形成される。より具体的には、アレイ基板１１０においては、画素領域に対応した画素電極１１１がマトリックス状に配列され、その画素領域ごとにＴＦＴ１４０が形成される。また、ＴＦＴ１４０ごとに信号を印加するために、多数のゲート配線１１２および多数のデータ配線１１４が形成されている。 FIG. 22 is a schematic plan view of the array substrate 110 based on one pixel region. In the array substrate 110 shown in FIG. 22, a TFT 140 that is a switching element, a gate wiring 112, a data wiring 114, and a pixel electrode 111 are formed on a translucent substrate 150. More specifically, in the array substrate 110, the pixel electrodes 111 corresponding to the pixel regions are arranged in a matrix, and the TFT 140 is formed for each pixel region. A large number of gate lines 112 and a large number of data lines 114 are formed in order to apply signals to each TFT 140.
　ここで、製造工程上、相互に異なる信号をＴＦＴ１４０に伝達するゲート配線１１２とデータ配線１１４とは、同一層には形成することができない。したがって、ゲート配線１１２とデータ配線１１４とは、それぞれ別の層に絶縁膜を介して形成される。図２２に示した例では、下層のゲート配線１１２を乗り越えるように上層のデータ配線１１４が延びる交差部１５５が存在する。そして、このような交差部１５５においては、下層のゲート配線１１２の段差によって、上層のデータ配線１１４が断線される不良が発生することがある。なお、段差部によるドレイン電極およびカバレージ不足を緩和して、断線や点欠陥などの不良を低減させる構造として、特許文献２に開示されるものが提案されている。 Here, in the manufacturing process, the gate wiring 112 and the data wiring 114 that transmit different signals to the TFT 140 cannot be formed in the same layer. Therefore, the gate wiring 112 and the data wiring 114 are formed in different layers with an insulating film interposed therebetween. In the example shown in FIG. 22, there is an intersection 155 where the upper data wiring 114 extends so as to get over the lower gate wiring 112. In such an intersecting portion 155, a defect in which the upper data wiring 114 is disconnected may occur due to a step of the lower gate wiring 112. In addition, what is disclosed in Patent Document 2 is proposed as a structure that alleviates a shortage of drain electrodes and coverage due to a stepped portion and reduces defects such as disconnection and point defects.
特開２００７－３１０３５１号公報JP 2007-310351 A 特開２００２－３２９７２６号公報JP 2002-329726 A
　この断線の問題に対して、特許文献１では、下層のゲート配線１１２の近傍にバッファ配線を形成することによって、データ配線１１４の断線を防ぐようにしている。すなわち、ゲート配線の近傍にバッファ配線を形成することによって、ソース配線がゲート配線のパターンを乗り越える部分のスロープを滑らかにすることにより、乗り越え段差におけるソース配線の断線を防止するようにしている。 In order to deal with this disconnection problem, in Patent Document 1, a buffer wiring is formed in the vicinity of the lower gate wiring 112 to prevent the data wiring 114 from being disconnected. That is, by forming a buffer wiring in the vicinity of the gate wiring, the slope of the portion where the source wiring crosses the pattern of the gate wiring is smoothed, thereby preventing disconnection of the source wiring at the jumping step.
　しかしながら、下層のゲート配線１１２の近傍にバッファ配線が形成できない場合があり得る。また、エッチング液の侵食によって断線が生じるのを防ぐ場合において、当該乗り越え部分のスロープをできるだけ滑らかにすることが望まれる場合もある。 However, there may be a case where a buffer wiring cannot be formed in the vicinity of the lower gate wiring 112. Further, when preventing the disconnection due to the etching solution erosion, it may be desired to make the slope of the crossing portion as smooth as possible.
　本発明はかかる点に鑑みてなされたものであり、その主な目的は、ソース配線の断線を抑制できる液晶パネル用アレイ基板および液晶パネルを提供することにある。 The present invention has been made in view of such a point, and a main object thereof is to provide an array substrate for a liquid crystal panel and a liquid crystal panel capable of suppressing disconnection of a source wiring.
　本発明に係る液晶パネル用アレイ基板は、行及び列を有するマトリックス状に画素が配置された液晶パネル用アレイ基板であり、行方向に延びる補助容量配線と、前記補助容量配線よりも上層に位置し、列方向に延びるソース配線とを備えている。前記補助容量配線は、基板の上に形成されており、前記基板の上には、前記補助容量配線を覆うように絶縁層が形成されている。前記補助容量配線と前記ソース配線との交差領域において、前記絶縁層の上に、半導体層が形成されており、前記ソース配線は、前記半導体層を覆うように前記絶縁層の上に形成されている。 An array substrate for a liquid crystal panel according to the present invention is an array substrate for a liquid crystal panel in which pixels are arranged in a matrix having rows and columns, and an auxiliary capacitance wiring extending in a row direction and positioned above the auxiliary capacitance wiring. And a source wiring extending in the column direction. The auxiliary capacitance wiring is formed on a substrate, and an insulating layer is formed on the substrate so as to cover the auxiliary capacitance wiring. A semiconductor layer is formed on the insulating layer in an intersection region of the auxiliary capacitance wiring and the source wiring, and the source wiring is formed on the insulating layer so as to cover the semiconductor layer. Yes.
　ある好適な実施形態において、前記絶縁層の上に形成される前記半導体層は、前記交差領域における前記ソース配線の段差の勾配を緩和する段差緩和パターンである。 In a preferred embodiment, the semiconductor layer formed on the insulating layer has a step mitigation pattern for mitigating a step gradient of the source wiring in the intersection region.
　ある好適な実施形態において、前記半導体層の厚さは、前記補助容量配線の厚さよりも小さい。 In a preferred embodiment, the thickness of the semiconductor layer is smaller than the thickness of the auxiliary capacitance wiring.
　ある好適な実施形態において、前記半導体層は、少なくとも２段の段差構造を有している。 In a preferred embodiment, the semiconductor layer has at least a two-step structure.
　ある好適な実施形態において、前記半導体層は、前記補助容量配線と平行な方向である行方向に沿って延びている。 In a preferred embodiment, the semiconductor layer extends along a row direction which is a direction parallel to the storage capacitor wiring.
　ある好適な実施形態において、前記半導体層は、前記補助容量配線の第１辺に沿って延びる第１半導体層と、前記補助容量配線の第２辺に沿って延びる第２半導体層とを含んでいる。 In a preferred embodiment, the semiconductor layer includes a first semiconductor layer extending along a first side of the storage capacitor line and a second semiconductor layer extending along a second side of the storage capacitor line. Yes.
　ある好適な実施形態において、前記ソース配線のうち前記半導体層の上に位置する部位は、湾曲部となっている。 In a preferred embodiment, a portion of the source wiring located on the semiconductor layer is a curved portion.
　ある好適な実施形態において、前記ソース配線のうち前記半導体層の上に位置する部位は、湾曲部となっている。 In a preferred embodiment, a portion of the source wiring located on the semiconductor layer is a curved portion.
　ある好適な実施形態において、前記補助容量配線と前記ソース配線との全ての前記交差領域において、前記半導体層が形成されている。 In a preferred embodiment, the semiconductor layer is formed in all the intersecting regions of the storage capacitor line and the source line.
　ある好適な実施形態において、前記マトリックス状に配置された画素のそれぞれには、薄膜トランジスタが形成されている。前記薄膜トランジスタには、前記ソース配線から延びるソース電極と、前記ソース電極に対向して配置されたドレイン電極とを備え、前記ドレイン電極からは、画素電極に接続されるドレイン配線が延びている。前記ドレイン配線の端部は、前記補助容量配線に接続されている。 In a preferred embodiment, a thin film transistor is formed in each of the pixels arranged in the matrix. The thin film transistor includes a source electrode extending from the source wiring and a drain electrode disposed opposite to the source electrode, and a drain wiring connected to the pixel electrode extends from the drain electrode. An end of the drain wiring is connected to the auxiliary capacitance wiring.
　本発明に係る液晶パネルは、上記アレイ基板と、前記アレイ基板に対向して配置されるカラーフィルタ基板と、前記アレイ基板と前記カラーフィルタ基板との間に配置される液晶層とを備えた、液晶パネルである。 A liquid crystal panel according to the present invention includes the array substrate, a color filter substrate disposed to face the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. It is a liquid crystal panel.
　本発明に係る液晶表示装置は、上記液晶パネルと、前記液晶パネルに光を照射するバックライトユニットとを備えた、液晶表示装置である。 A liquid crystal display device according to the present invention is a liquid crystal display device including the liquid crystal panel and a backlight unit that irradiates the liquid crystal panel with light.
　本発明によれば、行方向に延びる補助容量配線と、列方向に延びるソース配線との交差領域において、絶縁層の上に半導体層が形成されており、そして、ソース配線は、半導体層を覆うように絶縁層の上に形成されており、したがって、交差領域においてソース配線が乗り越える段差は、当該半導体層によって段差の勾配が緩和されている。その結果、ソース配線の断線を抑制できる液晶パネル用アレイ基板を実現することができる。 According to the present invention, the semiconductor layer is formed on the insulating layer in the intersection region between the storage capacitor line extending in the row direction and the source line extending in the column direction, and the source line covers the semiconductor layer. Therefore, the step difference over which the source wiring crosses the intersection region is moderated by the semiconductor layer. As a result, an array substrate for a liquid crystal panel that can suppress disconnection of the source wiring can be realized.
本発明の実施形態に係る液晶表示装置１００を説明するための分解斜視図である。It is a disassembled perspective view for demonstrating the liquid crystal display device 100 which concerns on embodiment of this invention. 本発明の実施形態に係る液晶パネル用アレイ基板１１の上面拡大図である。It is an upper surface enlarged view of the array substrate 11 for liquid crystal panels which concerns on embodiment of this invention. （ａ）は、アレイ基板１１における交差領域４０の上面図であり、（ｂ）は、交差領域４０の断面図である。(A) is a top view of the intersection region 40 in the array substrate 11, and (b) is a cross-sectional view of the intersection region 40. 比較例のアレイ基板２１０の上面構成を模式的に示す一部拡大図である。FIG. 6 is a partially enlarged view schematically showing the upper surface configuration of an array substrate 210 of a comparative example. （ａ）は、比較例における交差領域２４０の拡大図であり、（ｂ）は、交差領域２４０の断面図である。(A) is an enlarged view of the intersection area | region 240 in a comparative example, (b) is sectional drawing of the intersection area | region 240. FIG. （ａ）および（ｂ）は、それぞれ、ソース配線２３４が乗り越える部位２４２にて断線２４６が生じることを説明するための平面図および断面図である。(A) And (b) is the top view and sectional drawing for demonstrating that the disconnection 246 arises in the site | part 242 where the source wiring 234 gets over, respectively. 交差領域４０におけるソース配線３４の電流の様子を模式的に示す断面図である。4 is a cross-sectional view schematically showing a state of a current of a source wiring 34 in an intersection region 40. FIG. 比較例となる交差領域２４０におけるソース配線１３４の電流の様子を模式的に示す断面図である。It is sectional drawing which shows typically the mode of the electric current of the source wiring 134 in the cross | intersection area | region 240 used as a comparative example. （ａ）は、アレイ基板１１における交差領域４０の上面図であり、（ｂ）は、交差領域４０の断面図である。(A) is a top view of the intersection region 40 in the array substrate 11, and (b) is a cross-sectional view of the intersection region 40. 交差領域４０におけるソース配線３４の電流の様子を模式的に示す断面図である。4 is a cross-sectional view schematically showing a state of a current of a source wiring 34 in an intersection region 40. FIG. （ａ）は、アレイ基板１１における交差領域４０の上面図であり、（ｂ）は、交差領域４０の断面図である。(A) is a top view of the intersection region 40 in the array substrate 11, and (b) is a cross-sectional view of the intersection region 40. 絶縁層３９上の半導体層４１を覆うソース配線３４の湾曲部３４ｃを示す断面図である。4 is a cross-sectional view showing a curved portion 34c of a source wiring 34 that covers a semiconductor layer 41 on an insulating layer 39. FIG. アレイ基板１１における交差領域４０の断面図である。3 is a cross-sectional view of an intersecting region 40 in the array substrate 11. FIG. 交差領域４０における半導体層４１を示す上面図である。4 is a top view showing a semiconductor layer 41 in an intersecting region 40. FIG. 交差領域４０における半導体層４１を示す上面図である。4 is a top view showing a semiconductor layer 41 in an intersecting region 40. FIG. 交差領域４０における半導体層４１を示す上面図である。4 is a top view showing a semiconductor layer 41 in an intersecting region 40. FIG. 交差領域４０における半導体層４１を示す上面図である。4 is a top view showing a semiconductor layer 41 in an intersecting region 40. FIG. （ａ）から（ｄ）は、アレイ基板１１の製造方法を説明するための工程断面図である。(A) to (d) are process cross-sectional views for explaining a method of manufacturing the array substrate 11. （ａ）から（ｄ）は、アレイ基板１１の製造方法を説明するための工程断面図である。(A) to (d) are process cross-sectional views for explaining a method of manufacturing the array substrate 11. （ａ）から（ｄ）は、アレイ基板１１の製造方法を説明するための工程断面図である。(A) to (d) are process cross-sectional views for explaining a method of manufacturing the array substrate 11. 従来の液晶パネル１０００の構成を示す斜視図である。It is a perspective view which shows the structure of the conventional liquid crystal panel 1000. FIG. 一つの画素領域を基準にしたアレイ基板１１０の概略的な平面図である。2 is a schematic plan view of an array substrate 110 based on one pixel region. FIG.
　以下、図面を参照しながら、本発明の実施形態を説明する。以下の図面においては、説明の簡潔化のために、実質的に同一の機能を有する構成要素を同一の参照符号で示す。なお、本発明は以下の実施形態に限定されない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.
　図１は、本発明の実施形態に係る液晶表示装置１００の構成を模式的に示す分解斜視図である。図１に示すように、本実施形態の液晶表示装置１００は、画像を表示可能な液晶表示装置である。液晶表示装置１００は、液晶パネル１０と、液晶パネル１０に光を照射するバックライトユニット２０とから構成されている。本実施形態の液晶パネル１０は、例えば、２０インチから１１０インチ（典型的には、３２インチから６０インチ）のサイズを有している。 FIG. 1 is an exploded perspective view schematically showing a configuration of a liquid crystal display device 100 according to an embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device 100 of the present embodiment is a liquid crystal display device capable of displaying an image. The liquid crystal display device 100 includes a liquid crystal panel 10 and a backlight unit 20 that irradiates the liquid crystal panel 10 with light. The liquid crystal panel 10 of the present embodiment has a size of, for example, 20 inches to 110 inches (typically 32 inches to 60 inches).
　本実施形態の液晶パネル１０は、概して、全体として矩形の形状を有しており、一対の透光性基板（ガラス基板）１１および１２から構成されている。両基板１１および１２は、互いに対向して配置され、その間には液晶層（不図示）が設けられている。液晶層は、基板１１および１２の間の電界印加に伴って光学特定が変化する液晶材料からなる。 The liquid crystal panel 10 of the present embodiment generally has a rectangular shape as a whole, and is composed of a pair of translucent substrates (glass substrates) 11 and 12. Both the substrates 11 and 12 are arranged to face each other, and a liquid crystal layer (not shown) is provided between them. The liquid crystal layer is made of a liquid crystal material whose optical characteristics change with application of an electric field between the substrates 11 and 12.
　なお、基板１１および１２の外縁部には、シール剤（不図示）が設けられて、液晶層を封止している。また、両基板１１および１２の外面には、それぞれ、偏光板１３、１３が貼り付けられている。本実施形態では、基板１１および１２のうち、裏側がアレイ基板（ＴＦＴ基板）１１であり、一方、表側がカラーフィルタ基板（ＣＦ基板）１２である。 A sealing agent (not shown) is provided on the outer edge portions of the substrates 11 and 12 to seal the liquid crystal layer. Further, polarizing plates 13 and 13 are attached to the outer surfaces of both the substrates 11 and 12, respectively. In this embodiment, the back side of the substrates 11 and 12 is the array substrate (TFT substrate) 11, while the front side is the color filter substrate (CF substrate) 12.
　本実施形態のアレイ基板１１は、行及び列を有するマトリックス状に画素が配置された液晶パネル用アレイ基板である。詳細は後述するが、本実施形態の構成では、行方向にゲート配線が延び、列方向にソース配線が延びている。また、各画素には、薄膜トランジスタ（ＴＦＴ）が配置されている。なお、行方向・列方向は、便宜上のものであるので、行方向が横方向、列方向が縦方向を意味する場合の他、その関係を逆にしても構わない。 The array substrate 11 of this embodiment is an array substrate for a liquid crystal panel in which pixels are arranged in a matrix having rows and columns. Although details will be described later, in the configuration of the present embodiment, the gate wiring extends in the row direction and the source wiring extends in the column direction. Each pixel is provided with a thin film transistor (TFT). Since the row direction and the column direction are for convenience, the relationship may be reversed in addition to the case where the row direction means the horizontal direction and the column direction means the vertical direction.
　本実施形態のバックライトユニット２０は、液晶パネル１０に光を照射する光源ユニットである。図１に示した例のバックライトユニット２０は、エッジライト型のバックライトユニットである。本実施形態のバックライトユニット２０は、複数の発光素子２３と、発光素子２３が発した光を液晶パネル１０に照射させる導光板２２とから構成されている。 The backlight unit 20 of the present embodiment is a light source unit that irradiates the liquid crystal panel 10 with light. The backlight unit 20 in the example shown in FIG. 1 is an edge light type backlight unit. The backlight unit 20 of the present embodiment includes a plurality of light emitting elements 23 and a light guide plate 22 that irradiates the liquid crystal panel 10 with light emitted from the light emitting elements 23.
　本実施形態の発光素子２３は、ＬＥＤ素子（点状光源）であり、図１に示した構成例では、複数のＬＥＤ素子２３が配線基板２５の上に載置されている。ＬＥＤ素子２３は、導光板２２の側面の一つ（入射面）２２ｂに対向して配置されており、ＬＥＤ素子２３から出射された光は、導光板２２の入射面２２ｂから導光板２２内に入射する。 The light emitting element 23 of the present embodiment is an LED element (point light source). In the configuration example shown in FIG. 1, a plurality of LED elements 23 are mounted on a wiring board 25. The LED element 23 is arranged to face one of the side surfaces (incident surface) 22b of the light guide plate 22, and light emitted from the LED element 23 enters the light guide plate 22 from the incident surface 22b of the light guide plate 22. Incident.
　導光板２２は、入射面２２ｂに入射した光を、発光面（主面）２２ａから面状に照射する光学部材である。導光板２２は、例えば、アクリル板から構成されている。本実施形態の導光板２２の底面２２ｃには、反射層となるドットパターン（不図示）が形成されている。このドットパターンは、反射パターン又は拡散パターンを形成するインクなどを用いて印刷によって形成されている。 The light guide plate 22 is an optical member that irradiates light incident on the incident surface 22b in a planar shape from the light emitting surface (main surface) 22a. The light guide plate 22 is made of, for example, an acrylic plate. A dot pattern (not shown) serving as a reflective layer is formed on the bottom surface 22c of the light guide plate 22 of the present embodiment. This dot pattern is formed by printing using ink or the like that forms a reflection pattern or a diffusion pattern.
　また、導光板２２と液晶パネル１０との間には、光学シート２１（２１ａから２１ｃ）が配置されている。この例では、光学シート２１ａから２１ｃは、それぞれ、例えば、レンズシート、プリズムシート、拡散板である。なお、光学シート２１の構成は、これらのものに限らず、他の構成を採用してもよい。 Further, an optical sheet 21 (21a to 21c) is disposed between the light guide plate 22 and the liquid crystal panel 10. In this example, the optical sheets 21a to 21c are, for example, a lens sheet, a prism sheet, and a diffusion plate, respectively. Note that the configuration of the optical sheet 21 is not limited to these, and other configurations may be adopted.
　さらに、本実施形態のバックライトユニット２０は、導光板２２を収納するバックライトシャーシ２８を備えている。また、本実施形態のバックライトシャーシ２８は、金属材料（例えば、アルミニウム、鉄など）から構成されており、液晶表示装置１００の裏面全体を覆う板金部材である。また、バックライトシャーシ２８と導光板２２との間には、反射シート２７が配置されている。 Furthermore, the backlight unit 20 of this embodiment includes a backlight chassis 28 that houses the light guide plate 22. Further, the backlight chassis 28 of the present embodiment is made of a metal material (for example, aluminum, iron, etc.), and is a sheet metal member that covers the entire back surface of the liquid crystal display device 100. Further, a reflective sheet 27 is disposed between the backlight chassis 28 and the light guide plate 22.
　本実施形態の液晶表示装置１００にはベゼル２９が設けられている。ベゼル２９は、金属材料（例えば、アルミニウム、鉄）からなり、液晶パネルの外縁部を押さえて固定するフレーム部材である。本実施形態の構成においては、液晶パネル１０、光学シート２１、導光板２２、ＬＥＤ素子２３が実装された配線基板（ＬＥＤ基板）２５、反射シート２７をバックライトシャーシ２８に収納した状態で、そのバックライトシャーシ２８にベゼル２９を取り付ける。 A bezel 29 is provided in the liquid crystal display device 100 of the present embodiment. The bezel 29 is made of a metal material (for example, aluminum or iron), and is a frame member that presses and fixes the outer edge portion of the liquid crystal panel. In the configuration of this embodiment, the liquid crystal panel 10, the optical sheet 21, the light guide plate 22, the wiring board (LED board) 25 on which the LED elements 23 are mounted, and the reflection sheet 27 are stored in the backlight chassis 28. A bezel 29 is attached to the backlight chassis 28.
　なお、図１に示した構成では、ＬＥＤ素子２３を用いたエッジライト型のバックライトユニット２０を示したがそれに限らない。例えば、本発明では、他の発光素子（例えば、冷陰極管（ＣＣＦＬ））を用いたエッジライト型のバックライトユニット２０を使用することもできる。あるいは、直下型のバックライトユニット２０を使用することも可能である。直下型のバックライトユニット２０の場合、発光素子は、ＬＥＤ素子、冷陰極管などを用いることができる。 In the configuration shown in FIG. 1, the edge light type backlight unit 20 using the LED element 23 is shown, but the configuration is not limited thereto. For example, in the present invention, an edge light type backlight unit 20 using another light emitting element (for example, a cold cathode fluorescent lamp (CCFL)) can be used. Alternatively, it is also possible to use a direct type backlight unit 20. In the case of the direct type backlight unit 20, an LED element, a cold cathode tube, or the like can be used as the light emitting element.
　次に、図２を参照しながら、本実施形態の構成について説明する。図２は、本実施形態のアレイ基板１１の上面構成を模式的に示す一部拡大図である。 Next, the configuration of the present embodiment will be described with reference to FIG. FIG. 2 is a partially enlarged view schematically showing the upper surface configuration of the array substrate 11 of the present embodiment.
　本実施形態のアレイ基板１１は、行及び列を有するマトリックス状に画素が配置されている。この例では、行方向（矢印５１）にゲート配線３３が延び、列方向（矢印５２方向）にソース配線３４が延びている。ゲート配線３３とソース配線３４との交差部には、スイッチング素子としてのＴＦＴ素子３０が形成されている。 The array substrate 11 of the present embodiment has pixels arranged in a matrix having rows and columns. In this example, the gate wiring 33 extends in the row direction (arrow 51), and the source wiring 34 extends in the column direction (arrow 52 direction). A TFT element 30 as a switching element is formed at the intersection of the gate wiring 33 and the source wiring 34.
　ＴＦＴ素子３０は、チャネル層となる半導体層３１と、ソース配線３４から延びたソース電極３２ｓと、ソース電極３２ｓに対向して配置されたドレイン電極３２ｄとから構成されている。半導体層３１は、例えばシリコン（アモルファスシリコン、多結晶シリコンなど）から構成されている。そして、ゲート配線３３のうちの半導体層３１の下方に位置する部位は、ゲート電極となる。ゲート電極と半導体層３１との間には、ゲート絶縁膜が形成されている。半導体層３１の表面には、ソース電極３２ｓとドレイン電極３２ｄとが配置されており、ソース電極３２ｓとドレイン電極３２ｄとの間がチャネル領域となる。 The TFT element 30 includes a semiconductor layer 31 serving as a channel layer, a source electrode 32 s extending from the source wiring 34, and a drain electrode 32 d disposed to face the source electrode 32 s. The semiconductor layer 31 is made of, for example, silicon (amorphous silicon, polycrystalline silicon, etc.). A portion of the gate wiring 33 located below the semiconductor layer 31 is a gate electrode. A gate insulating film is formed between the gate electrode and the semiconductor layer 31. A source electrode 32s and a drain electrode 32d are disposed on the surface of the semiconductor layer 31, and a channel region is formed between the source electrode 32s and the drain electrode 32d.
　ドレイン電極３２ｄからは、ドレイン配線３６が延びている。図２に示した例では、ドレイン配線３６の一部３６ｄは、接続部位３６ｅにて画素電極３７に接続されている。画素電極３７は、各画素を規定する電極であり、透明電極（例えば、ＩＴＯ）から構成されている。本実施形態の画素は、カラーフィルタ基板１２が三原色（Ｒ・Ｇ・Ｂ）の構成の場合、そのＲ（赤）・Ｇ（緑）・Ｂ（青）に対応する領域である。なお、Ｒ・Ｇ・Ｂの３つの領域をまとめて画素と称する場合、画素電極３７が位置する領域は、サブ画素領域、または、絵素領域と称しても構わない。また、カラーフィルタ基板１２が四原色（Ｒ・Ｇ・Ｂ・Ｙ）の構成の場合、本実施形態の画素は、そのＲ（赤）・Ｇ（緑）・Ｂ（青）・Ｙ（黄）に対応する領域になる。加えて、画素電極３７のパターンは、本実施形態の構成では例示として示しており、具体的なパターンについては適宜好適なものを採用すればよい。 A drain wiring 36 extends from the drain electrode 32d. In the example shown in FIG. 2, a part 36d of the drain wiring 36 is connected to the pixel electrode 37 at the connection portion 36e. The pixel electrode 37 is an electrode that defines each pixel, and is composed of a transparent electrode (for example, ITO). When the color filter substrate 12 has a configuration of three primary colors (R, G, and B), the pixel of this embodiment is an area corresponding to R (red), G (green), and B (blue). Note that when the three regions R, G, and B are collectively referred to as a pixel, the region where the pixel electrode 37 is located may be referred to as a sub-pixel region or a pixel region. Further, when the color filter substrate 12 has a configuration of four primary colors (R, G, B, and Y), the pixels of the present embodiment have R (red), G (green), B (blue), and Y (yellow). It becomes the area corresponding to. In addition, the pattern of the pixel electrode 37 is shown as an example in the configuration of the present embodiment, and a suitable specific pattern may be adopted as appropriate.
　また、本実施形態の構成では、アレイ基板１１に補助容量（Ｃｓ）が形成されるように構成されている。アレイ基板１１に補助容量配線（Ｃｓ配線）３５が形成されている。ここで、補助容量（Ｃｓ）は、Ｃｓ配線３５の一部に位置するＣｓ電極、絶縁膜（不図示）、画素電極３７によって形成されている。補助容量（Ｃｓ）を構成する絶縁膜（誘電体層）は、Ｃｓ電極と画素電極３７との間に位置しており、そして、補助容量（Ｃｓ）は、Ｃｓ配線３５と画素電極３７との交差部において形成されている。また、補助容量（Ｃｓ）は、ゲート信号がＯＦＦの期間において液晶層に電荷を供給し、画素の輝度を保持するという役割を有するものである。本実施形態の構成では、ドレイン配線３６の端部３６ｇは、補助容量配線（Ｃｓ配線）３５に接続されている。具体的には、ドレイン配線３６は、引き出し部３６ｄ、３６ｆを介して、Ｃｓ配線３５に接続されている。 Further, in the configuration of the present embodiment, the auxiliary capacitance (Cs) is formed on the array substrate 11. An auxiliary capacitance wiring (Cs wiring) 35 is formed on the array substrate 11. Here, the auxiliary capacitance (Cs) is formed by a Cs electrode, an insulating film (not shown), and a pixel electrode 37 that are located in a part of the Cs wiring 35. The insulating film (dielectric layer) constituting the auxiliary capacitor (Cs) is located between the Cs electrode and the pixel electrode 37, and the auxiliary capacitor (Cs) is formed between the Cs wiring 35 and the pixel electrode 37. It is formed at the intersection. Further, the auxiliary capacitor (Cs) has a role of supplying charges to the liquid crystal layer and maintaining the luminance of the pixel in a period in which the gate signal is OFF. In the configuration of the present embodiment, the end portion 36 g of the drain wiring 36 is connected to the auxiliary capacitance wiring (Cs wiring) 35. Specifically, the drain wiring 36 is connected to the Cs wiring 35 through lead portions 36d and 36f.
　さらに、本実施形態の構成では、Ｃｓ配線３５は、ゲート配線３３と同様に、行方向（矢印５１）に延びている。ソース配線３４は、Ｃｓ配線３５よりも上層に位置しており、そして、アレイ基板１１には、ソース配線３４とＣｓ配線３５とが互いに交差する交差領域４０が存在している。 Furthermore, in the configuration of the present embodiment, the Cs wiring 35 extends in the row direction (arrow 51), similarly to the gate wiring 33. The source wiring 34 is located above the Cs wiring 35, and the array substrate 11 has an intersection region 40 where the source wiring 34 and the Cs wiring 35 intersect each other.
　図３（ａ）および（ｂ）は、それぞれ、交差領域４０におけるソース配線３４およびＣｓ配線３５の構成を模式的に示す上面図および断面図である。本実施形態の構成において、Ｃｓ配線３５は、基板３８（アレイ基板１１を構成するガラス基板）の上に形成されている。基板３８がガラス基板から構成されている場合、ガラス基板の表面に他の層（絶縁層など）が形成されていても構わない。 3A and 3B are a top view and a cross-sectional view schematically showing the configuration of the source wiring 34 and the Cs wiring 35 in the intersection region 40, respectively. In the configuration of this embodiment, the Cs wiring 35 is formed on a substrate 38 (a glass substrate constituting the array substrate 11). When the substrate 38 is made of a glass substrate, another layer (insulating layer or the like) may be formed on the surface of the glass substrate.
　基板３８の上には、Ｃｓ配線３５を覆うように絶縁層３９が形成されている。絶縁層３９は、Ｃｓ配線３５とソース配線３４との間の層間絶縁膜の機能を有している。Ｃｓ配線３５を乗り越えるように絶縁層３９が形成されていることから、Ｃｓ配線３５の両サイドには、段差４５が形成されている。 An insulating layer 39 is formed on the substrate 38 so as to cover the Cs wiring 35. The insulating layer 39 has a function of an interlayer insulating film between the Cs wiring 35 and the source wiring 34. Since the insulating layer 39 is formed so as to get over the Cs wiring 35, a step 45 is formed on both sides of the Cs wiring 35.
　本実施形態の構成では、Ｃｓ配線３５とソース配線３４との交差領域４０において、絶縁層３９の上に、半導体層４１が形成されている。そして、ソース配線３４は、半導体層４１を覆うように絶縁層３９の上に形成されている。ここで、本実施形態の半導体層４１は、交差領域４０におけるソース配線３４の段差４５の勾配を緩和する段差緩和パターンとしての機能を有している。また、本実施形態の半導体層４１は、Ｃｓ配線３５の厚さよりも薄い構造を有している。 In the configuration of the present embodiment, the semiconductor layer 41 is formed on the insulating layer 39 in the intersecting region 40 between the Cs wiring 35 and the source wiring 34. The source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41. Here, the semiconductor layer 41 of the present embodiment has a function as a step relief pattern that relaxes the gradient of the step 45 of the source wiring 34 in the intersecting region 40. Further, the semiconductor layer 41 of the present embodiment has a structure that is thinner than the thickness of the Cs wiring 35.
　また、本実施形態の半導体層４１は、Ｃｓ配線３５と平行な方向である行方向５１に沿って延びている。本実施形態の構成では、半導体層４１は、Ｃｓ配線３５の第１辺（３５ｆ）に沿って延びる第１半導体層４１ｆと、Ｃｓ配線３５の第２辺（３５ｓ）に沿って延びる第２半導体層４１ｓとを含んでいる。Ｃｓ配線３５の両サイドに半導体層４１（４１ｆ、４１ｓ）を形成することによって、両サイドの段差４５の勾配を緩和することができる。 Further, the semiconductor layer 41 of the present embodiment extends along the row direction 51 which is a direction parallel to the Cs wiring 35. In the configuration of the present embodiment, the semiconductor layer 41 includes the first semiconductor layer 41f extending along the first side (35f) of the Cs wiring 35 and the second semiconductor extending along the second side (35s) of the Cs wiring 35. Layer 41s. By forming the semiconductor layer 41 (41f, 41s) on both sides of the Cs wiring 35, the gradient of the step 45 on both sides can be relaxed.
　さらに、本実施形態の構成において、図２に示したゲート配線３３は、Ｃｓ配線３５と同一レベルの層に形成されている。したがって、ソース配線３４は、ゲート配線３３よりも上層に位置している。また、本実施形態のアレイ基板１１には、ソース配線３４とゲート配線３３とが互いに交差する交差領域４７が存在している。図示した例では、ソース配線３４は、列方向５２に延びる本体部３４ａを有しており、ソース配線３４の本体部３４ａは、交差領域４０および４７においても本体部３４ａと同様に列方向に延びている。 Furthermore, in the configuration of the present embodiment, the gate wiring 33 shown in FIG. 2 is formed in the same level layer as the Cs wiring 35. Therefore, the source wiring 34 is located in an upper layer than the gate wiring 33. In the array substrate 11 of this embodiment, there is an intersection region 47 where the source wiring 34 and the gate wiring 33 intersect each other. In the illustrated example, the source wiring 34 has a main body 34 a extending in the column direction 52, and the main body 34 a of the source wiring 34 extends in the column direction in the intersecting regions 40 and 47 as well as the main body 34 a. ing.
　なお、本実施形態の構成では、ソース配線３４は、銅から構成されている。また、Ｃｓ配線３５およびゲート配線３３も、銅から構成されている。また、ソース配線３４、Ｃｓ配線３５、ゲート配線３３は、銅配線に限らず、他の金属材料（アルミニウム）から構成されていてもよいし、多層膜（例えば、Ｃｕ・Ｍｏ、Ｃｕ・Ｔｉ）の構成であってもよい。さらに、ソース配線３４（例えば、銅配線）と、Ｃｓ配線３５・ゲート配線３３とを異なる材料から構成しても構わない。 In the configuration of the present embodiment, the source wiring 34 is made of copper. The Cs wiring 35 and the gate wiring 33 are also made of copper. Further, the source wiring 34, the Cs wiring 35, and the gate wiring 33 are not limited to the copper wiring, and may be composed of other metal materials (aluminum) or a multilayer film (for example, Cu · Mo, Cu · Ti). It may be configured as follows. Further, the source wiring 34 (for example, copper wiring) and the Cs wiring 35 / gate wiring 33 may be made of different materials.
　本実施形態の構成によれば、行方向５１に延びるＣｓ配線３５と、列方向５２に延びるソース配線３４との交差領域４０において、絶縁層３９の上に半導体層４１が形成されている。そして、ソース配線３４は、半導体層４１を覆うように絶縁層３９の上に形成されている。したがって、交差領域４０においてソース配線３４が乗り越える段差４５は、半導体層４１によって勾配を緩和することができる。その結果、ソース配線３４の断線を抑制できる液晶パネル用アレイ基板１１を実現することができる。 According to the configuration of the present embodiment, the semiconductor layer 41 is formed on the insulating layer 39 in the intersection region 40 between the Cs wiring 35 extending in the row direction 51 and the source wiring 34 extending in the column direction 52. The source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41. Therefore, the step 45 over which the source wiring 34 crosses the intersection region 40 can be moderated by the semiconductor layer 41. As a result, the liquid crystal panel array substrate 11 capable of suppressing the disconnection of the source wiring 34 can be realized.
　さらに、図４から図６を参照しながら、ソース配線の断線の原因について説明する。図４は、比較例のアレイ基板２１０の上面構成を模式的に示す一部拡大図である。 Further, the cause of the disconnection of the source wiring will be described with reference to FIGS. FIG. 4 is a partially enlarged view schematically showing the upper surface configuration of the array substrate 210 of the comparative example.
　図４に示した比較例のアレイ基板２１０では、行方向５１に延びるゲート配線２３３およびＣｓ配線２３５と、列方向５２に延びるソース配線２３４とが形成されている。また、ＴＦＴ素子２３０は、半導体層２３１と、ソース電極２３２ｓ、ドレイン電極２３２ｄから構成されている。ドレイン電極２３２ｄから延びたドレイン配線２３６ｄは、接続部位２３６ｅにて画素電極２３７に接続されている。なお、図示していないが、ドレイン配線２３６ｄの端部は、Ｃｓ配線２３５に接続されている。 4, the gate wiring 233 and Cs wiring 235 extending in the row direction 51 and the source wiring 234 extending in the column direction 52 are formed in the array substrate 210 of the comparative example shown in FIG. The TFT element 230 includes a semiconductor layer 231, a source electrode 232 s, and a drain electrode 232 d. A drain wiring 236d extending from the drain electrode 232d is connected to the pixel electrode 237 at a connection portion 236e. Although not shown, the end of the drain wiring 236d is connected to the Cs wiring 235.
　この比較例では、ソース配線２３４とＣｓ配線２３５との交差領域２４０において、本実施形態における段差緩和用の半導体層４１は形成されていない。図５（ａ）は、交差領域２４０の拡大図であり、そして、図５（ｂ）は、交差領域２４０の断面図である。 In this comparative example, in the intersecting region 240 between the source wiring 234 and the Cs wiring 235, the semiconductor layer 41 for level difference mitigation in this embodiment is not formed. 5A is an enlarged view of the intersection region 240, and FIG. 5B is a cross-sectional view of the intersection region 240. As shown in FIG.
　図５（ｂ）に示すように、ガラス基板２３８の上にＣｓ配線２３５が延びている。そして、Ｃｓ配線２３５を覆うように絶縁層２３９がガラス基板２３８の上に形成されている。そして、絶縁層２３９の上に、ソース配線２３４が形成されている。図示するように、ソース配線２３４は、交差領域２４０において、Ｃｓ配線２３５によって形成された段差２４５を乗り越えるようにして延びる。 As shown in FIG. 5B, the Cs wiring 235 extends on the glass substrate 238. An insulating layer 239 is formed on the glass substrate 238 so as to cover the Cs wiring 235. A source wiring 234 is formed on the insulating layer 239. As shown in the drawing, the source wiring 234 extends so as to get over the step 245 formed by the Cs wiring 235 in the intersection region 240.
　ソース配線２３４は、金属膜をエッチングでパターニングすることによって形成される。それゆえに、図６（ａ）および（ｂ）に示すように、エッチングの残渣などによる侵食の影響で、Ｃｓ配線２３５による段差部２４５をソース配線２３４が乗り越える部位にて断線（２４６）が生じる可能性が高まる。さらには、ソース配線２３４が銅配線の場合、銅配線の酸化腐食によって、段差部２４５にて断線（２４６）が発生することもある。 The source wiring 234 is formed by patterning a metal film by etching. Therefore, as shown in FIGS. 6A and 6B, disconnection (246) may occur at the portion where the source wiring 234 gets over the stepped portion 245 by the Cs wiring 235 due to the influence of erosion due to etching residue or the like. Increases nature. Furthermore, when the source wiring 234 is a copper wiring, disconnection (246) may occur in the stepped portion 245 due to oxidative corrosion of the copper wiring.
　一方、本実施形態の構成によれば、図７に示すように、交差領域４０における段差４５の勾配を緩和する半導体層４１が形成されているので、ソース配線３４の断線を抑制することができる。また、段差４５の勾配を緩和する半導体層４１の存在によって、交差領域４０におけるソース配線３４の電流５０の流れをスムーズにすることができる。特に、本実施形態の構成では、半導体層４１の厚さは、Ｃｓ配線３５の厚さよりも小さくしているので、段差４５の変化を滑らかにすることが容易となる。 On the other hand, according to the configuration of the present embodiment, as shown in FIG. 7, the semiconductor layer 41 that relaxes the gradient of the step 45 in the intersecting region 40 is formed, so that disconnection of the source wiring 34 can be suppressed. . In addition, the presence of the semiconductor layer 41 that reduces the gradient of the step 45 can smooth the flow of the current 50 of the source wiring 34 in the intersecting region 40. In particular, in the configuration of the present embodiment, since the thickness of the semiconductor layer 41 is smaller than the thickness of the Cs wiring 35, it is easy to smooth the change in the step 45.
　図８は、図４及び図５に示した交差領域２４０において、ガラス基板３８の上にバッファ配線１４１を形成した構造を示している。図８に示した構造においては、バッファ配線１４１の存在によって、ソース配線１３４が乗り越える段差（２４５ａ、２４５ｂ）の勾配（スロープ）を比較的滑らかにすることができる。しかしながら、ソース配線１３４の電流１５０の流れは、段差２４５ａに対応する箇所（１５０ａ）において段差２４５ａの影響でスムーズに流れない場合が発生し得る。 FIG. 8 shows a structure in which the buffer wiring 141 is formed on the glass substrate 38 in the intersecting region 240 shown in FIGS. In the structure shown in FIG. 8, the presence of the buffer wiring 141 makes it possible to make the slope (slope) of the step (245a, 245b) over which the source wiring 134 gets over relatively smooth. However, the flow of the current 150 of the source wiring 134 may not flow smoothly due to the influence of the step 245a at the location (150a) corresponding to the step 245a.
　さらに説明すると、図８に示した構造では、Ｃｓ配線２３５とバッファ配線１４１とは同じ厚さで形成されることから、図７に示した本実施形態の構造と比較して、段差２４５ａを滑らかにすることが困難である。換言すると、本実施形態の構造では、半導体層４１の厚さをＣｓ配線３５の厚さよりも薄くしているので、図８に示した構造と比較して段差（４５）の勾配を滑らかに変化させることが容易となる。 More specifically, since the Cs wiring 235 and the buffer wiring 141 are formed with the same thickness in the structure shown in FIG. 8, the step 245a is smoother than the structure of the present embodiment shown in FIG. It is difficult to make. In other words, in the structure of the present embodiment, the thickness of the semiconductor layer 41 is made thinner than the thickness of the Cs wiring 35, so that the gradient of the step (45) can be smoothly changed compared to the structure shown in FIG. It becomes easy to make.
　さらには、段差２４５ａにおける構造によっては、Ｃｓ配線２３５の両サイドにバッファ配線１４１を形成することが困難である場合もあり得る。本実施形態の構成では、絶縁層３９の上に半導体層４１を形成できることから、図８に示した構造のような問題、すなわちバッファ配線１４１の形成が困難である場合が発生する問題を回避することが容易である。 Furthermore, depending on the structure of the step 245a, it may be difficult to form the buffer wiring 141 on both sides of the Cs wiring 235. In the configuration of this embodiment, since the semiconductor layer 41 can be formed on the insulating layer 39, the problem as in the structure shown in FIG. 8, that is, the problem that the buffer wiring 141 is difficult to form can be avoided. Is easy.
　なお、図２に示したアレイ基板１１では、ソース配線３４とＣｓ配線３５との交差領域４０のそれぞれに、半導体層４１を形成しているが、全ての交差領域４０でなくても指定の交差領域４０を選択して半導体層４１を形成することも可能である。加えて、ＴＦＴ素子３０の構造との関係にもよるが、ゲート配線３３との交差領域４７においても、Ｃｓ配線３５の交差領域４０と同様に、段差の勾配緩和のための半導体層４１を形成しても構わない。具体的には、交差領域４７において、絶縁層３９の上においてゲート配線３３の両サイドに半導体層４１を形成する。このようにすれば、ゲート配線３３を乗り越えるソース配線３４の断線も抑制することが容易となる。 In the array substrate 11 shown in FIG. 2, the semiconductor layer 41 is formed in each of the intersecting regions 40 of the source wiring 34 and the Cs wiring 35. It is also possible to select the region 40 and form the semiconductor layer 41. In addition, although depending on the relationship with the structure of the TFT element 30, the semiconductor layer 41 is formed in the intersection region 47 with the gate wiring 33 in order to reduce the step gradient as in the intersection region 40 with the Cs wiring 35. It doesn't matter. Specifically, the semiconductor layer 41 is formed on both sides of the gate wiring 33 on the insulating layer 39 in the intersection region 47. In this way, it becomes easy to suppress disconnection of the source wiring 34 over the gate wiring 33.
　なお、本実施形態の構成において、配線の幅などの条件を例示的に示すと次の通りである。ソース配線３４の幅は、例えば５～８μｍである。ゲート配線３３の幅は、例えば１０～２０μｍである。Ｃｓ配線３５の幅は、例えば１０～２０μｍである。ソース配線３４の厚さは、例えば３０００～４５００Åであり、ゲート配線３３およびＣｓ配線３５の厚さは、例えば３０００～６０００Å（典型的には６０００Å）である。また、半導体層４１の幅は、例えば１０～５０μｍであり、半導体層４１の厚さは例えば１８００～２５００Å（典型的には２３００Å）である。加えて、絶縁層３９の厚さは、例えば２５００～４１００Åである。 In the configuration of this embodiment, conditions such as the width of the wiring are exemplarily shown as follows. The width of the source wiring 34 is, for example, 5 to 8 μm. The width of the gate wiring 33 is, for example, 10 to 20 μm. The width of the Cs wiring 35 is, for example, 10 to 20 μm. The thickness of the source wiring 34 is, for example, 3000 to 4500 mm, and the thickness of the gate wiring 33 and the Cs wiring 35 is, for example, 3000 to 6000 mm (typically 6000 mm). The width of the semiconductor layer 41 is, for example, 10 to 50 μm, and the thickness of the semiconductor layer 41 is, for example, 1800 to 2500 mm (typically 2300 mm). In addition, the thickness of the insulating layer 39 is, for example, 2500 to 4100 mm.
　本実施形態の構成においては、半導体層４１の厚さ（典型的には２３００Å）は、Ｃｓ配線３５の厚さ（典型的には６０００Å）よりも小さくしている。また、図３に示した構成においては、半導体層４１の厚さは、絶縁層３９の厚さよりも小さくしている。 In the configuration of the present embodiment, the thickness of the semiconductor layer 41 (typically 2300 mm) is smaller than the thickness of the Cs wiring 35 (typically 6000 mm). In the configuration shown in FIG. 3, the thickness of the semiconductor layer 41 is smaller than the thickness of the insulating layer 39.
　次に、図９および図１０を参照しながら、本実施形態のアレイ基板１１の改変例について説明する。図９（ａ）および（ｂ）は、それぞれ、本実施形態の改変例のアレイ基板１１における交差領域４０の上面図および断面図である。 Next, a modified example of the array substrate 11 of this embodiment will be described with reference to FIGS. 9 and 10. FIGS. 9A and 9B are a top view and a cross-sectional view, respectively, of the intersecting region 40 in the array substrate 11 of the modified example of the present embodiment.
　図９に示した構成においては、半導体層４１は、少なくとも２段の段差構造（４１ａ、４１ｂ）を有している。図示した例では、半導体層４１は、Ｃｓ配線３５の側に近い第１段差部４１ａと、第１段差部４１ａに連続した第２段差部４１ｂとから構成されている。第２段差部４１ｂの厚さは、第１段差部４１ａの厚さよりも小さい。この例における第１段差部４１ａの厚さは例えば２３００Åであり、そして、第２段差部４１ｂの厚さは例えば１０００Åである。 In the configuration shown in FIG. 9, the semiconductor layer 41 has at least a two-step structure (41a, 41b). In the illustrated example, the semiconductor layer 41 includes a first stepped portion 41a close to the Cs wiring 35 side and a second stepped portion 41b continuous to the first stepped portion 41a. The thickness of the second step portion 41b is smaller than the thickness of the first step portion 41a. In this example, the thickness of the first step portion 41a is 2300 mm, for example, and the thickness of the second step portion 41b is 1000 mm, for example.
　このように半導体層４１を段差構造（４１ａ、４１ｂ）にすると、図１０に示すように、段差４５の勾配をより滑らかに緩和することができる。その結果、ソース配線３４の断線をより抑制することができる。そして、段差構造（４１ａ、４１ｂ）を有する半導体層４１によって、交差領域４０におけるソース配線３４の電流５０の流れをよりスムーズにすることができる。なお、２段の段差構造（４１ａ、４１ｂ）に限らず、３段以上の段差構造にしても構わない。 Thus, when the semiconductor layer 41 has the step structure (41a, 41b), the gradient of the step 45 can be more smoothly relaxed as shown in FIG. As a result, disconnection of the source wiring 34 can be further suppressed. The flow of the current 50 of the source wiring 34 in the intersecting region 40 can be made smoother by the semiconductor layer 41 having the step structure (41a, 41b). The step structure is not limited to the two-step structure (41a, 41b), and may be a three-step or more step structure.
　さらには、本実施形態のアレイ基板１１は、次のように改変することも可能である。図１１（ａ）および（ｂ）は、それぞれ、本実施形態の改変例のアレイ基板１１における交差領域４０の上面図および断面図である。 Furthermore, the array substrate 11 of the present embodiment can be modified as follows. FIGS. 11A and 11B are a top view and a cross-sectional view, respectively, of the intersecting region 40 in the array substrate 11 according to the modified example of the present embodiment.
　図１１（ａ）及び（ｂ）に示した構造では、半導体層４１をＣｓ配線３５から少し離間して形成している。半導体層４１は、Ｃｓ配線３５を乗り越えて隆起した絶縁層３９に接するように形成する他、図１１に示した構造のように、隆起した絶縁層３９から離れた位置に形成することができる。このように離間して半導体層４１を形成しても、段差４５の勾配を緩和することができる。 In the structure shown in FIGS. 11A and 11B, the semiconductor layer 41 is formed slightly apart from the Cs wiring 35. The semiconductor layer 41 can be formed so as to be in contact with the raised insulating layer 39 over the Cs wiring 35 and at a position away from the raised insulating layer 39 as in the structure shown in FIG. Even if the semiconductor layer 41 is formed so as to be separated in this way, the gradient of the step 45 can be relaxed.
　次に、図１２および図１３を参照しながら、本実施形態の改変例について説明する。図１２は、本実施形態の半導体層４１を覆うようにソース配線３４を形成した構造を示している。 Next, a modified example of this embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 shows a structure in which the source wiring 34 is formed so as to cover the semiconductor layer 41 of the present embodiment.
　このソース配線３４では、半導体層４１を乗り越える部位において湾曲部３４ｃが形成されている。この湾曲部３４ｃを利用して、段差４５の勾配を緩和することができる。具体的には、Ｃｓ配線３５の厚さよりも薄い半導体層４１が形成されており、そして、Ｃｓ配線３５の幅よりも幅が細い半導体層４１の上に、ソース配線３４が堆積されると、ソース配線３４の上に位置するソース配線３４の部位３４ｃは、滑らかな曲面となる。そして、その滑らかな曲面を有する湾曲部３４ｃにより、ソース配線３４の断線を抑制することができる。 In the source wiring 34, a curved portion 34c is formed at a portion over the semiconductor layer 41. By using the curved portion 34c, the gradient of the step 45 can be relaxed. Specifically, the semiconductor layer 41 thinner than the thickness of the Cs wiring 35 is formed, and when the source wiring 34 is deposited on the semiconductor layer 41 narrower than the width of the Cs wiring 35, A portion 34c of the source wiring 34 located on the source wiring 34 has a smooth curved surface. The disconnection of the source wiring 34 can be suppressed by the curved portion 34c having a smooth curved surface.
　図１３は、ソース配線３４の湾曲部３４ｃを利用して、段差４５の勾配を緩和した構造を示している。ソース配線３４は、半導体層４１を乗り越えるように形成されており、その乗り越え部位が湾曲部３４ｃとなって、段差４５の勾配を緩和した構造となっている。 FIG. 13 shows a structure in which the slope of the step 45 is relaxed by using the curved portion 34 c of the source wiring 34. The source wiring 34 is formed so as to get over the semiconductor layer 41, and the part that goes over becomes a curved portion 34 c so that the gradient of the step 45 is relaxed.
　なお、半導体層４１の上面形状は、矩形に限らず、種々の形状を採用することができる。図１４から図１６は、それぞれ、半導体層４１の形状を模式的に示す上面図である。 Note that the shape of the upper surface of the semiconductor layer 41 is not limited to a rectangle, and various shapes can be employed. 14 to 16 are top views schematically showing the shape of the semiconductor layer 41, respectively.
　図１４に示した構造では、半導体層４１の一部に凹部４２ａが形成されている。具体的には、ソース配線３４の下方に位置する部位に凹部（又は切り欠き部）４２ａが形成されている。また、図１４に示した構造では、ソース配線３４で覆われていない部分は、ソース配線３４の辺３４ｅに対して斜めに延びる辺４２ｂを有している。半導体層４１に凹部４２ａを形成することによって、半導体層４１とソース配線３４との間に薬液が侵入したとしても、侵食されることを効果的に抑制することができる。 In the structure shown in FIG. 14, a recess 42 a is formed in a part of the semiconductor layer 41. Specifically, a recess (or notch) 42 a is formed in a portion located below the source wiring 34. In the structure shown in FIG. 14, the portion not covered with the source wiring 34 has a side 42 b extending obliquely with respect to the side 34 e of the source wiring 34. By forming the recess 42 a in the semiconductor layer 41, even if a chemical solution enters between the semiconductor layer 41 and the source wiring 34, it is possible to effectively suppress erosion.
  図１５に示した構造では、半導体層４１の一部に波形の形状部位４３ａが形成されている。具体的には、ソース配線３４の下方に位置する部位に波形の辺を有する部位４３ａが形成されている。また、図１５に示した構造では、ソース配線３４で覆われていない部分は、ソース配線３４の辺３４ｅに対して斜めに延びる辺４３ｂを有している。半導体層４１に波形部位４３ａを形成することによって、半導体層４１とソース配線３４との間に薬液が侵入したとしても、侵食されることを効果的に抑制することができる。加えて、この構造によれば、半導体層４１とソース配線３４との位置ズレが生じた場合でも、波形部位４３ａには複数の凸凹が存在することから、半導体層４１とソース配線３４との間に薬液が侵入したとしても、侵食されることを効果的に抑制することができる。 In the structure shown in FIG. 15, a wavy shape portion 43 a is formed in a part of the semiconductor layer 41. Specifically, a portion 43 a having a waveform side is formed at a portion located below the source wiring 34. In the structure shown in FIG. 15, the portion not covered with the source wiring 34 has a side 43 b extending obliquely with respect to the side 34 e of the source wiring 34. By forming the corrugated portion 43 a in the semiconductor layer 41, even if the chemical solution enters between the semiconductor layer 41 and the source wiring 34, it is possible to effectively suppress erosion. In addition, according to this structure, even when a positional deviation between the semiconductor layer 41 and the source wiring 34 occurs, there are a plurality of irregularities in the waveform portion 43 a, so that there is a gap between the semiconductor layer 41 and the source wiring 34. Even if the chemical solution enters, the erosion can be effectively suppressed.
　なお、半導体層４１のうちのソース配線３４の下方に位置する部位の形状は、図１４に示した凹部４２ａ、図１５に示した波形形状４３ａに限らず、他の形状（例えば、凸型、三角形状、円弧状、凹凸型など）にすることも可能である。 Note that the shape of the portion of the semiconductor layer 41 located below the source wiring 34 is not limited to the concave portion 42a shown in FIG. 14 and the corrugated shape 43a shown in FIG. 15, but other shapes (for example, convex, It is also possible to use a triangular shape, an arc shape, an uneven shape, or the like.
　また、図１６に示した構造では、半導体層４１は台形形状（４４ａ、４４ｂ）を有している。具体的には、半導体層４１は、Ｃｓ配線３５と平行に延びる辺４４ａと、ソース配線３４の辺３４ｅに対して斜めに延びる辺４４ｂとから構成されている。図示した例では、半導体層４１の辺４４ａの一部は、ソース配線３４の下方に位置しており、それ以外の部分は、ソース配線３４の外に延びている。半導体層４１を台形形状（４４ａ、４４ｂ）にすることによって、ソース配線３４が半導体層の中央を外れて形成されたとしても、エッチング液が侵入し易くなる領域を発生し難くすることができるという効果を得ることができる。 In the structure shown in FIG. 16, the semiconductor layer 41 has a trapezoidal shape (44a, 44b). Specifically, the semiconductor layer 41 includes a side 44 a extending in parallel with the Cs wiring 35 and a side 44 b extending obliquely with respect to the side 34 e of the source wiring 34. In the illustrated example, a part of the side 44 a of the semiconductor layer 41 is located below the source line 34, and the other part extends outside the source line 34. By forming the semiconductor layer 41 into a trapezoidal shape (44a, 44b), even if the source wiring 34 is formed off the center of the semiconductor layer, it is possible to make it difficult to generate a region where the etching solution easily enters. An effect can be obtained.
　また、図１７に示すような台形形状（４４ａ、４４ｂ）に半導体層４１を構成することも可能である。具体的には、台形形状（４４ａ、４４ｂ）を有する半導体層４１は、ソース配線３４の下方に覆われるように形成されている。ソース配線３４の下方に覆われるような台形形状（４４ａ、４４ｂ）にすることによって、ソース配線３４が半導体層の中央を外れて形成されたとしても、エッチング液が侵入し易くなる領域を発生し難くすることができる。 It is also possible to configure the semiconductor layer 41 in a trapezoidal shape (44a, 44b) as shown in FIG. Specifically, the semiconductor layer 41 having a trapezoidal shape (44a, 44b) is formed so as to be covered under the source wiring 34. By forming the trapezoidal shape (44a, 44b) so as to be covered under the source wiring 34, even if the source wiring 34 is formed off the center of the semiconductor layer, a region where the etching solution easily enters is generated. Can be difficult.
　次に、図１８（ａ）から（ｄ）を参照しながら、本実施形態における交差領域４０における半導体層４１およびソース配線３４の製造方法について説明する。図１８（ａ）から（ｄ）は、本実施形態の製造方法を説明するための工程断面図である。 Next, a method for manufacturing the semiconductor layer 41 and the source wiring 34 in the intersecting region 40 according to this embodiment will be described with reference to FIGS. 18A to 18D are process cross-sectional views for explaining the manufacturing method of the present embodiment.
　まず、図１８（ａ）に示すように、ガラス基板３８の上にＣｓ配線３５を形成した後、Ｃｓ配線３５を覆うように絶縁層３９を形成し、次いで、その絶縁層３９の上に、半導体層４１の材料となる半導体材料４１ｃを堆積する。 First, as shown in FIG. 18A, after forming the Cs wiring 35 on the glass substrate 38, an insulating layer 39 is formed so as to cover the Cs wiring 35, and then on the insulating layer 39, A semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited.
　Ｃｓ配線３５は、ガラス基板３８の上に金属膜（例えば、Ｃｕ膜）を堆積した後、レジストパターン（不図示）をマスクとしてウエットエッチングすることによって形成される。なお、このウエットエッチングで、ゲート配線３３も形成される。ここで、エッチング液（エッチャント）は、例えば、フッ化化合物を含む溶液である。本実施形態の絶縁層３９は、例えば、チッ化シリコンから構成されており、その厚さは、例えば３０００～４５００Åである。 The Cs wiring 35 is formed by depositing a metal film (for example, Cu film) on the glass substrate 38 and then performing wet etching using a resist pattern (not shown) as a mask. The gate wiring 33 is also formed by this wet etching. Here, the etching solution (etchant) is, for example, a solution containing a fluorinated compound. The insulating layer 39 of the present embodiment is made of, for example, silicon nitride and has a thickness of, for example, 3000 to 4500 mm.
　この構成では、半導体材料４１ｃは、例えば、シリコンからなる。具体的には、半導体材料４１ｃは、ＴＦＴ素子３０を構成する半導体層３１（図２参照）と同じ材料を用いることができる。さらに説明すると、ＴＦＴ素子３０を構成する半導体層３１を形成する工程において、交差領域４０にて半導体材料４１ｃを堆積することが好ましい。 In this configuration, the semiconductor material 41c is made of, for example, silicon. Specifically, the same material as the semiconductor layer 31 (see FIG. 2) constituting the TFT element 30 can be used as the semiconductor material 41c. More specifically, in the step of forming the semiconductor layer 31 constituting the TFT element 30, it is preferable to deposit the semiconductor material 41 c in the intersecting region 40.
　次に、図１８（ｂ）に示すように、半導体材料４１ｃの上に、半導体層４１のパターンを規定するレジストパターン４１ｍを形成する。レジストパターン４１ｍは、フォトリソグラフィによって形成された樹脂製のパターンである。 Next, as shown in FIG. 18B, a resist pattern 41m that defines the pattern of the semiconductor layer 41 is formed on the semiconductor material 41c. The resist pattern 41m is a resin pattern formed by photolithography.
　次に、図１８（ｃ）に示すように、レジストパターン４１ｍをマスクとして、半導体材料４１ｃをエッチングすることによって、半導体材料４１ｃから半導体層４１を得る。なお、この例では、ドライエッチングによって半導体材料４１ｃをパターニングして、半導体層４１を形成する。図示した例では、レジストパターン４１ｍと絶縁層３９とに挟まれている部分の半導体材料４１ｃは、他の部分よりもエッチングがされにくいので、半導体層４１には少しの段差４１ｄが生じることが多い。なお、ドライエッチングの後は、レジストパターン４１ｍは取り除かれる。 Next, as shown in FIG. 18C, the semiconductor layer 41 is obtained from the semiconductor material 41c by etching the semiconductor material 41c using the resist pattern 41m as a mask. In this example, the semiconductor layer 41 is formed by patterning the semiconductor material 41c by dry etching. In the illustrated example, the portion of the semiconductor material 41c sandwiched between the resist pattern 41m and the insulating layer 39 is less likely to be etched than the other portions, so that the semiconductor layer 41 often has a slight step 41d. . Note that the resist pattern 41m is removed after the dry etching.
　その後、図１８（ｄ）に示すように、半導体層４１を覆うように絶縁層３９の上にソース配線３４を形成する。具体的には、絶縁層３９の上にソース配線３４の材料（ソースメタル）となる金属膜（例えば、Ｃｕ膜）を積層した後、レジストパターン（不図示）をマスクとしてウエットエッチングすることによって形成される。ここで、エッチング液（エッチャント）は、例えば、フッ化化合物を含む溶液である。 Thereafter, as shown in FIG. 18D, a source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41. Specifically, a metal film (for example, a Cu film) serving as a material (source metal) of the source wiring 34 is stacked on the insulating layer 39 and then wet-etched using a resist pattern (not shown) as a mask. Is done. Here, the etching solution (etchant) is, for example, a solution containing a fluorinated compound.
　本実施形態の手法によれば、Ｃｓ配線３５とソース配線３４との交差領域４０において、ソース配線３４の段差４５の勾配を緩和する半導体層４１が形成されているので、ソース配線３４の断線も抑制することが容易となる。 According to the method of the present embodiment, since the semiconductor layer 41 that reduces the gradient of the step 45 of the source wiring 34 is formed in the intersection region 40 between the Cs wiring 35 and the source wiring 34, disconnection of the source wiring 34 is also prevented. It becomes easy to suppress.
　次に、図１９（ａ）から（ｄ）を参照しながら、本実施形態における交差領域４０における半導体層４１およびソース配線３４の他の製造方法について説明する。図１９（ａ）から（ｄ）は、本実施形態の他の製造方法を説明するための工程断面図である。 Next, another method for manufacturing the semiconductor layer 41 and the source wiring 34 in the intersecting region 40 in this embodiment will be described with reference to FIGS. 19A to 19D. FIGS. 19A to 19D are process cross-sectional views for explaining another manufacturing method of the present embodiment.
　まず、図１９（ａ）に示すように、ガラス基板３８の上にＣｓ配線３５および絶縁層３９を形成した後、絶縁層３９の上に、半導体層４１の材料となる半導体材料４１ｃを堆積する。これは、上述した図１８（ａ）と同様である。 First, as shown in FIG. 19A, a Cs wiring 35 and an insulating layer 39 are formed on a glass substrate 38, and then a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39. . This is the same as FIG. 18A described above.
　次に、図１９（ｂ）に示すように、少なくとも二段構造の半導体層４１のパターンを規定するレジストパターン４１ｎを形成する。図１９（ｂ）に示したレジストパターン４１ｎは、ハーフトーンフォトグラフィによって段差４１ｇを有するように形成されている。なお、ドライエッチングの後は、レジストパターン４１ｎは取り除かれる。 Next, as shown in FIG. 19B, a resist pattern 41n that defines the pattern of the semiconductor layer 41 having at least a two-stage structure is formed. The resist pattern 41n shown in FIG. 19B is formed so as to have a step 41g by halftone photography. Note that the resist pattern 41n is removed after the dry etching.
　次に、図１９（ｃ）に示すように、段差４１ｇを有するレジストパターン４１ｎをマスクとして、半導体材料４１ｃをドライエッチングすることによって、半導体材料４１ｃから、第１段差部４１ａおよび第２段差部４１ｂを有する半導体層４１を得る。なお、この例では、図１８（ｃ）と同様に、半導体層４１に少しの段差４１ｄが形成されている。 Next, as shown in FIG. 19C, by using the resist pattern 41n having the step 41g as a mask, the semiconductor material 41c is dry-etched, so that the first step portion 41a and the second step portion 41b are formed from the semiconductor material 41c. A semiconductor layer 41 having the following is obtained. In this example, a small step 41d is formed in the semiconductor layer 41 as in FIG.
　その後、図１９（ｄ）に示すように、段差部（４１ａ、４１ｂ）を有する半導体層４１を覆うように絶縁層３９の上にソース配線３４を形成する。具体的には、絶縁層３９の上にソース配線３４の材料（ソースメタル）となる金属膜（例えば、Ｃｕ膜）を積層した後、レジストパターン（不図示）をマスクとしてウエットエッチングすることによって形成される。 Thereafter, as shown in FIG. 19D, the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41 having the step portions (41a, 41b). Specifically, a metal film (for example, a Cu film) serving as a material (source metal) of the source wiring 34 is stacked on the insulating layer 39 and then wet-etched using a resist pattern (not shown) as a mask. Is done.
　図１９に示した実施形態の手法によれば、Ｃｓ配線３５とソース配線３４との交差領域４０において、少なくとも２つの段差部（４１ａ、４１ｂ）を有する半導体層４１を形成することができる。したがって、段差４５をより滑らかに変化させることができるので、ソース配線３４の断線をより効果的に抑制することができる。 19, the semiconductor layer 41 having at least two step portions (41a, 41b) can be formed in the intersecting region 40 of the Cs wiring 35 and the source wiring 34. Therefore, since the step 45 can be changed more smoothly, disconnection of the source wiring 34 can be more effectively suppressed.
　次に、図２０（ａ）から（ｄ）を参照しながら、本実施形態における交差領域４０における半導体層４１およびソース配線３４の他の製造方法について説明する。図２０（ａ）から（ｄ）は、本実施形態の他の製造方法を説明するための工程断面図である。 Next, another method for manufacturing the semiconductor layer 41 and the source wiring 34 in the intersecting region 40 in this embodiment will be described with reference to FIGS. 20A to 20D are process cross-sectional views for explaining another manufacturing method of the present embodiment.
　まず、図２０（ａ）に示すように、ガラス基板３８の上にＣｓ配線３５および絶縁層３９を形成した後、絶縁層３９の上に、半導体層４１の材料となる半導体材料４１ｃを堆積する。これは、上述した図１８（ａ）と同様である。 First, as shown in FIG. 20A, a Cs wiring 35 and an insulating layer 39 are formed on a glass substrate 38, and then a semiconductor material 41 c that is a material of the semiconductor layer 41 is deposited on the insulating layer 39. . This is the same as FIG. 18A described above.
　次に、図２０（ｂ）に示すように、Ｃｓ配線３５を乗り越えた部位の半導体材料４１ｃから少し離間した位置で、半導体材料４１ｃの上に、半導体層４１のパターンを規定するレジストパターン４１ｍを形成する。 Next, as shown in FIG. 20B, a resist pattern 41m that defines the pattern of the semiconductor layer 41 is formed on the semiconductor material 41c at a position slightly separated from the semiconductor material 41c at a position over the Cs wiring 35. Form.
　次に、図２０（ｃ）に示すように、レジストパターン４１ｍをマスクとして、半導体材料４１ｃをドライエッチングすることによって、半導体材料４１ｃから半導体層４１を得る。なお、レジストパターン４１ｍを少し離間して形成しているので、図１８（ｃ）に示した少しの段差４１ｄは半導体層４１には形成されていない。また、ドライエッチングの後は、レジストパターン４１ｍは取り除かれる。 Next, as shown in FIG. 20C, the semiconductor layer 41 is obtained from the semiconductor material 41c by dry etching the semiconductor material 41c using the resist pattern 41m as a mask. Since the resist pattern 41m is formed slightly apart, the slight step 41d shown in FIG. 18C is not formed in the semiconductor layer 41. Further, after dry etching, the resist pattern 41m is removed.
　その後、図２０（ｄ）に示すように、半導体層４１を覆うように絶縁層３９の上にソース配線３４を形成する。具体的には、絶縁層３９の上にソース配線３４の材料（ソースメタル）となる金属膜（例えば、Ｃｕ膜）を積層した後、レジストパターン（不図示）をマスクとしてウエットエッチングすることによって形成される。 Thereafter, as shown in FIG. 20D, the source wiring 34 is formed on the insulating layer 39 so as to cover the semiconductor layer 41. Specifically, a metal film (for example, a Cu film) serving as a material (source metal) of the source wiring 34 is stacked on the insulating layer 39 and then wet-etched using a resist pattern (not shown) as a mask. Is done.
　図２０に示した実施形態の手法によっても、Ｃｓ配線３５とソース配線３４との交差領域４０において、Ｃｓ配線３５の厚さよりも薄い半導体層４１を形成することができ、その結果、ソース配線３４の断線を抑制することができる。 20, the semiconductor layer 41 thinner than the thickness of the Cs wiring 35 can be formed in the intersection region 40 between the Cs wiring 35 and the source wiring 34, and as a result, the source wiring 34. Can be suppressed.
　なお、図１に示した本実施形態の液晶表示装置１００においては、液晶パネル１０及び／又は発光素子（例えば、ＬＥＤ素子）２３の駆動を制御する制御装置（不図示）を含めることができる。そのような制御装置は、半導体集積回路からなる。本実施形態の制御装置は、液晶パネル駆動部およびＬＥＤ駆動部を含んでいる。液晶パネル駆動部は、液晶パネル１０を駆動することによって液晶パネル１０に画像を表示させる部位であり、ゲートドライバ、ソースドライバなどのドライバ回路に該当する。ＬＥＤ駆動部は、各ＬＥＤ素子２３を個別に点灯／消灯させたり、発光強度を変更させるための部位であり、例えばスイッチ等を含むドライバ回路によって構成されている。なお、発光素子が冷陰極管（ＣＣＦＬ）の場合には、ＬＥＤ駆動部は、ＣＣＦＬ駆動部（または、バックライト駆動部）となる。 Note that the liquid crystal display device 100 of the present embodiment shown in FIG. 1 can include a control device (not shown) that controls the driving of the liquid crystal panel 10 and / or the light emitting elements (for example, LED elements) 23. Such a control device comprises a semiconductor integrated circuit. The control device of the present embodiment includes a liquid crystal panel driving unit and an LED driving unit. The liquid crystal panel driving unit is a part that displays an image on the liquid crystal panel 10 by driving the liquid crystal panel 10, and corresponds to a driver circuit such as a gate driver or a source driver. The LED drive unit is a part for individually turning on / off each LED element 23 or changing the light emission intensity, and is configured by a driver circuit including, for example, a switch. When the light emitting element is a cold cathode fluorescent lamp (CCFL), the LED driving unit is a CCFL driving unit (or a backlight driving unit).
　また、本実施形態のＬＥＤ素子２３は、導光板２２に光を出射するように複数個配列されており、例えば白色ＬＥＤからなる。図１に示した例では、導光板２２の一辺にＬＥＤ素子２３を配列させたが、それに限らず、導光板２２の二辺又はそれ以上（例えば、三辺）にＬＥＤ素子２３を配列させることも可能である。なお、上述したように、ＬＥＤ素子２３は、直下型のＬＥＤバックライトの構成で使用することも可能である。 Also, a plurality of the LED elements 23 of the present embodiment are arranged so as to emit light to the light guide plate 22, and are made of, for example, white LEDs. In the example shown in FIG. 1, the LED elements 23 are arranged on one side of the light guide plate 22, but not limited thereto, the LED elements 23 are arranged on two sides or more (for example, three sides) of the light guide plate 22. Is also possible. As described above, the LED element 23 can also be used in the configuration of a direct type LED backlight.
　以上、本発明を好適な実施形態により説明してきたが、こうした記述は限定事項ではなく、勿論、種々の改変が可能である。例えば、上述した実施形態では、１枚の液晶パネル１０を用いて画像表示部を構成しているが、複数枚の液晶パネル１０を組み合わせて１つの画像表示部（マルチディスプレイ）を構成することも可能である。そのような複数枚の液晶パネル１０を組み合わせた液晶表示装置１００を、大画面のデジタルサイネージ（例えば、１００インチ以上の表示装置）の用途に使用することも可能である。 As mentioned above, although this invention has been demonstrated by suitable embodiment, such description is not a limitation matter and, of course, various modifications are possible. For example, in the above-described embodiment, the image display unit is configured by using one liquid crystal panel 10, but one image display unit (multi-display) may be configured by combining a plurality of liquid crystal panels 10. Is possible. The liquid crystal display device 100 in which such a plurality of liquid crystal panels 10 are combined can be used for a large-screen digital signage (for example, a display device of 100 inches or more).
　本発明によれば、ソース配線の断線を抑制できる液晶パネル用アレイ基板および液晶パネルを提供することができる。 According to the present invention, it is possible to provide an array substrate for a liquid crystal panel and a liquid crystal panel that can suppress disconnection of the source wiring.
 １０ 液晶パネル
 １１ アレイ基板（ＴＦＴ基板）
 １２ カラーフィルタ基板
 １３ 偏光板
 ２０ バックライトユニット
 ２１ 光学シート
 ２２ 導光板
 ２３ 発光素子
 ２５ 配線基板
 ２７ 反射シート
 ２８ バックライトシャーシ
 ２９ ベゼル
 ３０ ＴＦＴ素子
 ３１ 半導体層
 ３２ｄ ドレイン電極
 ３２ｓ ソース電極
 ３３ ゲート配線
 ３４ ソース配線
 ３４ａ 本体部
 ３４ｃ 湾曲部
 ３５ 補助容量配線（Ｃｓ配線）
 ３６ ドレイン配線
 ３７ 画素電極
 ３８ 基板（ガラス基板）
 ３９ 絶縁層
 ４０ 交差領域
 ４１ 半導体層
 ４１ａ 第１段差部
 ４１ｂ 第２段差部
 ４１ｃ 半導体材料
 ４１ｆ 第１半導体層
 ４１ｓ 第２半導体層
 ４１ｍ、４１ｎ レジストパターン
 ４２ａ 凹部
 ４３ａ 波形部位
 ４５ 段差
 ４７ 交差領域
 ５０ 電流
１００ 液晶表示装置
１０００ 液晶パネル 10 Liquid crystal panel 11 Array substrate (TFT substrate)
DESCRIPTION OF SYMBOLS 12 Color filter substrate 13 Polarizing plate 20 Backlight unit 21 Optical sheet 22 Light guide plate 23 Light emitting element 25 Wiring board 27 Reflective sheet 28 Backlight chassis 29 Bezel 30 TFT element 31 Semiconductor layer 32d Drain electrode 32s Source electrode 33 Gate wiring 34 Source wiring 34a body part 34c bending part 35 auxiliary capacity wiring (Cs wiring)
36 Drain wiring 37 Pixel electrode 38 Substrate (glass substrate)
39 Insulating layer 40 Crossing region 41 Semiconductor layer 41a First step portion 41b Second step portion 41c Semiconductor material 41f First semiconductor layer 41s Second semiconductor layer 41m, 41n Resist pattern 42a Recess 43a Waveform portion 45 Step 47 Crossing region 50 Current 100 Liquid crystal display device 1000 Liquid crystal panel

Claims (12)

  1. 　行及び列を有するマトリックス状に画素が配置された液晶パネル用アレイ基板であって、
    　行方向に延びる補助容量配線と、
    　前記補助容量配線よりも上層に位置し、列方向に延びるソース配線と
    　を備え、
    　前記補助容量配線は、基板の上に形成されており、
    　前記基板の上には、前記補助容量配線を覆うように絶縁層が形成されており、
    　前記補助容量配線と前記ソース配線との交差領域において、前記絶縁層の上に、半導体層が形成されており、
    　前記ソース配線は、前記半導体層を覆うように前記絶縁層の上に形成されている、アレイ基板。     An array substrate for a liquid crystal panel in which pixels are arranged in a matrix having rows and columns,
    Auxiliary capacitance wiring extending in the row direction,
    A source wiring located above the auxiliary capacitance wiring and extending in the column direction,
    The auxiliary capacitance wiring is formed on a substrate,
    An insulating layer is formed on the substrate so as to cover the auxiliary capacitance wiring,
    A semiconductor layer is formed on the insulating layer in an intersection region between the auxiliary capacitance wiring and the source wiring,
    The array substrate, wherein the source wiring is formed on the insulating layer so as to cover the semiconductor layer.
  2. 　前記絶縁層の上に形成される前記半導体層は、前記交差領域における前記ソース配線の段差の勾配を緩和する段差緩和パターンである、請求項１に記載のアレイ基板。 The array substrate according to claim 1, wherein the semiconductor layer formed on the insulating layer is a step mitigation pattern for mitigating a step gradient of the source wiring in the intersection region.
  3. 　前記半導体層の厚さは、前記補助容量配線の厚さよりも小さい、請求項１または２に記載のアレイ基板。 3. The array substrate according to claim 1, wherein a thickness of the semiconductor layer is smaller than a thickness of the auxiliary capacitance wiring.
  4. 　前記半導体層は、少なくとも２段の段差構造を有している、請求項１から３の何れか１つに記載のアレイ基板。 The array substrate according to any one of claims 1 to 3, wherein the semiconductor layer has a step structure of at least two steps.
  5. 　前記半導体層は、前記補助容量配線と平行な方向である行方向に沿って延びている、請求項１から４の何れか１つに記載のアレイ基板。 The array substrate according to any one of claims 1 to 4, wherein the semiconductor layer extends along a row direction that is parallel to the storage capacitor wiring.
  6. 　前記半導体層は、
          前記補助容量配線の第１辺に沿って延びる第１半導体層と、
          前記補助容量配線の第２辺に沿って延びる第２半導体層と
    　を含んでいる、請求項５に記載のアレイ基板。     The semiconductor layer is
    A first semiconductor layer extending along a first side of the auxiliary capacitance wiring;
    The array substrate according to claim 5, further comprising: a second semiconductor layer extending along a second side of the auxiliary capacitance wiring.
  7. 　前記ソース配線のうち前記半導体層の上に位置する部位は、湾曲部となっている、請求項１から６の何れか１つに記載のアレイ基板。 The array substrate according to any one of claims 1 to 6, wherein a portion of the source wiring located on the semiconductor layer is a curved portion.
  8. 　前記ソース配線の下方に位置する半導体層の一部には、少なくとも１つの凹部が形成されている、請求項１から７の何れか１つに記載のアレイ基板。 The array substrate according to any one of claims 1 to 7, wherein at least one concave portion is formed in a part of the semiconductor layer located below the source wiring.
  9. 　前記補助容量配線と前記ソース配線との全ての前記交差領域において、前記半導体層が形成されている、請求項１から８の何れか１つに記載のアレイ基板。 The array substrate according to any one of claims 1 to 8, wherein the semiconductor layer is formed in all the intersecting regions of the storage capacitor wiring and the source wiring.
  10. 　前記マトリックス状に配置された画素のそれぞれには、薄膜トランジスタが形成されており、
    　前記薄膜トランジスタには、
          前記ソース配線から延びるソース電極と、
          前記ソース電極に対向して配置されたドレイン電極と
    　を備え、
    　前記ドレイン電極からは、画素電極に接続されるドレイン配線が延びており、
    　前記ドレイン配線の端部は、前記補助容量配線に接続されている、請求項１から９の何れか１つに記載のアレイ基板。     A thin film transistor is formed in each of the pixels arranged in the matrix,
    In the thin film transistor,
    A source electrode extending from the source wiring;
    A drain electrode disposed opposite to the source electrode,
    A drain wiring connected to the pixel electrode extends from the drain electrode,
    The array substrate according to claim 1, wherein an end portion of the drain wiring is connected to the auxiliary capacitance wiring.
  11. 　請求項１から１０の何れか１つに記載のアレイ基板と、
    　前記アレイ基板に対向して配置されるカラーフィルタ基板と、
    　前記アレイ基板と前記カラーフィルタ基板との間に配置される液晶層と
    　を備えた、液晶パネル。     The array substrate according to any one of claims 1 to 10,
    A color filter substrate disposed to face the array substrate;
    A liquid crystal panel, comprising: a liquid crystal layer disposed between the array substrate and the color filter substrate.
  12. 　請求項１１に記載の液晶パネルと、
    　前記液晶パネルに光を照射するバックライトユニットと
    　を備えた、液晶表示装置。     A liquid crystal panel according to claim 11;
    A liquid crystal display device comprising: a backlight unit that irradiates light to the liquid crystal panel.
PCT/JP2012/057469 2011-03-30 2012-03-23 Array substrate for liquid crystal panel and liquid crystal panel WO2012133157A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-075310 2011-03-30
JP2011075310 2011-03-30

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CN104460150A (en) * 2014-12-09 2015-03-25 深圳市华星光电技术有限公司 Array substrate, liquid crystal display panel and manufacturing method of array substrate
CN111697008A (en) * 2020-06-22 2020-09-22 成都中电熊猫显示科技有限公司 Array substrate and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104460150A (en) * 2014-12-09 2015-03-25 深圳市华星光电技术有限公司 Array substrate, liquid crystal display panel and manufacturing method of array substrate
CN111697008A (en) * 2020-06-22 2020-09-22 成都中电熊猫显示科技有限公司 Array substrate and manufacturing method thereof

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