JPS62280890A - Active matrix array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention Industrial Application Field The present invention relates to an active material having thin film semiconductor elements arranged in a matrix on an insulating substrate (IJ waxlay) and its manufacturing method, particularly to liquid crystals. The present invention relates to an active matrix array that drives a display device material such as a material or an electroluminescent material, or sequentially scans a sensor material such as a photoelectric conversion material.

Conventional technology Amorphous 'j is a non-single crystal semiconductor whose main component is silicon.
U'stone (amorphous silicon) is well known. For example, a thin film field effect transistor (hereinafter referred to as TPT) using amorphous silicon produced by plasma CVD method
Since it can be formed in a large area on a substrate such as glass at a temperature of around 300° C. and has a large on-off ratio, it has often been used in active matrix arrays used in liquid crystal display devices and the like. The following is a typical active matrix array using amorphous silicon.
An active matrix array for a liquid crystal display device (hereinafter referred to as a TFT array) having T's arranged in a matrix will be described in detail.

FIG. 5 is a circuit diagram of a typical liquid crystal display device using a TFT array. The area surrounded by the broken line abcd has a large number of pixels (the area surrounded by the broken line 11) repeated in a matrix. 1 is a first wiring to which a scanning signal is applied, and 2 is a second wiring to which an image signal is applied.

12 is a TPT for switching, 13 is a capacitor for storing image signals, and 10 is a common electrode wiring. A pixel electrode 9 drives a liquid crystal 14 sandwiched between it and a counter electrode 15 on a counter substrate to display an image. The portion other than the counter electrode 15 and the liquid crystal 14 within the broken line abed is fabricated as a TFT array built on an insulating substrate. Note that 16, 17, and 18 are peripheral circuits.

FIG. 6a is a partial plan view of a conventionally developed TFT array using an amorphous silicon semiconductor for a liquid crystal display device.
FIG. 6 is a sectional view taken along the line B-B in FIG. 61. FIG. 6 shows the structure of the TFTi 2, a part of the first wiring 1, a part of the second wiring 2, and a part of the pixel electrode 9 in FIG. 5, and the same parts as in FIG. 5 are given the same symbols. are doing. 3 is an insulating substrate, and a portion of the first wiring 1 serves as a gate electrode of an inverted staggered TPT. 4
is a gate insulating film, 6 is an amorphous silicon (semiconductor layer forming the channel part of TPT, hereinafter referred to as the first amorphous silicon), and 6 is a source electrode for the first amorphous silicon. 2 or drain electrode 8 is a low-resistance amorphous silicon (hereinafter referred to as second amorphous silicon) containing phosphorus as an impurity for making ohmic contact with the drain electrode 8. A portion of the second wiring 2 serves as a source electrode of the TPT, and is formed of two layers of conductive thin films together with the drain electrode 8. 2a and 8a are the first conductive thin films made of metal silicide (for example, MoSix), Ti, Ta, etc., and 2b and 8b are the second conductive thin films, and conductive thin films mainly composed of metal are often used. It will be done.

The function of the first conductive thin film is to suppress the diffusion of impurities into the amorphous silicon semiconductor layer during heating processes and voltage application, and to
In order to prevent deterioration of PT characteristics, metal silicide, Ta, or T may be used for the second wiring.
It is known that a large effect can be produced by using a thin film such as i as the first conductive thin film (for example, in JP-A No. 6
0-12770).

The cross-sectional shape of FIG. 6, which is a conventional structure, is shown for the sake of explanation when it is etched according to the shape of the resist, but in actual production, the shape is often different.

In particular, when the second wiring 2 is formed by wet etching, which has higher productivity than dry etching, the following phenomenon occurs.

Typically, an etching solution containing hydrofluoric acid is used for etching metal silicide, Ta, T, etc. Therefore, when patterning the source/drain electrodes by wet etching, it is often very difficult to etch them separately with a good selectivity from the semiconductor layer whose main component is silicon (for example, using a typical MoSix etching solution). 7) A mixed solution of acid and nitric acid is a typical etching solution for amorphous silicon). Also, non-uniformity in etching (
For example, non-uniformity in the film thickness and film quality of the film to be etched, variations in etching due to the number of substrates processed in the etching device and position of the substrates in the etching bath, variations in etching due to changes in the temperature and concentration of the etching solution, etc.) As a countermeasure, it is necessary to perform sufficient overetching. 7th
Figure (a) shows the TF before etching the source and drain electrodes.
It is a sectional view of the T section. patterned resist 19
The second conductive thin film 2b' and the first conductive thin film 2 are
Etch 1L'. After that, the second amorphous silicon 6' with low resistance containing impurities in the channel part of the TPT (between the source and drain electrodes) is removed using an etching solution containing hydrofluoric acid. In addition, the above-mentioned over-etching is also added, and in reality, the shape often ends up as shown in Figure 7.

Problems to be Solved by the Invention In the conventional TFT array having the above-mentioned particular structure, disconnection of the second wiring due to side etching of the first conductive thin film often became a problem. FIG. 8 is a diagram schematically expressing only the relationship between the first and second amorphous silicon and the second wiring 2 in FIG. 6. are given the same symbols). FIG. 8a shows the result after the step of selectively forming the second wiring by wet etching and the step of removing the second amorphous silicon in the channel portion. At this time, large side etching often occurs in the first conductive thin film at the pattern edges (line segments αβ and α'β') of the first and second amorphous silicon. Figure 8
The second conductive thin film 2a in the upper half of FIG. (This is thought to be caused by a local increase in the etching rate due to damage or stress concentration, etc., or the intrusion of etching solution due to cleaning residue caused by the step shape.) If this constriction progresses, it may lead to direct wire breakage, or even if it does not lead to direct wire breakage, it may cause wire breakage during subsequent cleaning (especially ultrasonic cleaning) or surface treatment of the TFT array (for example, alignment treatment in liquid crystal display devices). becomes. Particularly in the case of liquid crystal display devices having hundreds to hundreds of thousands of such configurations, the above-mentioned wire breakage is one of the factors that greatly reduces the manufacturing yield.

The object of the present invention is to reduce the probability of disconnection of the second wiring due to the constriction of the first conductive thin film in an extremely easy way, and to improve the manufacturing yield of active matrix arrays. It is.

Means for Solving the Problems Technical means of the present invention for solving the above problems are as follows:
The length of the pattern edge of the amorphous silicon is made longer than the wiring width of the second wiring, so that the shape is such that it is difficult to break even if a constriction occurs in the first conductive thin film.

Specifically, for example, the pattern shape of the first and second amorphous silicon semiconductor layers may be configured as a curved line or a broken line under the second wiring, or the width of the second wiring may be locally increased in that part. That's what I'll do. FIGS. 2 and 3 show the first and second amorphous silicon and the second wiring 2, similar to FIG.
This is a schematic representation of only the relationship between the following, and is after the process of selectively forming the second wiring by wet etching and the process of removing the second amorphous silicon in the channel part.
FIG. 2 and FIG. 3 are views with a portion of the second conductive thin film 2 removed. In FIG. 2, the pattern edges of the first and second amorphous silicon form a curved line and a broken line under the second wiring 2, and in FIG. 3, the line width of the second wiring 2 itself is is locally thickened. Even if the first conductive thin film 2a has a constriction to the same extent as the conventional one, the constricted portion is still visible when comparing the conventional figure 8 and the present invention's figures 2 and 3. It is possible to secure a wide line width of the first conductive thin film 2a.

Effect The present invention uses the above-mentioned means to make the pattern edges of the first and second amorphous silicon under the second wiring longer than before, so that the length of the pattern edges of the first conductive thin film 2a can be made longer than before. Even if a constriction occurs due to etching, as described above, it is possible to suppress the local decrease in the line width of the first conductive thin film by an extremely easy method, and the probability of wire breakage due to the constriction is reduced.

Particularly in the case of a TFT array using inverted staggered TPTs, which includes many of the above-mentioned configurations, the reduction in the probability of disconnection due to this constriction helps improve manufacturing yield.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 1a is a partial plan view of a TFT array for a liquid crystal display device showing a first embodiment of the present invention, and FIG. 1 is a sectional view taken along line λB. The structure is almost the same as the conventional one shown in FIG. 6, and the same symbols have the same purpose.

3 is an insulating substrate, which is a glass substrate (Corning Corporation 705
9) is used. 1 is the first wiring and has a thickness of approximately 10
Cr thin film by sputtering method;ffl:II
F 6e+ f-form imaginary 1 or A, 1 is also h-mo Ichiju 4;
This serves as the gate electrode of a staggered TPT. Reference numeral 4 denotes a SiNx thin film having a thickness of about 3Q00 to 4500, formed by plasma CVD and used as a gate insulating film. 5 is the first layer with a thickness of about 1,508 to 500 using the plasma CVD method.
6 is a low-resistance second amorphous silicon containing phosphorus having a thickness of 300 to 700 nm by plasma CVD.

2a and 8a are first conductive thin films, which are MoSix thin films of about 1000 nm thick formed by sputtering.

2b and 8b are second conductive thin films, which are Ag thin films containing about 2% Si and having a thickness of about 7,000 yen by sputtering.

A part of the second wiring 2 serves as the source electrode of the TPT, and is selectively formed together with the drain electrode 8 by wet etching. At the same time as 8a, etching is performed with a mixed solution of 7-acid, nitric acid, and acetic acid. This is a SiNx thin film with a thickness of approximately 500 to 1,000 wafers formed by plasma CVD and used as an etching stopper in 7 cigarettes. 9 is a pixel electrode, which has a thickness of about 100 mm by sputtering.
There are 0 iTos.

Comparing Fig. 1 of the embodiment of the present invention and Fig. 6 of the conventional example, the second
The pattern shapes of the first and second amorphous silicon under the wiring are different, and are in the shape of a polygonal line (γε and 1762 parts), which is the configuration used in FIG. For this reason, even if the first conductive thin film 2a is constricted, it is much less likely to be disconnected than in the past, and the manufacturing yield of the TFT array having the structure shown in FIG. 1 in a matrix is improved.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a partial plan view of a TFT array for a liquid crystal display device showing a second embodiment, which was produced in the same process as FIG. 1, and the same components are given the same reference numerals. In the case of Fig. 4, there is a TPT at the intersection of the second wiring 2 and the first wiring 1.
The source electrode 22 is drawn out without forming the first wiring 1.
TPT is built into the top. At the intersection between the first wiring 1 and the second wiring 2 and at the intersection between the second wiring 2 and the common electrode wiring 10, a first amorphous silicon 5a, 5b and a second amorphous silicon are formed.
(In Figure 4, it is only under the second wiring, so it cannot be drawn in the plan view, but before the process of removing the second amorphous silicon in the channel part, the first and second amorphous silicon are patterned in the same shape) and Si
The Nx thin films a and 7b are left in place in order to leave a plurality of thin films at the intersections of the two types of wires to make it difficult for the wires to be shrunk. However, the amorphous silicon pattern edges (x, x', Y,
MoSi x which is the first conductive thin film mentioned above in Part 2)
A constriction occurs. Therefore, in FIG. 4, the second wiring 2
By making the pattern edges of the lower amorphous silicon curved lines in the X and X' parts and broken lines in the Y part, and locally increasing the line width of the second wiring 2 in the second part, the first conductive Even if a constriction occurs in the MoS material, which is a thin film, the probability of disconnection of the second wiring can be reduced compared to the conventional method due to the reasons mentioned above.
The manufacturing yield of a TFT array having the structure shown in FIG. 4 in a matrix is improved.

Effects of the Invention As described above, although the present invention has an extremely simple structure, it can reduce the probability of disconnection of the second wiring, improve the manufacturing yield of active matrix arrays, and is practically effective. .

[Brief explanation of the drawing]

FIG. 1a shows a TF for a liquid crystal display device according to a first embodiment of the present invention.
A partial plan view of the T array, and a sectional view taken along the line A-B of the same a,
2a and 3a are plan views of amorphous silicon and the second wiring portion in a TFT array according to an embodiment of the present invention, and FIGS. FIG. 3 is a plan view with some of the wiring in FIG. 6a is a partial plan view of a conventional TFT array for a liquid crystal display device, and the same is A of N1.
-B cross-sectional view, Figures 7a and b are cross-sectional views of the etching process of the TPT source and drain electrodes, Figure 8. is N1
1 is a plan view with some of the wiring removed, 1... first wiring, 2... second wiring, 5...
...First amorphous silicon, 6...Second amorphous silicon, 2a, 8a...First conductive thin film, 2b. 8b...Second conductive thin film. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure (OLn) Figure 3 (6 Otsu)
(8) Figure 4 Figure 5 1L-1-1--
” c Fig. 6 Fig. 8 (α) (-1

Claims (8)

[Claims] (1) A first wiring is formed using a conductive thin film on an insulating substrate, and a first non-single crystal semiconductor layer mainly composed of silicon partially overlaps the first wiring via the insulating thin film. selectively forming a second wiring having at least partially a two-layer structure consisting of a first conductive thin film and a second conductive thin film, the first conductive thin film being a metal The first conductive thin film and the first non-single-crystal semiconductor layer are made of silicide, a thin film of Ti, Ta, etc., and the first conductive thin film and the first non-single crystal semiconductor layer are directly electrically contacted, or the main component is low-resistance silicon containing impurities. In an active matrix array formed through a second non-single-crystal semiconductor layer, the pattern shape of the first non-single-crystal semiconductor layer that crosses the second wiring or the second An active matrix array characterized in that the pattern shape of the non-single crystal semiconductor layer is a curved line or a polygonal line having one or more bending points under the second wiring. (2) A first non-single crystal semiconductor layer mainly composed of silicon and a second layer mainly composed of low resistance silicon containing impurities.
2. The active matrix array according to claim 1, wherein the non-single crystal semiconductor layer is an amorphous silicon semiconductor layer. (3) The active matrix array according to claim 2, characterized in that it has inverted staggered thin film field effect transistors arranged in a matrix. (4) The step of removing the second non-single crystal semiconductor layer in the channel portion of the inverted staggered thin film field effect transistor is performed by wet etching at the same time as or after the selective formation of the second wiring. An active matrix array according to claim 3. (5) A first wiring is formed using a conductive thin film on an insulating substrate, and a first non-single crystal semiconductor layer mainly composed of silicon partially overlaps the first wiring via the insulating thin film. selectively forming a second wiring having at least partially a two-layer structure consisting of a first conductive thin film and a second conductive thin film; The thin film is a thin film of metal silicide, Ti, Ta, etc., and furthermore, the first conductive thin film and the first non-single crystal semiconductor layer are directly electrically contacted, or low resistance silicon containing impurities is made. In an active matrix array formed through a second non-single-crystal semiconductor layer as a main component, pattern edges are formed by selectively forming the first non-single-crystal semiconductor layer or the second non-single-crystal semiconductor layer. When the second wiring is formed across the second wiring, the wiring width of the second wiring is locally formed to be thicker on the pattern edges of the first and second non-single crystal semiconductor layers. Active matrix array. (6) A first non-single crystal semiconductor layer mainly composed of silicon and a second layer mainly composed of low resistance silicon containing impurities.
6. The active matrix array according to claim 5, wherein the non-single crystal semiconductor layer is an amorphous silicon semiconductor layer. (7) The active matrix array according to claim 6, characterized in that it has inverted staggered thin film field effect transistors arranged in a matrix. (8) The step of removing the second non-single crystal semiconductor layer in the channel portion of the inverted staggered thin film field effect transistor is performed by wet etching at the same time as or after the selective formation of the second wiring. An active matrix array according to claim 7.