JPH11194361A - Manufacture of thin film transistor array substrate and liquid crystl display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array substrate where the number of processes and yield are improved by providing a conductive film pattern for anode oxidation, which is not connected to a gate electrode and a gate bus line, and forming a guard resistor between a short pattern and the conduc tive film pattern for anode oxidation. SOLUTION: The short pattern for anode oxidation 16 which is electrically shorted with the gate electrode and the gate bus line 3 and the conductive film pattern for anode oxidation 22 which is connected to the short pattern for anode oxidation 16 and is not connected to the gate electrode and the gate bus line 3 are formed. The gate bus line 3 and the conductive film pattern for anode oxidation 22 are connected through the guard resistor in a subsequent process. Namely, the guard resistor is formed in the case of the obtained TFT array substrate. Thus, the thin film transistor is prevented from being destroyed by static electricity even if after laser cutting for array inspection. Then, any material and any form are required for the guard resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter, referred to as a TFT) used for a liquid crystal display device.
The present invention relates to a method of manufacturing an array substrate, and more particularly to a method of manufacturing a TFT array substrate for a liquid crystal display device, which can prevent damage due to static electricity during a manufacturing process and can easily perform an array inspection.

[0002]

2. Description of the Related Art FIG. 12 is a schematic sectional view showing a method of manufacturing a TFT array substrate on which TFTs of a TFT type liquid crystal display device using conventional low resistance signal wiring are mounted. The manufacturing process is shown in FIGS. 12 (a),..., FIGS.
(G), where 1 is a glass substrate (insulating substrate) and 2 is a pure A formed on the glass substrate 1.
A single-layer gate electrode 3 made of a low-resistance metal such as l or Al alloy is a gate bus line extending the gate electrode 2. Reference numeral 4 denotes a resist pattern for partially protecting a terminal lead-out region on the gate bus line 3; The gate insulating film (first gate insulating film) and the interlayer insulating film formed as described above are not anodized under the resist pattern 4. 7, a gate insulating film (second gate insulating film) of a silicon nitride film formed on the glass substrate 1 including the gate electrode 2 on which the oxide film is formed and the gate bus line 3, and 8 a gate insulating film on the gate electrode 2. An amorphous silicon film (a-Si film) formed via the insulating film 7, an n + type amorphous silicon film (n + a-Si film) 9 formed on the amorphous silicon 8, and 10 a second Formed on the gate insulating film 7
The pixel electrode is composed of In addition, ITO (Indim T
“in Oxide” is a transparent conductive film made of In ₂ O ₃ and SnO ₂ . Reference numeral 11 denotes a terminal take-out opening formed by opening the gate insulating film 7 on the gate bus line 3. Further, 12 is a source / drain electrode provided on the n + type amorphous silicon film 9,
Reference numeral 13 denotes a terminal lead-out line formed of the same material as the source / drain electrode 12, reference numeral 14 denotes a channel portion formed by selectively etching the n + type amorphous silicon film 9, and reference numeral 15 denotes a portion covering the entire glass substrate 1. This is a passivation film formed as described above.

Next, FIG. 13 and FIG.
FIG. 13 is a schematic plan view of a portion where a guard resistor is to be originally formed in the T array substrate, and FIG.
FIG. 14 shows the latter half of the process. 13 and 14, 1 is a glass substrate, 3 is a gate bus line, 4 is a resist pattern, 7 is a gate insulating film (second gate insulating film), and 8 is an amorphous silicon film (a-S
i), 9 is an n + type amorphous silicon film (n + a-Si film), and 11 is a terminal extraction opening. further,
Reference numeral 16 denotes a short pattern for anodic oxidation, which is connected to the gate bus line 3. Reference numeral 17 denotes an anodized film, 19 denotes a terminal leading conductive film on the gate bus line 3, and 20 denotes a terminal leading conductive film on the anodized short pattern 16. FIG. 15 shows the TFT array substrate,
FIG. 4 is a schematic cross-sectional view of a portion where a guard resistor should be formed. In the figure, 1 is a glass substrate, 4 is a resist pattern, 7 is a gate insulating film (second gate insulating film), 8 is an amorphous silicon film, 9 is an n + type amorphous silicon film (n + a-Si film), Reference numeral 11 denotes a terminal take-out opening. Reference numeral 19 denotes a terminal leading conductive film on the gate bus line 3, 20 denotes a terminal leading conductive film on the anodic oxidation short pattern 16, and 21 denotes a cross section of the gate bus line 3 and the anodic oxidation short pattern 16.

Next, a TFT mounted with a TFT of a TFT type liquid crystal display device using such a conventional low resistance signal wiring.
A method for manufacturing an array substrate will be described with reference to FIG. A low-resistance metal film such as pure Al or an Al alloy is formed as a single layer on a glass substrate 1, resist patterning is performed, the metal film is etched, and a gate electrode 2 and a gate bus line 3 are formed. (FIG. 12 (a)). Next, a resist pattern 4 for partially protecting the terminal take-out region on the gate bus line 3 is formed, and the gate electrode 2 and the gate bus line 3 are selectively anodized using the formed resist pattern 4 as a mask. 12 to form a gate insulating film 5 and an interlayer insulating film 6 (FIG. 12).
(B)). In this method, since the anodic oxide film does not grow under the resist pattern 4, it is not necessary to remove the anodic oxide film on the surface of the terminal extraction region.

Next, PECVD (Plasma Enhanced Che)
mical Vapor Deposition: Also called plasma CVD)
Gate insulating film 7, amorphous silicon film 8,
In order to form an n + type amorphous silicon film 9 continuously and further form a channel portion of the transistor, the amorphous silicon film 8 and the n + type amorphous silicon film 9 are subjected to resist patterning and etching (
FIG. 12 (c)). Next, the pixel electrode 10 is formed by ITO (FIG. 12D), the gate insulating film 7 at the terminal take-out portion is etched, and the terminal opening 11 is formed on the gate bus line 3 to be exposed ( FIG. 12 (e)),
The source / drain electrodes 12 and the terminal lead lines 13 are formed of Cr or the like. Subsequently, the channel portion 14 is formed by selectively etching the n + -type amorphous silicon film 9 of the semiconductor layer by dry etching, and then the resist is removed (FIG. 12F). Finally, a passivation film 15 for protecting the TFT with an insulating film such as a silicon nitride film is formed. (FIG. 12 (g))

[0006]

However, in the conventional method using the anodic oxide film as the gate insulating film as described above, in order to form the anodic oxide film on the gate electrode and the gate bus line, the gate bus line 3 must be formed. The anodic oxidation short pattern 16 must be short-circuited. Therefore, the TF manufactured by the conventional method shown in FIG.
In the T-array substrate, it was necessary to separate the gate bus line 3 from the short-circuit pattern 16 for anodic oxidation at the time of an array inspection for inspecting whether or not each TFT exhibits desired electrical characteristics. For this reason, in the conventional method of cutting a large number of gate bus lines 3 from the anodic oxidation short pattern 16 using a laser, the cutting process takes a long time, and the number of gate bus lines further increases, so that the gate bus lines are increased. There is a problem that the difficulty of cutting increases as the line width becomes thinner and more delicate.

In addition, when a countermeasure against static electricity during the manufacturing process is taken, the gate bus line 3 and the anodic oxidation short pattern 16 are connected by a guard resistor having a resistance lower than that of the insulating film but considerably higher than that of the insulating film. Pattern 16
If a large current and a large voltage such as static electricity are generated, the gate and the source will have the same potential via the guard resistor, and will not adversely affect the transistor. When a transistor is tested by applying a potential to the source, the test is performed with a small current and a small voltage. Therefore, the gate and the source do not have the same potential via the guard resistor, and an array test can be performed. However, in the thin film transistor array substrate according to the conventional method, since the anodic oxide film is used as the gate insulating film, the gate bus line 3 and the short pattern 16 for anodic oxidation are formed to form the anodic oxide film on the gate electrode and the gate bus line. There is a problem that the short circuit must be short-circuited and the above-described guard resistance cannot be formed.

[0008] In recent years, liquid crystal display devices using such a thin film transistor array substrate have become increasingly finer.
There has been a demand for higher brightness, and there has been a problem that the aperture ratio of pixels must be further increased by thinning the pattern.

The present invention has been made to solve the above-mentioned conventional problems, and eliminates the need for a step of cutting a gate bus line from a short pattern for anodic oxidation by laser or the like at the time of array inspection. A first object is to obtain a method of manufacturing a thin film transistor array substrate with an improved number of steps and a yield in which a guard resistor is also formed between each gate bus line and a short pattern for anodic oxidation to prevent static electricity during the manufacturing process. And further,
A second object is to obtain a liquid crystal display device in which the number of manufacturing steps and the yield of a thin film transistor array substrate to be used are improved and the high aperture ratio of pixels is also improved.

[0010]

According to a method of manufacturing a thin film transistor array substrate according to the present invention, a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor are simultaneously formed on an insulating substrate. One electrode and a short pattern electrically connected to the first electrode wiring are formed on one end of the insulating substrate, and the other end is connected to the short pattern, but the first A first step of forming a conductive film pattern that is not connected to the electrode and the first electrode wiring, and a second step of forming a resist pattern in a terminal extraction portion on the first electrode wiring Disposing the insulating substrate such that the short pattern is formed in the chemical conversion solution and the conductive film pattern is formed on the chemical conversion surface, and the resist pattern is formed. A third step of forming a first insulating film on the first electrode and on the first electrode wiring and on the short pattern in the chemical conversion solution using a mask as a mask, and on the first electrode and A fourth step of forming a second insulating film on the insulating substrate including on the first electrode wiring, and a semiconductor layer of a thin film transistor on the first electrode via the second insulating film. A fifth step of forming, and a sixth step of forming a pixel electrode on the second insulating film,
A seventh step of providing an opening by etching the second insulating film of the terminal extraction portion on the first electrode wiring,
An eighth step of forming a second electrode and a third electrode of the thin film transistor on the semiconductor layer.

In a method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate at the same time as one end of the insulating substrate. A first step of forming a conductive film pattern not connected to the first electrode and the first electrode wiring on the side, and a material different from the material of the first electrode; The conductive film pattern is connected to the first electrode wiring by using a material which does not melt during the anodic oxidation treatment of the first electrode wiring and the first electrode wiring and can be etched with an etchant having a selectivity with the anodic oxide film. A second step of forming a short pattern so as to form a third step of forming a resist pattern at a terminal extraction portion on the first electrode wiring; and A fourth step of forming a first insulating film on the first electrode and the first electrode wiring as a mask, and etching the short pattern formed of a material different from the first electrode material A fifth step, a sixth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring, and a second step of forming a second insulating film on the first electrode. A seventh step of forming a semiconductor layer through the insulating film, an eighth step of forming a pixel electrode on the second insulating film, and a seventh step of forming a terminal on the first electrode wiring. A ninth step of forming an opening by etching the second insulating film; and a tenth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer.

Further, in the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate at the same time as one end of the insulating substrate. A first step of forming a conductive film pattern that is not connected to the first electrode or the first electrode wiring on the side, and a material different from the first electrode material; And using a material that is not melted during the anodic oxidation treatment of the first electrode wiring, and that can be etched with an anodic oxide film and an etchant having a selectivity with the first electrode material, the conductive film pattern and the first electrode. A second step of forming a short pattern so as to connect to the electrode wiring, and forming a contact pattern also at a terminal extraction portion on the first electrode wiring; A third step of forming a first insulating film on the first electrode and the first electrode wiring using the pattern as a mask, and the material formed of a material different from the material of the first electrode. A fourth step of etching the short pattern and the contact pattern, and a fifth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring, A sixth step of forming a semiconductor layer on the first electrode via the second insulating film, a seventh step of forming a pixel electrode on the second insulating film, Eighth step of providing an opening by etching the second insulating film of the terminal extraction part on the electrode wiring, and ninth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer And the step of

According to a method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate at the same time as one end of the insulating substrate. A first step of forming a conductive film pattern not connected to the first electrode and the first electrode wiring, the same material as the first electrode material, the conductive film pattern and the A second step of forming a short pattern with a smaller thickness than the first electrode and the first electrode wiring so as to connect to the first electrode wiring; A third step of forming a resist pattern on the terminal take-out portion, and a fourth step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask. And a fifth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring, and the second insulating film on the first electrode A sixth step of forming a semiconductor film through the film, a seventh step of forming a pixel electrode on the second insulating film, and a second step of forming a terminal on the first electrode wiring. And an ninth step of forming a second electrode and a third electrode on the semiconductor film.

Further, according to a method of manufacturing a thin film transistor array substrate according to the present invention, a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor are formed on an insulating substrate, and one end of the insulating substrate is provided on one end side of the insulating substrate. When forming a conductive film pattern, a portion connecting the conductive film pattern and the first electrode wiring is etched so as to be thinner than the first electrode and the first electrode wiring, A first step of forming a short pattern connecting the first electrode and the first electrode wiring, and a second step of forming a resist pattern in a terminal extraction portion on the first electrode wiring, A third step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask, and on the first electrode and the first A fourth step of forming a second insulating film on the insulating substrate including on the electrode wiring, and a fifth step of forming a semiconductor layer on the first electrode via the second insulating film. A step of forming a pixel electrode on the second insulating film, and a step of providing an opening by etching the second insulating film of a terminal extraction portion on the first electrode wiring. The method includes a seventh step and an eighth step of forming a second electrode and a third electrode of the thin film transistor on the semiconductor layer.

According to a method of manufacturing a thin film transistor array substrate according to the present invention, a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor are formed on an insulating substrate, and one end of the insulating substrate is provided. Before forming the conductive film pattern connected to the first electrode and the first electrode wiring, the conductive film pattern formed on one end side of the insulating substrate and the first electrode wiring A step of forming an insulating film pattern at a position below a portion connecting the first electrode and the first electrode and the first electrode wiring on the insulating substrate on which the insulating film pattern is formed. A second step of forming the conductive film pattern on the one end side of the insulating substrate, and forming a resist pattern on a terminal extraction portion on the first electrode wiring. A third step, a fourth step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask, and a fourth step of forming a first insulating film on the first electrode and the first electrode A fifth step of forming a second insulating film on the insulating substrate including on the electrode wiring, and a sixth step of forming a semiconductor layer on the first electrode via the second insulating film. And a seventh step of forming a pixel electrode on the second insulating film, and providing an opening by etching the second insulating film at a terminal extraction portion on the first electrode wiring. An eighth step, a ninth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer.

In the method for manufacturing a thin film transistor array substrate according to the present invention, the first insulating film is formed by anodic oxidation.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode and the first electrode wiring are formed using Al or an alloy containing Al as a main component. It is.

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a thin film transistor array substrate formed by the manufacturing method according to any one of claims 1 to 8; And a counter substrate having a counter electrode.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same as the conventional one means the same or equivalent to the conventional one. FIG. 1 is a schematic sectional view showing a method for manufacturing a TFT array substrate according to Embodiment 1 of the present invention. In the figure, 1 to 15 are the same as those shown in FIG. 12 for explaining the above-mentioned conventional manufacturing method, 1 is a glass substrate (insulating substrate), and 2 is a first electrode of a TFT. A gate electrode, 3 a gate bus line, 4 a resist pattern, 5 a gate insulating film (first gate insulating film), 6 an interlayer insulating film, 7 a gate insulating film (second gate insulating film),
8 is an amorphous silicon film (a-Si film), 9 is n +
Type amorphous silicon film (n + a-Si film), 10 is a pixel electrode, 11 is an opening for taking out a terminal, 12 is a source / drain electrode serving as second and third electrodes of a TFT, 13
Is a terminal lead-out line, 14 is a channel portion, and 15 is a passivation film.

FIGS. 2 and 3 are schematic plan views of a main part for describing a method of manufacturing a guard resistor of a TFT array substrate according to the first embodiment of the present invention. FIG. FIG. 3 shows the latter half of the process. In the figure, 1 is a glass substrate, 3 is a gate bus line, 4 is a resist pattern, 7 is a gate insulating film (second gate insulating film), 9 is an n + type amorphous silicon film (n + a-Si film), Reference numeral 11 denotes a terminal take-out opening. further,
Reference numeral 16 denotes a short pattern for anodic oxidation, which is connected to the gate bus line 3. Reference numeral 17 denotes an anodized film, 18 denotes a guard resistor, and 19 denotes a terminal leading conductive film on the gate bus line 3, which are the same as those described with reference to FIGS. Reference numeral 22 denotes an anodizing conductive film pattern which is connected to the anodizing short pattern 16 and is not connected to the gate electrode 2 and the gate bus line 3; 23, a guard resistance forming portion; 24, a laser cut portion; Is a terminal leading conductive film on the anodizing conductive film pattern 22 which is connected to the anodizing short pattern 16 and is not connected to the gate electrode 2 and the gate bus line 3. FIG. 4 is a timing chart of T according to the first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing a guard resistor of an FT array substrate.

Next, a manufacturing method will be described with reference to FIGS. First, as a first step, an Al film or an Al alloy film is formed on a transparent glass substrate (insulating substrate) 1.
For example, a low-resistance metal film such as Al-0.2 wt% Cu is formed to a thickness of about 2700 ° by a sputtering method or the like, and the gate electrode 2 and the gate bus line 3 are formed by a photolithography method. (FIG. 1 (a)). At the same time, the anodic oxidation short pattern 16 and the anodic oxidation short pattern 16 electrically connected to the gate electrode 2 and the gate bus line 3 and connected to the gate electrode 2 and the gate bus line 3 are not connected. A conductive film pattern 22 is formed (FIG. 2A). By doing so, the gate bus line 3 and the conductive film pattern 22 for anodic oxidation are not short-circuited, and a guard resistor is formed between the gate bus line 3 and the conductive film pattern 22 for anodic oxidation in a later step. Can be. An etching solution containing phosphoric acid, acetic acid, and nitric acid as main components is used for etching the Al film or the Al alloy film. The composition of phosphoric acid, acetic acid, and nitric acid is appropriately selected, and the Al film or the Al alloy film is tapered. Processing into a shape is desirable from the viewpoint that disconnection or the like of the upper layer can be prevented. Next, a resist pattern 4 for partially protecting the terminal take-out area on the gate bus line 3 is formed.

Next, the gate electrode 2 and the gate bus line 3
The one formed with the anodic oxidation short pattern 16 which is electrically short-circuited with the anodic oxidation short pattern 16 is connected to a chemical solution containing ammonium tartrate and ethylene glycol as main components. Anodizing conductive film pattern 22 not connected to line 3
The substrate is placed so that the side on which the film is formed is on the surface of the chemical conversion solution, and the gate electrode 2 and the gate bus line 3 are selectively anodized using the resist pattern 4 as a mask to form a first gate insulating film 5 and an interlayer insulating film. A film 6 is formed. (Figure 1
(B) At this time, the anodic oxide film, that is, the first interlayer insulating film 6 does not grow below the resist pattern 4. Therefore, a new process of removing the anodic oxide film at the time of forming the wiring terminal portion is unnecessary.

Next, about 3700 silicon nitride is used as the second gate insulating film 7 on the entire surface by a plasma CVD method or the like.
Å Film formation, and then using the plasma CVD method, etc.
Amorphous silicon (hereinafter a-Si film) is about 1
200 °, n doped with impurities having ohmic contact
+ Type amorphous silicon (hereinafter referred to as n + a-Si)
A film 9 is sequentially formed in a thickness of about 300 ° and patterned by photolithography to form an a-Si film 8 serving as a semiconductor layer of a TFT portion and a high-resistance portion of a guard resistor and an ohmic contact n + a-Si film 9. Form. (Figure 1
(C) Next, as a transparent electrode film, an ITO film is formed to a thickness of about 1000 by a sputtering method or the like, and the pixel electrode 10 is formed by a photolithography method. (Fig. 1 (d))

Next, the silicon nitride of the second gate insulating film 7 is etched by dry etching to open and expose the terminal portion 11 on the gate bus line 3.
(FIG. 1E) Next, in order to form the source / drain electrodes 12 and the source bus lines (not shown), the n + a-Si film 9 and the ITO film of the pixel electrode 10 are formed by sputtering or the like. The lowermost layer is a Cr film that can make ohmic contact of about 1000 Å, and the low resistance Al-
A 0.2 wt% Cu film is continuously formed at about 3000 Å, and a Cr film is formed at the uppermost layer for about 500 Å to form a three-layer structure. Thereafter, the three-layered film is sequentially etched by using a photolithography method to form a source / drain electrode 12 and a source bus line serving as a second electrode and a third electrode of the TFT.

At this time, the terminal lead-out line 13 is also formed at the same time. Subsequently, the n + a-Si film 9 of the semiconductor layer is selectively etched by a dry etching method,
After forming the channel portion 14, the resist is removed.
(FIG. 1 (f)) Finally, in order to protect the TFT, a silicon nitride film is formed on the entire surface by a plasma CVD method or the like to a thickness of about 5000.degree.
A passivation film 15 was formed to obtain a desired TFT array substrate. (FIG. 1 (g)) In the TFT array substrate according to the first embodiment thus obtained, the gate bus line 3
There is no short circuit between the gate bus line 3 and the anodizing conductive film pattern 22 via the guard resistor 18 in a subsequent step. (FIG. 3 (e))

As described above, the manufacturing method of the thin film transistor array substrate according to the first embodiment is the same as the method of manufacturing the thin film transistor first electrode (gate electrode 2) and the thin film transistor Simultaneously with forming the electrode wiring (gate bus line 3), a short pattern 16 electrically connected to the first electrode and the first electrode wiring is formed on one end side of the insulating substrate; A second conductive film pattern (conductive film pattern for anodic oxidation 22) is formed on the other end side, which is connected to the short pattern but is not connected to the first electrode or the first electrode wiring. One step, a second step of forming a resist pattern 4 at a terminal extraction portion on the first electrode wiring, and a step of forming the short pattern 16 in a chemical solution. The insulating substrate 1 is arranged so that the side on which the conductive film pattern is formed is on the chemical conversion surface, and the resist pattern 4 is used as a mask on the first electrode and the first electrode wiring and A third step of forming a first insulating film (first gate insulating film 5 or interlayer insulating film 6) on the short pattern 16 in the chemical conversion solution, and on the first electrode and the first A fourth step of forming a second insulating film (second gate insulating film 7) on the insulating substrate including on the electrode wiring, and forming the second insulating film on the first electrode with the second insulating film interposed therebetween. The semiconductor layer of the thin film transistor (a-Si film 8 and ohmic contact n + a
A fifth step of forming a pixel electrode 10 on the second insulating film, and a fifth step of forming a pixel electrode 10 on the second insulating film; A seventh step of providing an opening 11 by etching the insulating film of the above, and an eighth step of forming a second electrode and a third electrode (source / drain electrode 12) of the thin film transistor on the semiconductor layer. It had.

However, T obtained by the method of Embodiment 1
In the case of an FT array substrate, the short-circuit pattern 16 for anodic oxidation and the source bus line are short-circuited to prevent static electricity. In other words, since the gate and the source are short-circuited, the laser cutting section 24 shown in FIG.
And the short pattern 16 for anodic oxidation. In the case of the TFT array substrate obtained by the conventional method, when the laser cutting is performed to separate the gate bus line from the short pattern for anodic oxidation, the thin film transistor may be destroyed by static electricity generated thereafter. In the case of the TFT array substrate obtained by the method 1, since the guard resistor 18 has been formed, the thin film transistor is not destroyed by static electricity even after laser cutting for array inspection. Further, the guard resistor 18 shown in FIG. 3 is merely an example, and the material is not limited to this, and any material may be used as long as it connects the gate bus line 3 and the conductive film pattern 22 for anodic oxidation. Any shape is acceptable.

Embodiment 2 FIGS. 5 to 7 are schematic plan views of main parts for describing a method of manufacturing a guard resistor of a TFT array substrate according to Embodiment 2 of the present invention.
FIG. 5 shows the first half, FIG. 6 shows the middle half, and FIG. 7 shows the second half. 5 to 7, 3 is a gate bus line, 4 is a resist pattern for partially protecting a terminal take-out region, 7 is a second gate insulating film, and 9 is n
+ a-Si film, 11 is an opening for taking out a terminal, 17 is an anodic oxide film, 18 is a guard resistor, 19 is a conductive film for taking out a terminal on a gate bus line, and 26 is an anode not connected to a gate electrode or a gate bus line. Conductive film pattern for oxidation, 2
7 is a short pattern connecting the gate bus line 3 and the conductive film pattern 26 with a different material from the gate electrode and the gate bus line, 28 is a terminal leading conductive film on the anodizing conductive film pattern 26, and 29 is a source short pattern. is there.

Next, a second embodiment will be described with reference to FIGS.
A method for manufacturing a TFT array substrate will be described.
First, as a first step, an Al film or an Al alloy film, for example, an Al— film is formed on a transparent glass substrate (insulating substrate) 1.
A low-resistance metal film such as 0.2 wt% Cu is formed to a thickness of about 2700 ° by a sputtering method or the like, and a gate electrode and a gate bus line 3 are formed by a photolithography method. (FIG. 5A) At the same time, a conductive film pattern 26 for anodic oxidation not connected to the gate electrode or the gate bus line 3 is formed.
By doing so, the gate bus line 3 and the anodizing conductive film pattern 26 are not short-circuited, and the guard resistance is provided between the gate bus line 3 and the anodizing conductive film pattern 26 (FIG. 5A). Can be made. Also, an Al film or A
An etching solution containing phosphoric acid, acetic acid, and nitric acid as a main component is used for etching the l-alloy film, but the composition of the phosphoric acid, acetic acid, and nitric acid is appropriately selected, and the Al film or the Al alloy film is processed into a tapered shape. However, it is desirable because disconnection of the upper layer can be prevented.

Next, as a conductive film for short-circuiting the gate bus line 3 and the conductive film pattern 26 for anodic oxidation,
W or an alloy containing W as a main component is formed on the entire surface by sputtering or the like, and the gate bus line 3 and the conductive film pattern 2 for anodic oxidation are formed by photolithography.
6 are formed to form a short pattern 27 for connection with the second pattern 6. (FIG. 5B) Note that Ti, Zr, Nb and an alloy containing these as main components may be used instead of W. Cr and Mo are dissolved during the anodic oxidation in the case of the chemical conversion solution (ammonium tartrate + ethylene glycol) used in the second embodiment, but the anodizing treatment may be completed before complete dissolution. Also, Cr,
When Mo is used, for example, it does not dissolve if a tartaric acid solution is used as a chemical conversion solution. In addition, the resist used for forming the short pattern 27 is removed before forming the terminal take-out area protection resist.

Next, a resist pattern 4 for partially protecting the terminal take-out area on the gate bus line 3 is formed. Next, the gate electrode and the gate bus line 3 are selectively anodized using the resist pattern as a mask,
Forming a first gate insulating film and an interlayer insulating film; (FIG. 5C) At this time, the anodic oxide film, that is, the first interlayer insulating film 6 does not grow below the resist pattern 4. Therefore, a new process of removing the anodic oxide film at the time of forming the wiring terminal portion is unnecessary. Next, the short pattern 27 is removed by etching. (FIG. 6D) By doing so, an anodic oxide film can be formed on the gate electrode and the gate bus line, and the gate bus line 3 and the anodic oxidation conductive film pattern 26 can be The guard resistor 18 can be formed between them.

Next, silicon nitride is applied to the entire surface as a second gate insulating film by a plasma CVD method or the like at about 3700 ° C.
A film is formed, and subsequently, a
-Si film is formed at about 1200 °, and an impurity doped n + a-Si film having ohmic contact property is formed at about 300 ° sequentially.
Patterning using photolithography, T
A serving as a high resistance part of the semiconductor layer and the guard resistance of the FT part
Forming an ohmic contact n + a-Si film with the Si film; (FIG. 6E) Next, as a transparent electrode film, an ITO film is formed to a thickness of about 1000 ° by a sputtering method or the like, and a pixel electrode is formed by a photolithography method.

Next, the silicon nitride 7 of the second gate insulating film 7 is etched by dry etching to open and expose terminals on the gate bus lines and the conductive film pattern 26 for anodic oxidation. (FIG. 6F) Next, in order to form source / drain electrodes and source bus lines, n + a-
The lowermost layer is a Cr film capable of making ohmic contact between the Si film and the ITO film of the pixel electrode, and the lowermost layer is about 1000 °.
000Å and a Cr film as the uppermost layer is continuously formed for about 500Å to form a three-layer structure. Thereafter, the three-layer film is sequentially etched by using a photolithography method to form source / drain electrodes and source bus lines. At this time,
Terminal lead lines and terminal lead conductive films 19 and 28 are also formed at the same time. Subsequently, the n + a-Si film of the semiconductor layer is selectively etched by a dry etching method to form a channel portion and a guard resistor, and then the resist is removed. Finally, in order to protect the TFT, a silicon nitride film is formed on the entire surface for about 5
000 to form a passivation film to obtain a desired TFT array substrate.

As described above, the manufacturing method of the thin film transistor array substrate according to the second embodiment is the same as the method of manufacturing the thin film transistor array substrate according to the first embodiment. At the same time as forming the electrode wiring (gate bus line 3) on one end of the insulating substrate, the conductive film pattern not connected to the first electrode and the first electrode wiring (conductive for anodic oxidation) A first step of forming a film pattern 26);
A material which is different from the material of the first electrode and which does not melt during the anodic oxidation treatment of the first electrode and the first electrode wiring, and can be etched with an etchant having a selectivity with the anodic oxide film. Using the short pattern 2 to connect the conductive film pattern and the first electrode wiring.
7, a third step of forming a resist pattern 4 at a terminal extraction portion on the first electrode wiring, and a step of forming a resist pattern 4 A fourth step of forming a first insulating film on one electrode wiring, a fifth step of etching the short pattern 27 formed of a material different from the first electrode material, A sixth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring; and forming a semiconductor layer on the first electrode with the second insulating film interposed therebetween. a-Si film and ohmic contact n + a-
A seventh step of forming a pixel electrode on the second insulating film, and a second step of forming a pixel electrode on the second insulating film; A ninth step of providing an opening by etching, and forming a second electrode and a third electrode (source / source) of the thin film transistor on the semiconductor layer.
And a tenth step of forming a drain electrode).

The T of the second embodiment obtained in this manner is
In the FT array substrate, the gate bus line 3 and the anodic oxidation conductive film pattern 26 are not short-circuited after the anodic oxidation treatment, and the gate bus line 3 and the anodic oxidation conductive film pattern 26 are connected in a subsequent step. It can be connected via the guard resistor 18. In the TFT array substrate obtained in the first embodiment, the guard resistor 18 could be formed, but it was necessary to separate the anodizing short pattern 16 and the gate bus line 3 by laser during the array inspection. However, in the TFT array substrate obtained in the second embodiment, not only the guard resistor 18 can be formed in a later process, but also since there is no short circuit between the gate and the source, there is no need to perform laser cutting during array inspection. Also, the guard resistance shown in FIG. 7 is merely an example,
The material is not limited to this, and any material and any shape may be used as long as the gate bus line 3 is connected to the conductive film pattern 26 for anodic oxidation with a high resistance. Further, FIG. 7 (g2)
The guard resistor can be formed by a source short pattern as described above. In this case, the conductive film pattern 26 for anodic oxidation becomes unnecessary. The conductive material used for forming the short pattern in the second step is W, Ti, Z
Since it is one of r, Nb, Cr, Mo and an alloy containing these as main components, it can function effectively as a short pattern in the fourth step.

Embodiment 3 FIG. 8 is a schematic sectional view showing a method of manufacturing an inverted staggered TFT array substrate according to Embodiment 3 of the present invention. In the figure, 1-3, 5-1
5 is the same as the above-mentioned conventional method, and the description thereof is omitted. Reference numeral 30 shown in FIG. 8B indicates a conductive film pattern (contact pattern) for protecting a terminal extraction region on the gate bus line 3.

Next, a method of manufacturing the inverted staggered TFT array substrate according to the third embodiment will be described with reference to FIGS. First, as a first step, an Al film or an Al alloy film, for example, a low-resistance metal film such as Al-0.2 wt% Cu is formed on a transparent glass substrate (insulating substrate) 1 by a sputtering method or the like at about 2700 °. A film is formed, and a gate electrode 2 and a gate bus line 3 are formed by using a photolithography method (FIG. 8A). At the same time,
Similarly to the second embodiment, an anodizing conductive film pattern 26 not connected to the gate electrode or the gate bus line 3 is formed (FIG. 5A). By doing so, the gate bus line 3 and the conductive film pattern 26 for anodic oxidation are not short-circuited, and a guard resistor can be formed between the gate bus line 3 and the conductive film pattern 26 for anodic oxidation.
For etching the Al film or the Al alloy film, an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components is used. The composition of phosphoric acid, acetic acid, and nitric acid is appropriately selected, and the Al film or the Al alloy film is formed. Processing into a tapered shape is preferable from the viewpoint that disconnection of the upper layer can be prevented.

Next, as a conductive film for short-circuiting the gate bus line 3 and the conductive film pattern 26 for anodic oxidation,
W or an alloy containing W as a main component is formed over the entire surface by sputtering or the like, and a short pattern 27 connecting the gate bus line 3 and the conductive film pattern 26 for anodic oxidation is formed by photolithography. Form.
(FIG. 5B) At the same time, a conductive film pattern 30 that partially protects the terminal extraction region on the gate bus line 3 is formed.
Note that Ti, Zr, Nb and alloys containing these as main components may be used instead of W. In the case of the chemical liquid (ammonium tartrate + ethylene glycol) used in the third embodiment, Cr dissolves during anodic oxidation, but the anodizing treatment may be completed before complete dissolution. When Cr is used, for example, it does not dissolve if a tartaric acid solution is used as a chemical conversion solution. Further, the resist used for forming the short pattern 27 and the conductive film pattern 30 for protecting the terminal extraction region is removed before the anodic oxidation.

Next, using the conductive film pattern 30 as a mask, the gate electrode 2 and the gate bus line 3 are selectively anodized to form a first gate insulating film 5 and an interlayer insulating film 6 (FIG. 8 ( b)). At this time, an anodic oxide film, that is, the first interlayer insulating film 6 is formed under the conductive film pattern 30.
Does not grow. Therefore, a new process of removing the anodic oxide film at the time of forming the wiring terminal portion is unnecessary. Further, in the conventional method, since the region for taking out the terminal on the gate bus line 3 is protected by the resist, a dielectric breakdown occurs during the anodic oxidation. And the accuracy of the shape of the oxide film pattern as the gate insulating film has been reduced. Since the conductive film pattern 30 has excellent adhesion to the underlying metal film (gate bus line 3), an oxide film serving as the interlayer insulating film 6 can be formed without the conductive film pattern 30 being peeled off during anodic oxidation. Next, short pattern 27
Then, the terminal conductive region protecting conductive film pattern 30 is removed by etching. By doing so, an anodic oxide film can be formed on the gate electrode and the gate bus line, and a guard resistor is formed between the gate bus line 3 and the conductive film pattern 26 for anodic oxidation in the subsequent steps. be able to.

Next, silicon nitride is applied to the entire surface as a second gate insulating film 7 by using a plasma CVD method or the like.
Then, the a-Si film 8 is formed to about 1200 ° and the n + a-Si film 9 doped with an ohmic contact impurity is formed to about 30
A-Si film 8 to be a semiconductor layer of the TFT part 8
Then, an ohmic contact n + a-Si film 9 is formed (FIG. 8C). Next, about 1000 ITO films are formed as transparent electrode films by a sputtering method or the like, and the pixel electrodes 10 are formed by a photolithography method. (FIG. 8 (d))

Next, the second gate insulating film 7 is etched to open and expose the terminal portion 11 on the gate bus line 3. (FIG. 8E) Next, in order to form source / drain electrodes and source bus lines, n + a-
A Cr film capable of making an ohmic contact between the Si film 9 and the ITO film of the pixel electrode 10 is about 1000 mm as a lowermost layer, a low resistance Al-0.2 wt% Cu film is about 3000 mm as an intermediate layer, and further in a developing solution. Of the pixel electrode 10
A Cr film that suppresses battery reaction with the O film is formed as a top layer, and is continuously formed at about 500 ° to form a three-layer structure. After that, the three-layer film is sequentially etched using a photolithography method,
Source / drain electrodes 12 and source bus lines are formed. At this time, the terminal lead wire 13 is also formed at the same time. (FIG. 8 (f))

Further, the n + a-Si film 9 of the semiconductor layer is selectively etched by a dry etching method to form the channel portion 14, and then the resist is removed. (FIG. 8
(F)). Finally, in order to protect the TFT, a silicon nitride film is formed on the entire surface by a plasma CVD method or the like for about 5,000.
Å A film is formed, and a passivation film 15 is formed (FIG. 8).
(G)) A desired TFT array substrate was obtained.

As described above, the method for manufacturing a thin film transistor array substrate according to the third embodiment includes a method of manufacturing the first electrode (gate electrode 2) of the thin film transistor and the first electrode of the thin film transistor on an insulating substrate (glass substrate 1). At the same time as forming the electrode wiring (gate bus line 3), a conductive film pattern (conductive for anodic oxidation) not connected to the first electrode or the first electrode wiring on one end side of the insulating substrate. The first step of forming the film pattern 26) is a material different from the first electrode material, and is not dissolved during the anodic oxidation treatment of the first electrode and the first electrode wiring, and Using a film and a material which can be etched with an etchant having a selectivity with the first electrode material, a short pattern 2 is used to connect the conductive film pattern and the first electrode wiring. A second step of forming a contact pattern (conductive film pattern 30 for protecting a terminal lead-out area) also at a terminal lead-out portion on the first electrode wiring; and A third step of forming a first insulating film (a first gate insulating film 5 or an interlayer insulating film 6) on one electrode and on a first electrode wiring; A fourth step of etching the short pattern 27 and the contact pattern (conductive film pattern 30) formed of a different material, and on an insulating substrate including the first electrode and the first electrode wiring. A fifth step of forming a second insulating film (second gate insulating film 7), and a semiconductor layer (a-Si) on the first electrode with the second insulating film interposed therebetween.
A sixth step of forming the film 8 and the ohmic contact n + a-Si film 9), a seventh step of forming the pixel electrode 10 on the second insulating film, and a step of forming the pixel electrode 10 on the first electrode wiring. An eighth step of etching the second insulating film of the terminal take-out portion to provide an opening (terminal take-out opening 11); and forming a second electrode and a third electrode (source) of a thin film transistor on the semiconductor layer. A ninth step of forming the drain electrode 12).

The T obtained in the third embodiment thus obtained is
In the FT array substrate, the gate bus line 3 and the anodic oxidation conductive film pattern 26 are not short-circuited after the anodic oxidation treatment, and the gate bus line 3 and the anodic oxidation conductive film pattern 26 are connected in a subsequent step. It could be connected via a guard resistor. Note that the T obtained in the second embodiment is
Like the FT array substrate, the TFT obtained in Embodiment 3
Not only was a guard resistor formed on the array substrate, but the gate and source were not short-circuited, eliminating the need for laser cutting during array inspection. Further, the conductive material used for forming the short pattern in the second step is any one of W, Ti, Zr, Nb, Cr and an alloy containing these as main components. Can be effectively functioned as. The conductive material used for forming the contact pattern in the second step is the same as the conductive material used for forming the short pattern, and is composed of W, Ti, Zr, Nb, Cr and an alloy containing these as main components. Either of them can effectively function as a protection mask in the third step, and the number of steps can be reduced.

Fourth Embodiment FIG. 9 is a schematic sectional view showing a method for manufacturing a guard resistor of a TFT array substrate according to a fourth embodiment of the present invention. In the figure, 1, 3, 4,
7 to 9, 11, 18, and 19 are the same as those in the above-described conventional method, and 26 and 28 are the same as those in the second embodiment, and a description thereof will be omitted. Reference numeral 31 denotes a short pattern for connecting the gate bus line 3 to the conductive film pattern 26 for anodic oxidation using the same material as the gate electrode and the gate bus line 3, and reference numeral 17 denotes an anodic oxide film.

Next, a method of manufacturing the TFT array substrate according to the fourth embodiment will be described with reference to FIG. First,
As a first step, an Al film or an Al alloy film, for example, Al-0.2 wt.
A metal film having a low resistance such as% Cu is formed to a thickness of about 2700 ° by a sputtering method or the like, and a gate electrode and a gate bus line 3 are formed by a photolithography method.
At the same time, a conductive film pattern 26 for anodic oxidation not connected to the gate electrode or the gate bus line 3 is formed. (FIG. 9A) By doing so, the gate bus line 3 and the anodizing conductive film pattern 26 are not short-circuited, and the guard resistance is provided between the gate bus line 3 and the anodizing conductive film pattern 26. Can be made. Also, an Al film or A
An etching solution containing phosphoric acid, acetic acid, and nitric acid as a main component is used for etching the l-alloy film, but the composition of the phosphoric acid, acetic acid, and nitric acid is appropriately selected, and the Al film or the Al alloy film is processed into a tapered shape. However, it is desirable because disconnection of the upper layer can be prevented.

Next, as a conductive film for short-circuiting the gate bus line 3 and the conductive film pattern 26 for anodic oxidation,
The same material as the gate electrode and the gate bus line 3 is formed on the entire surface by sputtering or the like so as to have a conductive film thickness enough to obtain a desired oxide film thickness, and the gate bus line 3 is formed by photolithography. And a short pattern 31 connecting the conductive pattern 26 to the anodizing conductive film pattern 26 is formed.
(FIG. 9B) Further, the resist used for forming the short pattern 31 is removed before forming the terminal take-out area protecting resist.

Next, a resist pattern for partially protecting the terminal take-out area on the gate bus line 3 is formed. Next, using the resist pattern as a mask, the gate electrode and the gate bus line 3 are selectively anodized to form a first gate insulating film and an interlayer insulating film. At this time, the anodic oxide film, that is, the first interlayer insulating film 6 does not grow below the resist pattern 4. Therefore, a new process of removing the anodic oxide film at the time of forming the wiring terminal portion is unnecessary. At this time, the short pattern 31
Is also anodized. The short pattern 31 is formed only to obtain a desired oxide film, and the anodic oxidation process automatically ends when all the conductive films of the short pattern 31 become oxide films. (FIG. 9C) At this point, the gate bus line 3 and the conductive film pattern 26 for anodic oxidation are electrically opened. By doing so, anodic oxide film 17 can be formed on the gate electrode and the gate bus line, and a guard resistor is formed between gate bus line 3 and conductive film pattern 26 for anodic oxidation in the subsequent steps. Can be made.

Next, silicon nitride is applied to the entire surface as a second gate insulating film by a plasma CVD method or the like at about 3700 ° C.
A film is formed, and subsequently, a
-Si film is formed at about 1200 °, and an impurity doped n + a-Si film having ohmic contact property is formed at about 300 ° sequentially.
Patterning using photolithography, T
An a-Si film 8 serving as a semiconductor layer of the FT portion and an ohmic contact n + a-Si film 9 are formed. (FIG. 9D) Next, as a transparent electrode film, an ITO film is formed to a thickness of about 1000 ° by a sputtering method or the like, and a pixel electrode is formed by a photolithography method.

Next, the silicon nitride of the second gate insulating film is etched by dry etching to open and expose a terminal portion on the gate bus line 3. (FIG. 9
(E) Next, in order to form source / drain electrodes and source bus lines, n + a-
The lowermost layer is a Cr film capable of making ohmic contact between the Si film and the ITO film of the pixel electrode, and the lowermost layer is about 1000 °.
000Å and a Cr film as the uppermost layer is continuously formed for about 500Å to form a three-layer structure. Thereafter, the three-layer film is sequentially etched by using a photolithography method to form source / drain electrodes and source bus lines.

At this time, terminal lead lines are also formed at the same time. Subsequently, the n + a-Si film of the semiconductor layer is selectively etched by a dry etching method to form a channel portion, and then the resist is removed. Finally, TF
In order to protect T, a silicon nitride film is formed by plasma CVD.
A film was formed on the entire surface by using a method such as a method of forming a passivation film, and a desired TFT array substrate was obtained.

As described above, in the method of manufacturing the thin film transistor array substrate according to the fourth embodiment, the first electrode (gate electrode 2) of the thin film transistor and the first electrode of the thin film transistor are formed on the insulating substrate (glass substrate 1). At the same time as forming the electrode wiring (gate bus line 3), a conductive film pattern (anodic oxidation conductive film) not connected to the first electrode or the first electrode wiring is formed on one end side of the insulating substrate. A first step of forming the pattern 26), and forming the short pattern 31 of the same material as the first electrode material so as to connect the conductive film pattern and the first electrode wiring. A second step of forming a thinner film than the first electrode and the first electrode wiring, and a third step of forming a resist pattern 4 at a terminal extraction portion on the first electrode wiring. A fourth step of forming a first insulating film (first gate insulating film 5 or interlayer insulating film 6) on the first electrode and the first electrode wiring using the resist pattern 4 as a mask; A fifth step of forming a second insulating film (second gate insulating film 7) on the insulating substrate including the first electrode and the first electrode wiring, and the first electrode A semiconductor layer (a-Si film 8 and ohmic contact n + a) is
A sixth step of forming a -Si film 9), a seventh step of forming a pixel electrode on the second insulating film, and a second step of extracting a terminal on the first electrode wiring. An eighth step of providing an opening 11 by etching the insulating film and a ninth step of forming a second electrode and a third electrode (source / drain electrode) on the semiconductor layer.

The T obtained in the fourth embodiment thus obtained.
In the FT array substrate, the gate bus line 3 and the anodic oxidation conductive film pattern 26 are not short-circuited after the anodic oxidation treatment, and the gate bus line 3 and the anodic oxidation conductive film pattern 26 are connected in a subsequent step. It could be connected via a guard resistor. Note that the T obtained in Embodiment 4
In the FT array substrate, Embodiment 2 and Embodiment 3
As in the case of the TFT array substrate obtained in (1), not only the guard resistor could be formed, but also there was no need to perform laser cutting during array inspection because the gate and source were not short-circuited. Further, the guard resistance shown in FIG. 9 is merely an example, and is not limited thereto, and may be of any material and any shape as long as the gate bus line 3 and the conductive film pattern 26 for anodic oxidation are connected.

Fifth Embodiment FIG. 10 is a schematic sectional view showing a method for manufacturing a guard resistor of a TFT array substrate according to a fifth embodiment of the present invention. In the figure, 1, 3,
Reference numerals 4, 7 to 9, 11, 18, and 19 are the same as those in the above-described conventional method, and reference numerals 26 and 28 are the same as those in the second embodiment. 32 is a short pattern connecting the gate bus line 3 and the conductive film pattern 26 with the same material as the gate electrode 2 and the gate bus line 3;
17 is an anodized film.

Next, a method of manufacturing the TFT array substrate according to the fifth embodiment will be described with reference to FIG. First, as the first step, a transparent glass substrate (insulating substrate)
1, an Al film or an Al alloy film, for example, Al-0.2
A low resistance metal film such as wt% Cu is formed to a thickness of about 2700 ° by a sputtering method or the like, and a gate electrode and a gate bus line 3 are formed by a photolithography method. At the same time, a conductive film pattern 26 for anodic oxidation not connected to the gate electrode or the gate bus line 3 is formed. At this time, a portion connecting the conductive film pattern for anodic oxidation and the gate bus line is etched so as to be thinner than the gate electrode and the gate bus line 3, thereby forming the short pattern 32. (FIG. 10A) By doing so, the gate bus line 3 and the anodizing conductive film pattern 26 are not short-circuited, and the guard resistance is provided between the gate bus line 3 and the anodizing conductive film pattern 26. Can be made. Also, an Al film or A
An etching solution containing phosphoric acid, acetic acid, and nitric acid as a main component is used for etching the l-alloy film, but the composition of the phosphoric acid, acetic acid, and nitric acid is appropriately selected, and the Al film or the Al alloy film is processed into a tapered shape. However, it is desirable because disconnection of the upper layer can be prevented.

Next, a resist pattern 4 for partially protecting the terminal take-out region on the gate bus line 3 is formed. Next, using the resist pattern 4 as a mask, the gate electrode and the gate bus line 3 are selectively anodized to form an anodic oxide film 17 (first insulating film) serving as a first gate insulating film or an interlayer insulating film. I do. At this time, the anodic oxide film 17, that is, the interlayer insulating film does not grow below the resist pattern 4. Therefore, a new process of removing the anodic oxide film 17 at the time of forming the wiring terminal portion is unnecessary. At this time, the short pattern 32 is also anodized. In the short pattern 32, only the desired oxide film remains, and the anodic oxidation process automatically ends when all the conductive films of the short pattern 32 become oxide films. (FIG. 10B) At this time, the gate bus line 3 and the conductive film pattern 26 for anodic oxidation are electrically opened. By doing so, an anodic oxide film can be formed on the gate electrode and the gate bus line, and the gate bus line 3 and the anodic oxidation conductive film pattern 2 can be formed in the subsequent steps.
6, a guard resistor can be formed.

Next, silicon nitride is used as the second gate insulating film 7 on the entire surface of the substrate by a plasma CVD method or the like.
Then, an a-Si film is formed at about 1200 ° and an n + a-Si film doped with an impurity having ohmic contact properties is formed at a thickness of about 300 ° using a plasma CVD method or the like. To form an a-Si film 8 and a ohmic contact n + a-Si film 9 to be semiconductor layers in the TFT portion. (FIG. 10
(C) Next, as a transparent electrode film, an ITO film is formed to a thickness of about 1000 by a sputtering method or the like, and a pixel electrode is formed by a photolithography method.

Next, the silicon nitride of the second gate insulating film is etched by dry etching to open and expose a terminal portion on the gate bus line 3. Next, in order to form a source / drain electrode and a source bus line, a Cr film capable of establishing an ohmic contact between the n + a-Si film and the ITO film of the pixel electrode is formed as a lowermost layer by a sputtering method or the like. Subsequently, a low-resistance Al-0.2 wt% Cu film is formed as an intermediate layer by about 3000.
{Circle around (5)}, and a Cr film is formed as the uppermost layer continuously for about 500 ° to form a three-layer structure. Thereafter, the three-layer film is sequentially etched by using a photolithography method to form source / drain electrodes and source bus lines.

At this time, terminal lead lines are also formed at the same time. Then, the n + a-Si film of the semiconductor layer is selectively etched by a dry etching method to form a channel portion, and then the resist is removed. Finally, TF
In order to protect T, a silicon nitride film is formed by plasma CVD.
A film was formed on the entire surface by using a method such as a method of forming a passivation film, and a desired TFT array substrate was obtained.

As described above, the method for manufacturing a thin film transistor array substrate according to the fifth embodiment is different from the method for manufacturing a thin film transistor first electrode (gate electrode 2) and thin film transistor first electrode on an insulating substrate (glass substrate 1). When forming an electrode wiring (gate bus line 3) and forming a conductive film pattern on one end side of the insulating substrate, the conductive film pattern (conductive film pattern for anodic oxidation 26) and the first electrode The portion connecting to the first wiring is etched to be thinner than the first electrode and the first electrode wiring, and the short pattern 32 connecting the first electrode and the first electrode wiring is formed. A first step of forming, a second step of forming a resist pattern 4 at a terminal extraction portion on the first electrode wiring, and a step of masking the resist pattern 4. Forming a first insulating film (anodic oxide film 17) on the first electrode and the first electrode wiring, and on the first electrode and the first electrode wiring A fourth step of forming a second insulating film (second gate insulating film 7) on the insulating substrate including: a semiconductor layer (on the first electrode via the second insulating film); a-
A fifth step of forming a Si film 8 and an ohmic contact n + a-Si film 9), a sixth step of forming a pixel electrode on the second insulating film, and a step of forming a pixel electrode on the first electrode wiring. A seventh step of etching the second insulating film of the terminal take-out portion to provide an opening 11, and forming a second electrode and a third electrode (source / drain electrode) of the thin film transistor on the semiconductor layer And an eighth step.

The T of the fifth embodiment thus obtained is
In the FT array substrate, the gate bus line 3 and the anodic oxidation conductive film pattern 26 are not short-circuited after the anodic oxidation treatment, and the gate bus line 3 and the anodic oxidation conductive film pattern 26 are connected in a subsequent step. It could be connected via a guard resistor. Note that the T obtained in Embodiment 5
In the FT array substrate, similarly to the TFT array substrate obtained in the second to fourth embodiments, not only a guard resistor can be formed but also the gate and the source are not short-circuited. Also gone. Further, the guard resistor shown in FIG. 10 is merely an example, and is not limited to this, and any material or any shape may be used as long as the gate bus line 3 and the conductive film pattern 26 for anodic oxidation are connected.

Embodiment 6 FIG. 11 is a schematic sectional view showing a method for manufacturing a guard resistor of a TFT array substrate according to Embodiment 6 of the present invention. In the figure, 1, 3,
Reference numerals 4, 7 to 9, and 11 are the same as those in the above-described conventional method, and a description thereof will be omitted. 18 is a guard resistor, 19 is a conductive film for taking out a terminal on the gate bus line, 33 is an insulating film pattern formed below a portion connecting the substrate end pattern and the gate bus line 3, and 34 is a gate bus line 3
A conductive film pattern connected to an anodic oxide film;
Reference numeral 5 denotes a substrate end pattern, and reference numeral 36 denotes a terminal leading conductive film on the substrate end pattern 35.

Next, a method of manufacturing the TFT array substrate according to the sixth embodiment will be described with reference to FIG. First, as a first step, for example, an insulating film such as silicon nitride is formed on a transparent glass substrate (insulating substrate) 1 by a plasma CVD method or the like at a thickness of about 5000 °, and a photolithography method is used to form a substrate edge. An insulating film pattern 33 is formed at a position below a portion connecting the pattern and the gate bus line. (FIG. 11A) Next, a low-resistance metal film such as Al-0.2 wt% Cu is formed to a thickness of about 2700 ° by a sputtering method or the like, and the gate electrode and the gate bus line 3 are formed by a photolithography method. To form At the same time, a conductive film pattern 34 connected to the gate electrode and the gate bus line 3 is formed. (FIG. 11 (b)) An etching solution containing phosphoric acid, acetic acid, and nitric acid as a main component is used for etching the Al film or the Al alloy film. A
It is desirable to process the 1 alloy film into a tapered shape from the viewpoint that disconnection of the upper layer can be prevented.

Next, a resist pattern 4 for partially protecting the terminal take-out region on the gate bus line 3 is formed. Next, using the resist pattern 4 as a mask, the gate electrode and the gate bus line 3 are selectively anodized,
An anodic oxide film 17 (first insulating film) to be a first gate insulating film or an interlayer insulating film is formed. At this time, an anodic oxide film, that is, an interlayer insulating film does not grow below the resist pattern 4. Therefore, a new process of removing the anodic oxide film at the time of forming the wiring terminal portion is unnecessary. At this time, the conductive film on the insulating film pattern 33 has poor step coverage, and the conductive film on the side surface of the insulating film pattern is thin. Therefore, the anodic oxidation treatment is automatically performed when all the thin conductive films become oxide films. To end. (FIG. 11C) At this point, the gate bus line 3 and the substrate end pattern 35 are formed.
Is electrically open. By doing this,
An anodic oxide film can be formed on the gate electrode and the gate bus line, and a guard resistor can be formed between the gate bus line 3 and the substrate end pattern 35 by the subsequent steps.

Next, about 3700 ° C. of silicon nitride is formed as a second gate insulating film on the entire surface by using a plasma CVD method or the like.
A film is formed, and subsequently, a
-Si film of about 1200 ° and an impurity-doped n + a-Si film of ohmic contact having a thickness of about 300 are sequentially formed.
Patterning using photolithography, T
An a-Si film 8 serving as a semiconductor layer of the FT portion and an ohmic contact n + a-Si film 9 are formed. Next, as a transparent electrode film, an ITO film was formed for about 100
Then, a pixel electrode is formed by photolithography.

Next, the silicon nitride of the second gate insulating film is etched by dry etching to open and expose a terminal portion on the gate bus line 3. Next, in order to form a source / drain electrode and a source bus line, a Cr film capable of establishing an ohmic contact between the n + a-Si film and the ITO film of the pixel electrode is formed as a lowermost layer by a sputtering method or the like. Subsequently, a low-resistance Al-0.2 wt% Cu film is formed as an intermediate layer by about 3000.
{Circle around (5)}, and a Cr film is formed as the uppermost layer continuously for about 500 ° to form a three-layer structure. Thereafter, the three-layer film is sequentially etched by using a photolithography method to form source / drain electrodes and source bus lines.

At this time, terminal lead lines are also formed at the same time. Subsequently, the n + a-Si film of the semiconductor layer is selectively etched by a dry etching method to form a channel portion, and then the resist is removed. Finally, TF
In order to protect T, a silicon nitride film is formed by plasma CVD.
A film was formed on the entire surface by using a method such as a method of forming a passivation film, and a desired TFT array substrate was obtained.

As described above, the manufacturing method of the thin film transistor array substrate according to the sixth embodiment is different from the method of manufacturing the thin film transistor array substrate according to the sixth embodiment in that the first electrode (gate electrode 2) of the thin film transistor and the first electrode Of the electrode (gate bus line 3) of
Before forming the conductive film pattern 34 connected to the first electrode and the first electrode wiring on one end side of the insulating substrate, the conductive film pattern formed on one end side of the insulating substrate A first step of forming an insulating film pattern 33 at a position below a portion connecting the first electrode wiring and the first electrode wiring; and forming the insulating film pattern 33 on the insulating substrate on which the insulating film pattern 33 is formed. A second step of forming a first electrode and a first electrode wiring, and forming the conductive film pattern on the one end side of the insulating substrate; and taking out terminals on the first electrode wiring. A third step of forming a resist pattern 4 in the portion, and forming a first insulating film (anodic oxide film 17) on the first electrode and the first electrode wiring using the resist pattern 4 as a mask. The fourth step and the first A fifth step of forming a second insulating film on the insulating substrate including the electrode and the first electrode wiring; and forming the second insulating film (the second gate) on the first electrode. A sixth step of forming a semiconductor layer (a-Si film 8 and ohmic contact n + a-Si film 9) via an insulating film 7), and a seventh step of forming a pixel electrode on the second insulating film. An eighth step of etching the second insulating film of the terminal lead-out portion on the first electrode wiring to provide an opening 11, and forming a second electrode of the thin film transistor on the semiconductor layer and a A ninth step of forming three electrodes (source / drain electrodes).

The T of Embodiment 6 thus obtained is
In the FT array substrate, there is no short circuit between the gate bus line 3 and the substrate end pattern 35 after the anodizing treatment, and the gate bus line 3 and the substrate end pattern 35 are connected via a guard resistor in a subsequent step. I was able to. In the TFT array substrate obtained in the sixth embodiment, similarly to the TFT array substrates obtained in the second to fifth embodiments, not only a guard resistor can be formed, but also the gate and the source are short-circuited. No need for laser cutting during array inspection. Further, the guard resistor shown in FIG. 11 is merely an example, and is not limited to this, and any material and any shape may be used as long as the gate bus line 3 and the substrate end pattern 35 are connected.

Embodiment 7 FIG. A TFT array substrate formed by the same method as in the first to sixth embodiments,
After forming an alignment film on the surface of a counter substrate on which a light-shielding layer, an overcoat layer and a counter electrode are formed on another transparent insulating substrate, the alignment film is opposed to the surface. A liquid crystal panel is formed by disposing a polarizing plate outside the TFT array substrate and the opposite substrate.
According to the present embodiment, the gate electrode 2 and the gate bus line 3 are formed using a material having a low specific resistance, and an anodic oxide film is formed on the surfaces of the gate electrode 2 and the gate bus line 3 to form a gate. A liquid crystal display device having a high aperture ratio by reducing the thickness of the electrodes 2 and the gate bus lines 3 and reducing display unevenness due to crosstalk can be obtained. In the first to seventh embodiments,
Although the a-Si film is used as the semiconductor layer, the present invention is not limited to this. For example, a polycrystalline Si film may be used.

[0071]

As described above, according to the method for manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate. At the same time, a short pattern electrically connected to the first electrode and the first electrode wiring is formed on one end of the insulating substrate, and the other end is connected to the short pattern. A first step of forming a conductive film pattern not connected to the first electrode or the first electrode wiring, and a second step of forming a resist pattern at a terminal extraction portion on the first electrode wiring. And the step of forming the short pattern in the chemical conversion solution and the step of forming the conductive film pattern on the surface of the chemical conversion solution, and disposing the insulating substrate. A third step of forming a first insulating film on the first electrode and on the first electrode wiring and on the short pattern in the chemical conversion solution using a mask as a mask, And a fourth step of forming a second insulating film on the insulating substrate including on the first electrode wiring, and a semiconductor layer of a thin film transistor on the first electrode via the second insulating film A fifth step of forming a pixel electrode on the second insulating film, and etching the second insulating film of the terminal extraction portion on the first electrode wiring And the eighth step of forming the second electrode and the third electrode of the thin film transistor on the semiconductor layer, so that the first electrode wiring and the substrate It is possible to form a guard resistor between the end conductive film pattern and There is an effect that it is possible to prevent the thin film transistor by electrostatic even after a short pattern and the gate bus line for anodic oxidation was cut with a laser during ray examination is destroyed.

According to the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are simultaneously formed on the insulating substrate. A first step of forming a conductive film pattern not connected to the first electrode and the first electrode wiring on one end side of
A material which is different from the material of the first electrode and which does not melt during the anodic oxidation treatment of the first electrode and the first electrode wiring, and can be etched with an etchant having a selectivity with the anodic oxide film. A second step of forming a short pattern so as to connect the conductive film pattern and the first electrode wiring, and forming a resist pattern at a terminal extraction portion on the first electrode wiring. A third step, a fourth step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask, and a material different from the first electrode material. A fifth step of etching the short pattern formed in, and a sixth step of forming a second insulating film on the insulating substrate including on the first electrode and the first electrode wiring, ,
A seventh step of forming a semiconductor layer on the first electrode with a second insulating film therebetween, an eighth step of forming a pixel electrode on the second insulating film, and the first electrode A ninth step of providing an opening by etching a second insulating film of a terminal extraction part on a wiring for use, and a tenth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer After the anodizing treatment, there is no short circuit between the first electrode wiring (gate bus line) and the conductive film pattern at the end of the substrate, and a guard resistor is formed in a subsequent step. Since these can be connected, it is not necessary to cut the short-circuit pattern for anodic oxidation at the substrate end and the wiring for the first electrode with a laser at the time of array inspection, thereby reducing the number of manufacturing steps and reducing the gate bus. Line and source bus line Since connected via the over de resistance, there is an effect that it is possible to prevent the thin film transistor is destroyed by static electricity during the manufacturing process.

According to the method of manufacturing a thin film transistor array substrate of the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are simultaneously formed on the insulating substrate. A first step of forming a conductive film pattern not connected to the first electrode or the first electrode wiring on one end side of the first electrode material, and a material different from the first electrode material, The electrode and the first electrode wiring are not melted during the anodic oxidation treatment, and the anodic oxide film and the first electrode material are etched using an etchant having a selectivity with the material. A second step of forming a short pattern so as to connect to one electrode wiring, and forming a contact pattern also in a terminal extraction portion on the first electrode wiring; A third step of forming a first insulating film on the first electrode and the first electrode wiring using a contact pattern as a mask, and the first electrode is formed of a material different from the material of the first electrode. A fourth step of etching the short pattern and the contact pattern, and a fifth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring, A sixth step of forming a semiconductor layer on the first electrode via the second insulating film, a seventh step of forming a pixel electrode on the second insulating film, Eighth step of providing an opening by etching the second insulating film of the terminal extraction portion on the electrode wiring, and ninth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer Anodizing treatment Since there is no short circuit between the first electrode wiring (gate bus line) and the conductive film pattern at the end of the substrate, a guard resistor can be formed and connected in a subsequent step, so that an array inspection can be performed. Sometimes it is not necessary to cut the short pattern for anodizing at the substrate end and the wiring for the first electrode with a laser, thereby reducing the number of manufacturing steps, and connecting the gate bus lines and source bus lines via guard resistors. Since the connection is established, there is an effect that the thin film transistor can be prevented from being damaged by static electricity during the manufacturing process. further,
Since the contact pattern can be formed simultaneously with the short pattern in the second step, the number of steps can be reduced.

According to the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are simultaneously formed on the insulating substrate. A first step of forming a conductive film pattern that is not connected to the first electrode and the first electrode wiring on one end side; and the same material as the first electrode material, wherein the conductive film pattern And a second step of forming a short pattern with a smaller thickness than the first electrode and the first electrode wiring so as to connect the first electrode wiring and the first electrode wiring, A third step of forming a resist pattern at a terminal extraction portion on the wiring, and forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask. And a fifth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring, and the second step on the first electrode A sixth step of forming a semiconductor layer via the insulating film, a seventh step of forming a pixel electrode on the second insulating film, and a step of extracting a terminal on the first electrode wiring. An anodic oxidation treatment by having an eighth step of providing an opening by etching the second insulating film and a ninth step of forming a second electrode and a third electrode on the semiconductor layer; Thereafter, there is no short circuit between the first electrode wiring (gate bus line) and the conductive film pattern at the end of the substrate, and a guard resistor can be formed in a subsequent step to connect them. During inspection, the short pattern for anodic oxidation on the substrate edge and the wiring for the first electrode are It is not necessary to cross, it is possible to reduce the number of steps during production,
Since the gate bus line and the source bus line are connected via the guard resistor, there is an effect that the thin film transistor can be prevented from being damaged by static electricity during the manufacturing process.

According to the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate, and one end of the insulating substrate is formed. When a conductive film pattern is formed on the side, a portion connecting the conductive film pattern and the first electrode wiring is etched so as to be thinner than the first electrode and the first electrode wiring. A first step of forming a short pattern connecting the first electrode and the first electrode wiring, and a second step of forming a resist pattern at a terminal extraction portion on the first electrode wiring And a third step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask, and on the first electrode and A fourth step of forming a second insulating film on the insulating substrate including on one electrode wiring, and forming a semiconductor layer on the first electrode with the second insulating film interposed therebetween. Fifth step, a sixth step of forming a pixel electrode on the second insulating film, and etching the second insulating film of the terminal extraction portion on the first electrode wiring to form an opening. Since the method includes the seventh step of providing and the eighth step of forming the second electrode and the third electrode of the thin film transistor on the semiconductor layer, the first electrode wiring (gate) There is no short circuit between the bus line) and the conductive film pattern at the end of the substrate, and a guard resistor can be formed and connected in a subsequent process. And the first electrode wiring need not be cut with a laser. In addition, the number of manufacturing steps can be reduced, and the gate bus line and the source bus line are connected via guard resistors, so that the thin film transistor can be prevented from being damaged by static electricity during the manufacturing process. There is.

According to the method of manufacturing a thin film transistor array substrate according to the present invention, the first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate, and the insulating substrate is formed. Before forming a conductive film pattern connected to the first electrode and the first electrode wiring on one end side, the conductive film pattern formed on one end side of the insulating substrate and the first electrode A first step of forming an insulating film pattern at a position below a portion connected to a wiring for use, and the first electrode and the first electrode on the insulating substrate on which the insulating film pattern is formed. A second step of forming the conductive film pattern on the one end side of the insulating substrate, and forming a resist pattern on a terminal extraction portion on the first electrode wiring. A third step of forming a fourth step of forming a first insulating film on the resist pattern above the first electrode as a mask and the first upper electrode wiring,
A fifth step of forming a second insulating film on the insulating substrate including the first electrode and the first electrode wiring,
A sixth step of forming a semiconductor layer on the first electrode via the second insulating film, a seventh step of forming a pixel electrode on the second insulating film, Eighth step of providing an opening by etching the second insulating film of the terminal extraction part on the electrode wiring, and ninth step of forming a second electrode and a third electrode of a thin film transistor on the semiconductor layer After the anodizing treatment, there is no short circuit between the first electrode wiring (gate bus line) and the conductive film pattern at the substrate end, and a guard resistor is formed in the subsequent steps Since these can be connected, it is not necessary to cut the short-circuit pattern for anodic oxidation at the substrate end and the wiring for the first electrode with a laser at the time of array inspection, and the number of steps during manufacturing can be reduced. Gate bus line and source bus Since Inn is connected through a guard resistor, there is an effect that it is possible to prevent the thin film transistor is destroyed by static electricity during the manufacturing process.

Further, according to the method of manufacturing a thin film transistor array substrate according to the present invention, anodization is performed on the first electrode and the first electrode wiring using the resist pattern or the conductive film pattern for protecting the terminal extraction region as a mask. As a result, the anodic oxide film does not grow under the resist pattern or the conductive film pattern for protecting the terminal take-out region. Therefore, the step of removing the anodic oxide film when forming the wiring terminals is performed. This has the effect that it is no longer necessary.

According to the method for manufacturing a thin film transistor array substrate of the present invention, the first electrode and the first electrode wiring are formed by using Al or an alloy containing Al as a main component. The width can be reduced, and a liquid crystal display device having a high aperture ratio can be realized by using a thin film transistor array substrate manufactured by this manufacturing method. In addition, when Al having a low wiring resistance is used, signal delay is eliminated, so that display unevenness due to crosstalk can be reduced.

According to a liquid crystal display device of the present invention, a thin film transistor array substrate formed by the manufacturing method according to any one of claims 1 to 8, and a liquid crystal material sandwiched between the thin film transistor array substrate and the thin film transistor array substrate. Since the counter substrate is provided, there is an effect that a destruction due to static electricity during a manufacturing process can be prevented, and a liquid crystal display device that can easily perform an array inspection can be realized. Further, there is an effect that a high-quality liquid crystal display device having a high aperture ratio and reduced display unevenness due to crosstalk can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a method for manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a first half of a method for manufacturing a guard resistor of a thin film transistor array substrate according to the first embodiment of the present invention;

FIG. 3 is a schematic plan view showing the latter half of the method of manufacturing the guard resistor of the thin film transistor array substrate according to the first embodiment of the present invention;

FIG. 4 is a schematic sectional view illustrating a method for manufacturing a guard resistor of the thin film transistor array substrate according to the first embodiment of the present invention.

FIG. 5 is a schematic plan view of a principal part showing the first half of a method of manufacturing a guard resistor of a thin film transistor array substrate according to Embodiment 2 of the present invention;

FIG. 6 is a schematic plan view of an essential part showing an intermediate stage of a method for manufacturing a guard resistor of a thin film transistor array substrate according to Embodiment 2 of the present invention;

FIG. 7 is a schematic plan view of a principal part showing a latter half of a method for manufacturing a guard resistor of a thin film transistor array substrate according to Embodiment 2 of the present invention;

FIG. 8 is a schematic sectional view illustrating a method for manufacturing a thin film transistor array substrate according to a third embodiment of the present invention.

FIG. 9 is a schematic sectional view illustrating a method for manufacturing a guard resistor of a thin film transistor array substrate according to a fourth embodiment of the present invention.

FIG. 10 is a schematic sectional view illustrating a method for manufacturing a guard resistor of a thin film transistor array substrate according to a fifth embodiment of the present invention.

FIG. 11 is a schematic sectional view illustrating a method for manufacturing a guard resistor of a thin film transistor array substrate according to a sixth embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view illustrating a method for manufacturing a conventional thin film transistor array substrate.

FIG. 13 is a schematic plan view (first half stage) of a portion of a conventional thin film transistor array substrate where a guard resistor should be originally formed.

FIG. 14 is a schematic plan view (second half stage) of a portion of a conventional thin film transistor array substrate where a guard resistor should be formed.

FIG. 15 is a schematic cross-sectional view of a portion of a conventional thin film transistor array substrate where a guard resistor should be formed.

[Explanation of symbols]

Reference Signs List 1 glass substrate (insulating substrate) 2 gate electrode (first electrode) 3 gate bus line 4 resist pattern 5 first gate insulating film 6 interlayer insulating film 7 second gate insulating film 8 a-Si film 9 n + a-Si film 10 pixel electrode 11 terminal lead-out opening 12 source / drain electrode 13 terminal lead-out line 14 channel part 15 passivation film 16 anodizing short pattern 17 anodic oxide film 18 guard resistor 19 terminal lead-out conductive film 20 terminal lead-out conductive film Reference Signs List 22 conductive film pattern for anodic oxidation 23 guard resistance forming part 24 laser cut part 25 terminal taking out part 26 conductive film pattern for anodic oxidation 27 short pattern 28 terminal taking out conductive film 29 source short pattern 30 conductive film pattern for protecting terminal taking out area 31 Short pattern 2 short pattern 33 insulating film pattern 34 conductive pattern 35 conductive extraction substrate edge pattern 36 pin

Claims (9)

[Claims] At the same time as forming a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor on an insulating substrate, it is electrically connected to the first electrode and the wiring for the first electrode. A conductive pattern is formed on one end of the insulating substrate and connected to the short pattern at the other end but not connected to the first electrode and the first electrode wiring. A first step of forming a film pattern; a second step of forming a resist pattern at a terminal take-out portion on the first electrode wiring; The insulating substrate is arranged so that the side on which the membrane pattern is formed is on the surface of the chemical conversion solution, and the resist pattern is used as a mask on the first electrode and the first electrode wiring and on the first electrode. A third step of forming a first insulating film on the short pattern in a liquid, and a second insulating film on the insulating substrate including the first electrode and the first electrode wiring A fourth step of forming; a fifth step of forming a semiconductor layer of a thin film transistor on the first electrode via the second insulating film; and forming a pixel electrode on the second insulating film. A sixth step of: etching a second insulating film of a terminal extraction portion on the first electrode wiring to provide an opening; and a second step of forming a thin film transistor on the semiconductor layer. An eighth step of forming an electrode and a third electrode. 2. The first electrode of the thin film transistor and the wiring for the first electrode of the thin film transistor are formed on the insulating substrate, and the first electrode and the first electrode are formed on one end side of the insulating substrate. A first step of forming a conductive film pattern that is not connected to the first wiring; and an anodic oxidation of the first electrode and the first electrode wiring, which is a different material from the material of the first electrode. A second step of forming a short pattern so as to connect the conductive film pattern and the first electrode wiring by using a material which does not melt during the process and can be etched with an etchant having a selectivity with the anodic oxide film; A third step of forming a resist pattern at a terminal extraction portion on the first electrode wiring; and forming a first resist pattern on the first electrode and the first electrode wiring using the resist pattern as a mask. A fourth step of forming an insulating film, a fifth step of etching the short pattern formed of a material different from the first electrode material, and a wiring on the first electrode and a first electrode A sixth step of forming a second insulating film on the insulating substrate including the above, a seventh step of forming a semiconductor layer on the first electrode via a second insulating film, An eighth step of forming a pixel electrode on the second insulating film, a ninth step of etching the second insulating film of the terminal lead-out portion on the first electrode wiring to provide an opening, A tenth step of forming a second electrode and a third electrode of the thin film transistor on the semiconductor layer. 3. A method for forming a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor on an insulative substrate and simultaneously forming the first electrode and the first electrode on one end of the insulative substrate. A first step of forming a conductive film pattern not connected to the first wiring, and a material different from the first electrode material, wherein the first electrode and the first electrode wiring are being anodized. Using a material that does not dissolve in and can be etched with an anodized film and an etchant having a selectivity with the first electrode material, a short pattern is formed to connect the conductive film pattern and the first electrode wiring. A second step of forming and forming a contact pattern also in a terminal extraction portion on the first electrode wiring; and forming a contact pattern on the first electrode and the first electrode using the contact pattern as a mask. A third step of forming a first insulating film on the wiring, a fourth step of etching the short pattern and the contact pattern formed of a material different from the material of the first electrode, A fifth step of forming a second insulating film on an insulating substrate including on one electrode and a wiring for the first electrode; and forming a semiconductor on the first electrode via the second insulating film. A sixth step of forming a layer; a seventh step of forming a pixel electrode on the second insulating film; and etching the second insulating film of a terminal extraction portion on the first electrode wiring. And a ninth step of forming a second electrode and a third electrode of the thin film transistor on the semiconductor layer. 9. A method of manufacturing a thin film transistor array substrate, comprising: 4. A method for forming a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor on an insulating substrate, and simultaneously forming the first electrode and the first electrode on one end side of the insulating substrate. A first step of forming a conductive film pattern that is not connected to the wiring, and the same material as the first electrode material, so that the conductive film pattern is connected to the first electrode wiring. A second step of forming a short pattern with a smaller film thickness than the first electrode and the first electrode wiring, and a third step of forming a resist pattern at a terminal extraction portion on the first electrode wiring A fourth step of forming a first insulating film on the first electrode and the first electrode wiring using the resist pattern as a mask; and a fourth step on the first electrode and the first electrode. Above including wiring A fifth step of forming a second insulating film on the edge substrate, a sixth step of forming a semiconductor layer on the first electrode via the second insulating film, A seventh step of forming a pixel electrode on the insulating film, an eighth step of etching the second insulating film of the terminal lead-out portion on the first electrode wiring to provide an opening, and Ninth step of forming a second electrode and a third electrode on the layer. 5. A method for forming a first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor on an insulating substrate, and forming a conductive film pattern on one end side of the insulating substrate. The portion connecting the pattern and the first electrode wiring is etched so as to be thinner than the first electrode and the first electrode wiring, and the first electrode and the first electrode wiring are etched. A second step of forming a resist pattern at a terminal extraction portion on the first electrode wiring; and a second step of forming a resist pattern at a terminal extraction portion on the first electrode wiring. And a third step of forming a first insulating film on the first electrode wiring, and a second insulating film on the insulating substrate including the first electrode and the first electrode wiring Form A fourth step, a fifth step of forming a semiconductor layer on the first electrode via the second insulating film, and a sixth step of forming a pixel electrode on the second insulating film A seventh step of etching the second insulating film of the terminal lead-out portion on the first electrode wiring to provide an opening; and a second electrode and a third electrode of a thin film transistor on the semiconductor layer. And an eighth step of forming an electrode. 6. A first electrode of a thin film transistor and a wiring for a first electrode of the thin film transistor are formed on an insulating substrate, and the first electrode and the first electrode for the first electrode are formed on one end side of the insulating substrate. Before forming the conductive film pattern connected to the wiring, at a position below the portion connecting the conductive film pattern formed on one end side of the insulating substrate and the first electrode wiring, A first step of forming an insulating film pattern; forming the first electrode and the first electrode wiring on the insulating substrate on which the insulating film pattern is formed; and forming the one end of the insulating substrate. A second step of forming the conductive film pattern on the side; a third step of forming a resist pattern at a terminal extraction portion on the first electrode wiring; and a first step of using the resist pattern as a mask. A fourth step of forming a first insulating film on the first electrode and the first electrode wiring, and a second step on the insulating substrate including the first electrode and the first electrode wiring. A fifth step of forming an insulating film, a sixth step of forming a semiconductor layer on the first electrode via the second insulating film, and forming a pixel electrode on the second insulating film. A seventh step of forming, an eighth step of etching the second insulating film of a terminal extraction portion on the first electrode wiring to provide an opening, and a second step of forming a thin film transistor on the semiconductor layer. And a ninth step of forming an electrode and a third electrode. 7. The method for manufacturing a thin film transistor array substrate according to claim 1, wherein the first insulating film is formed by anodic oxidation. 8. The first electrode and the first electrode wiring,
The method for manufacturing a thin film transistor array substrate according to any one of claims 1 to 7, wherein the method is formed using Al or an alloy containing Al as a main component. 9. A thin film transistor array substrate formed by the method according to claim 1, and a counter substrate having a counter electrode sandwiching a liquid crystal material together with the thin film transistor array substrate. A liquid crystal display device characterized by the above-mentioned.