JP2000035592A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the disconnection of lower layer metallic wiring and to provide a liquid crystal display device having high reliability and high aperture ratio by forming a plurality of apertures in the lower layer metallic wiring of portions which are the contact regions of terminal parts. SOLUTION: After a metallic film having small specific resistance is deposited by a sputtering method, etc., on the surface of a transparent insulating substrate 1, this metallic film is patterned by using a resist formed by a photomechanical process, by which gate electrodes and the lower layer metallic wiring are formed. At this time, a plurality of the apertures 22 of a rectangular shape are randomly formed at the lower layer metallic wiring 3 of the portion which is the contact region 21 of the terminal part 20. The expansion of the etched regions is suppressed by the apertures 22 formed in the lower layer metallic wiring 3 and the disconnection of the lower layer metallic wiring 3 may be prevented even if an etchant penetrates through the film defect parts of the gate insulating film in the contact region 21 of the terminal part 20 and etches the lower layer metallic wiring 3 consisting of Al or Al alloy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a thin film transistor (hereinafter, referred to as TFT).
The present invention relates to an active matrix type liquid crystal display device in which is mounted as a switching element.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional T having a low resistance signal wiring.
It is sectional drawing which shows the manufacturing process of the TFT part and terminal part of the TFT array board which mounted TFT of FT type liquid crystal display device. In the figure, 1 is a transparent insulating substrate such as a glass substrate,
Reference numeral 2 denotes a gate electrode formed on a transparent insulating substrate 1 and made of a low-resistance metal such as Al or an Al alloy. Reference numeral 3 denotes a lower metal wiring extending from the gate electrode 2, and reference numeral 4 denotes a lower metal wiring. Resist patterns 5 and 6 formed for protecting the terminal extraction region are anodic oxide films formed on the surfaces of the gate electrode 2 and the lower metal wiring 3, and the resist pattern 4 on the lower metal wiring 3 was formed. No anodic oxide film 6 is formed in the region. 7 is an anodic oxide film 5, 6
A gate insulating film made of a silicon nitride film formed on the entire surface of the gate electrode 2 on which is formed and the lower metal wiring 3;
Reference numeral 8 denotes a semiconductor layer made of an amorphous silicon film formed on the gate electrode 2 via the gate insulating film 7, 9 denotes a contact layer made of an n ⁺ type amorphous silicon film formed on the semiconductor layer 8, and 10 denotes an ITO film A contact hole for taking out a terminal formed in the gate insulating film 7 on the lower metal wiring 3; a source / drain electrode 12 formed on the contact layer 9; and a source / drain electrode 12 A terminal lead-out wiring formed at the same time as the formation, 14 is a channel portion formed by selectively etching the contact layer 9, and 15 is a passivation film formed so as to cover the above components.

FIG. 8 is a schematic plan view showing a TFT array substrate of the conventional TFT type liquid crystal display device shown in FIG. 7, FIG. 9 is a plan view showing an enlarged terminal portion of FIG. 8, and FIGS. It is a top view which shows the manufacturing process of the terminal part of FIG. In the figure, 1
Reference numeral 6 denotes a display unit in which TFTs and pixel electrodes are arranged in a matrix, 17 denotes a gate terminal, 18 denotes a source terminal, 1
9 is a short pattern for anodic oxidation, 20 is a gate terminal 1
7 or a terminal portion which shows the source terminal 18 in an enlarged manner, 21
Reference numeral denotes a contact region formed in the terminal portion 20, which is a contact portion between the lower metal wiring 3 and the terminal extraction wiring 13 through the terminal extraction contact hole 11 formed in the gate insulating film 7 in FIG.

Next, a conventional method for manufacturing a TFT array substrate on which TFTs are mounted will be described with reference to FIGS. 7, 10 and 11. FIG. First, as shown in FIG. 7A, a single-layer film made of a metal having a low specific resistance such as Al or an Al alloy is formed on the transparent insulating substrate 1 and then patterned using a resist to form the gate electrode 2. And the lower metal wiring 3 is formed. Next, as shown in FIG. 7B and FIG. 10A, after forming a resist pattern 4 to protect a terminal extraction region on the lower metal wiring 3, the resist pattern 4 is formed.
The anodic oxide films 5 and 6 are formed by selectively performing anodizing on the surface layers of the gate electrode 2 and the lower metal wiring 3 which are not covered by the above. Next, after removing the resist pattern 4, a silicon nitride film, an amorphous silicon film, and an n ⁺ type amorphous silicon film which are to be the gate insulating film 7 are sequentially formed by the plasma CVD method, and then the amorphous silicon film and n ^{The +} type amorphous silicon film is patterned to form a semiconductor layer 8 and a contact layer 9 in the TFT section above the gate electrode 2 (FIG. 7).
(C), FIG. 10 (b)).

[0007] Next, as shown in FIGS. 7D and 10C, after forming an ITO film, it is patterned by using a resist to form a pixel electrode 10. Next, FIG.
As shown in FIG. 10E and FIG. 10D, the gate insulating film 7 in the terminal extraction region is etched to form a contact hole 11 for terminal extraction. Next, FIG.
As shown in FIG. 11A, after forming a film of Cr or the like, patterning is performed using a resist to form source / drain electrodes 12 and terminal extraction wirings 13. At this time, the terminal extraction wiring 13 is connected to the contact hole 11.
Is electrically connected to the lower metal wiring 3 via. Then, the source / drain electrodes 1 are formed by dry etching.
The n ⁺ -type amorphous silicon film (contact layer 9) in the portion not covered with 2 is etched to form a channel portion 14.
To form Finally, as shown in FIGS. 7G and 11B, a passivation film 15 made of a silicon nitride film or the like is formed to protect the TFT portion.

[0006]

As described above, in the TFT array substrate of the conventional TFT type liquid crystal display device,
In order to miniaturize the scanning wiring (gate bus line) to obtain a liquid crystal display device with a high aperture ratio, a low-resistance signal wiring formed using a material mainly containing Al having a small specific resistance is used. Al or an Al alloy constituting the low-resistance signal wiring has poor chemical resistance, and when the pixel electrode 10 is formed (FIG. 7).
10D and FIG. 10C), since the lower metal wiring 3 of the contact region 21 of the terminal portion 20 is only covered with the gate insulating film 7, the gate insulating film 7 has a film defect such as a pinhole. When there is a portion, the etching solution used for patterning the ITO film forming the pixel electrode 10 is
As shown in FIG. 12, the permeation penetrates through the film defect portion of the gate insulating film 7 to form a corroded region 23 in the lower metal wire 3 made of Al or Al alloy in the contact region 21 of the terminal portion 20, and the lower metal wire 3 is Disconnect or lower metal wiring 3
There is a problem that the contact between the terminal and the terminal extraction wiring 13 is obstructed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the scanning wiring (gate bus line) is made of a material having a small specific resistance.
It is an object of the present invention to provide a highly reliable liquid crystal display device having a high aperture ratio by preventing disconnection of a lower metal wiring formed using a material having a low specific resistance at a terminal portion of an FT array substrate.

[0008]

A liquid crystal display device according to the present invention comprises a transparent insulating substrate, switching elements arranged in a matrix at the center of the transparent insulating substrate, and electrically connected to the switching elements. A display section comprising a pixel electrode and a scanning line (gate bus line) and a signal line (source bus line) formed around the pixel electrode; and a lower metal line around the display section on the transparent insulating substrate. A first substrate having a lower metal wiring and a terminal portion including a contact region to which an upper metal wiring formed via an insulating film is connected via a contact hole; and a liquid crystal material sandwiched between the first substrate and the first substrate. Comprising a second substrate,
A plurality of openings are formed in a lower metal wiring portion which is to be a contact region of the terminal portion.

In addition, a plurality of openings formed in the lower metal wiring at a portion to be a contact region of the terminal portion are randomly arranged. Further, the plurality of openings formed in the lower metal wiring in the portion to be the contact region of the terminal portion are arranged in several rows in a direction intersecting the direction in which the terminal portion is disconnected. Also, the plurality of openings formed in the lower metal wiring in a portion to be the contact region of the terminal portion have a slit shape having a length longer than the length of the contact region, and a direction intersecting the direction in which the terminal portion is disconnected. Are arranged. The lower metal wiring of the terminal portion is formed of Al or an alloy containing Al as a main component.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process of a TFT portion and a terminal portion of a TFT array substrate of a liquid crystal display according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a transparent insulating substrate such as a glass substrate, and 2 denotes A formed on the transparent insulating substrate 1.
a gate electrode made of a low-resistance metal such as l or Al alloy;
Reference numeral 3 denotes a lower metal wiring extending from the gate electrode 2, 4 denotes a resist pattern formed to protect a terminal extraction region on the lower metal wiring 3, and 5 and 6 denote gate electrodes 2 and the lower metal wiring 3 The anodic oxide film 6 is not formed in the region where the resist pattern 4 is formed on the lower metal wiring 3 in the anodic oxide film formed on the surface of the substrate. Reference numeral 7 denotes a gate insulating film made of a silicon nitride film formed over the entire surface of the gate electrode 2 on which the anodic oxide films 5 and 6 are formed and the lower metal wiring 3, and 8 denotes a gate insulating film above the gate electrode 2 via the gate insulating film 7. A semiconductor layer 9 made of an amorphous silicon film or the like formed on the semiconductor layer 9; a contact layer 9 made of an n ⁺ type amorphous silicon film formed on the semiconductor layer 8;
A pixel electrode composed of a TO film, 11 is a contact hole for taking out a terminal formed in the gate insulating film 7 on the lower metal wiring 3, and 12 is a source electrode formed on the contact layer 9.
A drain electrode 13, a terminal lead-out line formed simultaneously with the formation of the source / drain electrode 12, a channel portion 14 formed by selectively etching the contact layer 9,
Reference numeral 15 denotes a passivation film formed so as to cover the above components.

FIG. 2 shows the TFT of the liquid crystal display device shown in FIG.
FIG. 3 is an enlarged plan view of the terminal portion of FIG. 2, FIG. 3A is a schematic plan view of the terminal portion, and FIG. 3B is an enlarged plan view of a lower metal wiring constituting the terminal portion. . In the drawing, reference numeral 16 denotes a display portion in which TFTs and pixel electrodes are arranged in a matrix, 17 denotes a gate terminal, 18 denotes a source terminal, 19 denotes a short pattern for anodic oxidation, and 20 denotes a gate terminal 17 or a source terminal 18. Terminal portions 21 shown in FIG. 2 are contact regions formed in the terminal portions 20;
This is a contact portion between the lower metal wiring 3 and the terminal extraction wiring 13 via the terminal extraction contact hole 11 formed in the gate insulating film 7 in FIG. 22
Is an opening formed in the lower metal wiring 3 of the terminal portion 20.

Next, a method of manufacturing the TFT array substrate of the liquid crystal display according to the present embodiment will be described. First, FIG.
As shown in (a), the surface of the transparent insulating substrate 1 is made of Al containing, for example, 0.2% by weight of Cu (hereinafter referred to as Al-0.2).
After a metal film having a low specific resistance such as a film is formed to a thickness of about 270 nm by a sputtering method or the like, patterning is performed using a resist formed by a photoengraving method, and the gate electrode 2 and the lower metal wiring 3 are formed. Form. At this time, as shown in FIG. 3 (b), a plurality of rectangular openings 22 are formed at random in the lower metal wiring 3 in a portion to be the contact region 21 of the terminal portion 20. An etching solution containing phosphoric acid, acetic acid, and nitric acid as main components is used for etching the Al film. However, the composition of phosphoric acid, acetic acid, and nitric acid is examined in advance, and the etching end surface of the Al film is formed into a tapered shape. In addition, the coatability of a film formed as an upper layer can be improved.

Next, after a resist pattern 4 is formed to protect a terminal extraction region on the lower metal wiring 3,
Using the short pattern 19 electrically short-circuited with the gate electrode 2 and the lower metal wiring 3, a portion of the gate electrode 2 and the lower metal wiring 3 not covered with the resist pattern 4 is used.
Is selectively anodized to form anodized films 5 and 6 (FIG. 1B). At this time, since the anodic oxide film is not formed on the portion covered with the resist pattern 4, a step of removing the anodic oxide film in the terminal take-out region is not required in a later step. After that, the resist pattern 4 is removed.

Next, a silicon nitride film to be the gate insulating film 7 is about 370 nm, an amorphous silicon film is about 120 nm, and n
^{After a +} -type amorphous silicon film is sequentially formed to a thickness of about 30 nm, the amorphous silicon film and the n ⁺ -type amorphous silicon film are simultaneously patterned using a resist formed by photolithography, and a TF is formed above the gate electrode 2.
A semiconductor layer 8 and a contact layer 9 in a T portion are formed (FIG. 1C). Next, as shown in FIG. 1D, an ITO film as a transparent conductive film is formed to a thickness of about 100 nm by a sputtering method or the like, and then patterned using a resist formed by a photolithography method to form a pixel electrode 10. . Next, FIG.
As shown in (e), the gate insulating film 7 in the terminal take-out region is etched by a dry etching method to form a contact hole 11 for taking out a terminal.

Next, as shown in FIG.
Drain electrode 12 and source bus line (not shown)
First, a Cr film having good ohmic contact with an n ⁺ -type amorphous silicon film forming the contact layer 9 and an ITO film forming the pixel electrode 10 at the lowermost layer is formed to a thickness of about 100 nm by sputtering or the like. Al-0.2wt% Cu film with low specific resistance about 300n
m, a three-layer film is formed by continuously forming a Cr film on the uppermost layer by about 50 nm. Next, the three-layer film is sequentially patterned using a resist formed by a photoengraving method, and the source / drain electrodes 1 are formed.
2 and the terminal extraction wiring 13 are formed. At this time,
The terminal extraction wiring (upper metal wiring) 13 is electrically connected to the lower metal wiring 3 through the terminal extraction contact hole 11. Subsequently, n ^{+ of the} portion not covered by the source / drain electrode 12 by dry etching
The channel portion 14 is formed by etching the type amorphous silicon film (contact layer 9).

Finally, as shown in FIG.
In order to protect the portion, a silicon nitride film is formed to a thickness of about 500 nm by a plasma CVD method or the like.
5 is formed. After forming an alignment film on the surface of the TFT array substrate formed by the above process and the surface of the opposing substrate on which a light-shielding film, an opposing electrode, etc. are formed on another transparent insulating substrate, the liquid crystal material is injected therebetween. A liquid crystal display device is formed by enclosing with a sealing material.

The TFT of the liquid crystal display according to the present embodiment
In the array substrate, when the pixel electrode 10 is formed, an etchant used for patterning the ITO film forming the pixel electrode 10 causes a film defect of the gate insulating film 7 in the contact region 21 of the terminal portion 20 as shown in FIG. When the lower metal wiring 3 made of Al or an Al alloy is corroded and penetrated through the portion, the corrosion area 23 can be prevented from being enlarged by the opening 22 formed in the lower metal wiring 3, and the lower metal wiring 3 Disconnection can be prevented.

According to the present invention, the pixel electrode 10 is formed by randomly forming a plurality of rectangular openings 22 in the lower metal wiring 3 at a portion to be the contact region 21 of the terminal portion 20 of the TFT array substrate. The etching solution used for patterning the constituent ITO film is a gate insulating film 7.
In this case, even if it penetrates through the film defect part, the enlargement of the corroded area 23 of the lower metal wiring 3 by the etchant can be suppressed, and disconnection of the lower metal wiring 3 can be prevented.

Embodiment 2 In the first embodiment, the TFT
Although a plurality of rectangular openings 22 were randomly formed in the lower metal wiring 3 at the portion to be the contact region 21 of the terminal portion 20 of the array substrate, as shown in FIG. By arranging a plurality of rectangular openings 22 to be formed in several rows in a direction intersecting the direction in which the terminal section 20 is disconnected, the etching solution used for patterning the ITO film forming Even if it penetrates through the film defect part of the insulating film 7, as shown in FIG. 5B, the corroded area 23 of the lower metal wiring 3 by the etchant can be kept within a smaller range.

Embodiment 3 In the second embodiment, the TFT
A plurality of rectangular openings 22 are formed in the lower metal wiring 3 of the portion to be the contact region 21 of the terminal portion 20 of the array substrate in a direction intersecting the direction in which the terminal portion 20 is disconnected. As shown in FIG. 3A), the openings formed in the lower metal wiring 3 are formed as a plurality of slit-shaped openings 24 having a length longer than the length of the contact region 21, and the terminal portions 20 are formed.
Are arranged in a direction intersecting with the direction in which the pixel electrodes 10 are disconnected, so that the etching solution used for patterning the ITO film forming the pixel electrode 10 penetrates through the film defect portion of the gate insulating film 7 even if FIG. As shown in
The corroded area 23 of the lower metal wiring 3 due to the etchant can be kept between the two slit-shaped openings 24.

[0021]

As described above, according to the present invention, the scanning wiring (gate bus line) is formed using a material having a low specific resistance, and the lower layer of the TFT array substrate is formed as a contact region of a terminal portion. By forming a plurality of rectangular openings in metal wiring, the IT
When the etchant used for patterning the O film penetrates through the film defect of the insulating film covering the lower metal wiring, it is possible to suppress the corrosion area of the lower metal wiring from being expanded by the etchant, and to prevent the etching of the lower metal wiring. Disconnection can be prevented, and a highly reliable liquid crystal display device having a high aperture ratio can be obtained. Further, the opening formed in the lower metal wiring in the portion to be the contact region of the terminal portion of the TFT array substrate is a plurality of slit-shaped openings having a length longer than the length of the contact region, and the terminal portion is disconnected. By arranging in the direction intersecting the direction, the IT that constitutes the pixel electrode through the film defect portion of the insulating film covering the lower metal wiring is formed.
Even when the etchant for the O film permeates,
The corrosion area of the lower metal wiring by the etchant can be kept within a smaller range.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display according to Embodiment 1 of the present invention.

FIG. 2 is a schematic plan view showing a TFT array substrate of the liquid crystal display according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a terminal portion of the TFT array substrate of the liquid crystal display according to the first embodiment of the present invention.

FIG. 4 is a plan view for describing effects of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a plan view for explaining a structure of a terminal portion of a TFT array substrate of a liquid crystal display device according to a second embodiment of the present invention and an effect of the present embodiment.

FIG. 6 is a plan view for explaining a structure of a terminal portion of a TFT array substrate of a liquid crystal display device according to a third embodiment of the present invention and an effect of the present embodiment.

FIG. 7 is a cross-sectional view showing a manufacturing process of a TFT array substrate of this type of conventional liquid crystal display device.

FIG. 8 is a schematic plan view showing a TFT array substrate of a conventional liquid crystal display device.

FIG. 9 is a plan view showing a terminal portion of a TFT array substrate of a conventional liquid crystal display device.

FIG. 10 is a plan view showing a manufacturing process of a terminal portion of a TFT array substrate of a conventional liquid crystal display device.

FIG. 11 is a plan view showing a manufacturing process of a terminal portion of a TFT array substrate of a conventional liquid crystal display device.

FIG. 12 is a plan view showing a problem in a conventional liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate, 2 Gate electrode, 3 Lower metal wiring, 4 Resist pattern, 5 and 6 Anodized film, 7
Gate insulating film, 8 semiconductor layer, 9 contact layer, 10
Pixel electrode, 11 contact holes, 12 sources
Drain electrode, 13 terminal extraction wiring, 14 channel section, 15 passivation film, 16 display section, 17
Gate terminal, 18 source terminal, 19 short pattern for anodic oxidation, 20 terminal section, 21 contact area, 22 rectangular opening, 23 corroded area, 24 slit opening.

Continued on the front page F-term (reference) 2H092 JA26 JA29 JA33 JA35 JA38 JA39 JA42 JA43 JA44 JA47 JB13 JB23 JB27 JB32 JB33 JB36 JB38 JB54 JB56 JB63 JB69 JB79 KA05 KA07 KA12 KA16 KA18 KA22 KB05 MA14 MA19 MA24 MA19 MA24 MA27 MA34 MA35 MA37 MA41 NA14 NA15 NA25 NA27 NA28 NA29 PA06

Claims (5)

[Claims] 1. A transparent insulating substrate, switching elements arranged in a matrix on the transparent insulating substrate, pixel electrodes electrically connected to the switching elements, and scanning formed around the pixel electrodes. A display unit including a wiring (gate bus line) and a signal wiring (source bus line); a lower metal wiring on a periphery of the display unit on the transparent insulating substrate; and a lower metal wiring formed through the lower metal wiring and the insulating film. A first substrate having a terminal portion including a contact region to which the upper metal wiring is connected via a contact hole; a second substrate sandwiching a liquid crystal material together with the first substrate; A liquid crystal display device, wherein a plurality of openings are formed in the lower metal wiring in a portion to be a region. 2. The liquid crystal display device according to claim 1, wherein the plurality of openings formed in the lower metal wiring in a portion to be a contact region of the terminal portion are randomly arranged. 3. A plurality of openings formed in a lower metal wiring portion which is to be a contact region of a terminal portion are arranged in several rows in a direction intersecting a direction in which the terminal portion is disconnected. The liquid crystal display device according to claim 1. 4. A plurality of openings formed in a lower metal wiring in a portion to be a contact region of a terminal portion have a slit shape having a length longer than a length of the contact region, and disconnect the terminal portion. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is arranged in a direction intersecting the direction. 5. The semiconductor device according to claim 1, wherein the lower metal wiring is Al or A.
The liquid crystal display device according to any one of claims 1 to 4, wherein the liquid crystal display device is formed of an alloy containing l as a main component.