JP3975008B2 - Manufacturing method of display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a Viewing device, particularly a thin film transistor (TFT) a process for producing an active matrix type Viewing apparatus equipped with a switching element.
[0002]
[Prior art]
FIG. 7 is a cross-sectional view showing a manufacturing process of a TFT portion and a terminal portion of a TFT array substrate on which a TFT of a TFT type liquid crystal display device having a conventional low resistance signal wiring is mounted.
In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate electrode made of a low resistance metal such as Al or Al alloy formed on the transparent insulating substrate 1, and 3 is formed extending from the gate electrode 2. 4 is a resist pattern formed to protect a terminal lead-out region on the lower metal wiring 3, and 5 and 6 are anodic oxide films formed on the surfaces of the gate electrode 2 and the lower metal wiring 3. The anodic oxide film 6 is not formed in the region on the lower metal wiring 3 where the resist pattern 4 is formed. 7 is a gate insulating film made of a silicon nitride film formed on the entire surface of the gate electrode 2 and the lower metal wiring 3 on which the anodic oxide films 5 and 6 are formed, and 8 is formed on the gate electrode 2 through the gate insulating film 7. A formed semiconductor layer made of an amorphous silicon film, 9 is a contact layer made of an n ⁺ type amorphous silicon film formed on the semiconductor layer 8, 10 is a pixel electrode made of an ITO film, and 11 is a gate on the lower metal wiring 3. Contact holes for taking out terminals formed in the insulating film 7, 12 a source / drain electrode formed on the contact layer 9, 13 a terminal take-out wiring formed simultaneously with the formation of the source / drain electrode 12, and 14 a contact layer A channel portion 15 is formed by selectively etching 9 and a passivation film 15 is formed so as to cover the above components.
[0003]
8 is a schematic plan view showing a TFT array substrate of the conventional TFT type liquid crystal display device shown in FIG. 7, FIG. 9 is an enlarged plan view of the terminal portion of FIG. 8, and FIGS. 10 and 11 are terminal portions of FIG. It is a top view which shows this manufacturing process.
In the figure, 16 is a display portion in which TFTs and pixel electrodes are arranged in a matrix, 17 is a gate terminal, 18 is a source terminal, 19 is a short pattern for anodization, and 20 is an enlarged view of the gate terminal 17 or the source terminal 18. The terminal portion 21 shown in FIG. 7 is a contact region formed in the terminal portion 20, and the lower metal wiring 3 and the terminal extraction wiring 13 through the contact hole 11 for terminal extraction formed in the gate insulating film 7 in FIG. It is a contact part.
[0004]
Next, a method for manufacturing a TFT array substrate on which a conventional TFT is mounted will be described with reference to FIGS.
First, as shown in FIG. 7A, a single layer film made of a metal having a small specific resistance such as Al or an Al alloy is formed on the transparent insulating substrate 1, and then patterned using a resist, and the gate electrode 2 And lower layer metal wiring 3 is formed. Next, as shown in FIGS. 7B and 10A, after forming the resist pattern 4 to protect the terminal lead-out region on the lower layer metal wiring 3, the portion not covered by the resist pattern 4 is formed. The surface layers of the gate electrode 2 and the lower metal wiring 3 are selectively anodized to form anodized films 5 and 6.
Next, after removing the resist pattern 4, a silicon nitride film, an amorphous silicon film, and an n ⁺ -type amorphous silicon film to be the gate insulating film 7 are sequentially formed by a plasma CVD method, and then the amorphous silicon film and n are formed using a resist. ^{The +} -type amorphous silicon film is patterned to form the semiconductor layer 8 and the contact layer 9 of the TFT portion above the gate electrode 2 (FIGS. 7C and 10B).
[0005]
Next, as shown in FIG. 7D and FIG. 10C, after forming an ITO film, patterning is performed using a resist to form the pixel electrode 10. Next, as shown in FIGS. 7E and 10D, the gate insulating film 7 in the terminal extraction region is etched to form a contact hole 11 for terminal extraction. Next, as shown in FIGS. 7 (f) and 11 (a), after forming a film of Cr or the like, patterning is performed using a resist to form source / drain electrodes 12 and terminal lead-out wirings 13. At this time, the terminal lead-out wiring 13 is electrically connected to the lower metal wiring 3 through the contact hole 11. Subsequently, the n ⁺ -type amorphous silicon film (contact layer 9) that is not covered with the source / drain electrodes 12 is etched by dry etching to form the channel portion 14. Finally, as shown in FIGS. 7G and 11B, a passivation film 15 made of a silicon nitride film or the like is formed to protect the TFT portion.
[0006]
[Problems to be solved by the invention]
As described above, in the TFT array substrate of the conventional TFT liquid crystal display device, in order to obtain a high aperture ratio liquid crystal display device by miniaturizing the scanning wiring (gate bus line), Al having a small specific resistance is a main component. The Al or Al alloy constituting the low-resistance signal wiring has poor chemical resistance, and the pixel electrode 10 is formed (FIG. 7D). In FIG. 10C, since the lower layer metal wiring 3 of the contact region 21 of the terminal portion 20 is only covered with the gate insulating film 7, a film defect portion such as a pinhole exists in the gate insulating film 7. In this case, the etching solution used for patterning the ITO film constituting the pixel electrode 10 permeates through the film defect portion of the gate insulating film 7, and the Al in the contact region 21 of the terminal portion 20 as shown in FIG. Other forms of corrosion area 23 in the lower layer wiring metal of Al alloy, or by breaking the lower metal interconnect 3 has a problem such as to inhibit the contact between the lower metal interconnect 3 and the terminal lead-out wiring 13.
[0007]
This invention is a method of manufacturing a display device capable of resolving the problems described above, to prevent breakage of the lower layer metal wiring that put the terminal portion of the T FT array substrate, reliable and and to obtain the table shown having a high aperture ratio.
[0008]
[Means for Solving the Problems]
Method of manufacturing involved that Viewing apparatus to the present invention includes a base insulating substrate, switching elements arranged in a matrix in the insulation substrate, the switching element and electrically connected to the pixel electrode, and the pixel a display unit composed of a formed scan lines around the electrode (gate bus line) and the signal lines (source bus lines), and the lower layer metal wiring in the peripheral portion of the display portion on the insulation substrate, the lower metal interconnect a method of manufacturing a display device having a terminal portion having a contact hole formed in the gate insulating film formed on the pixel electrode above the gate insulating film is formed by etching using an etchant, the lower layer metal wires are formed by a metal film to be etched with an etching solution, the above-mentioned lower metal wiring terminal portion, the gate insulating film at the time of etching of the pixel electrode The area covered by only, and forming a plurality of openings.
[0009]
Further, a plurality of openings formed in the lower layer metal wiring is characterized by arranging at random.
Further, a plurality of openings formed in the lower layer metal wiring is characterized in that arranged in sequence in the direction intersecting the direction to break the terminal portion.
Further, a plurality of openings formed in the lower layer metal wiring is long chair slit shape than the length of the region covered by only the gate insulating film at the time of etching of the pixel electrode, intersects the direction in which the disconnection of the terminal portion It is arranged in a direction .
Further, the pixel electrode is formed of an ITO film, and the lower metal wiring is formed of Al or an alloy containing Al as a main component .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a manufacturing process of a TFT portion and a terminal portion of a TFT array substrate of a liquid crystal display device according to Embodiment 1 of the present invention.
In the figure, 1 is a transparent insulating substrate such as a glass substrate, 2 is a gate electrode made of a low resistance metal such as Al or Al alloy formed on the transparent insulating substrate 1, and 3 is formed extending from the gate electrode 2. 4 is a resist pattern formed to protect a terminal lead-out region on the lower metal wiring 3, and 5 and 6 are anodic oxide films formed on the surfaces of the gate electrode 2 and the lower metal wiring 3. The anodic oxide film 6 is not formed in the region on the lower metal wiring 3 where the resist pattern 4 is formed. 7 is a gate insulating film made of a silicon nitride film formed on the entire surface of the gate electrode 2 on which the anodic oxide films 5 and 6 are formed and the lower metal wiring 3, and 8 is above the gate electrode 2 through the gate insulating film 7. A semiconductor layer made of an amorphous silicon film or the like, 9 is a contact layer made of an n ⁺ type amorphous silicon film formed on the semiconductor layer 8, 10 is a pixel electrode made of an ITO film, and 11 is on the lower metal wiring 3. Contact holes for extracting terminals formed in the gate insulating film 7, 12 are source / drain electrodes formed on the contact layer 9, 13 are terminal extraction wirings formed simultaneously with the formation of the source / drain electrodes 12, 14 are A channel portion 15 formed by selectively etching the contact layer 9, and a passivation film 15 formed so as to cover the above-described components. The
[0011]
2 is a schematic plan view of the TFT array substrate of the liquid crystal display device shown in FIG. 1, FIG. 3 is an enlarged view of the terminal portion of FIG. 2, (a) is a schematic plan view of the terminal portion, and (b) is a terminal. It is an enlarged plan view of the lower layer metal wiring which comprises a part. In the figure, 16 is a display portion in which TFTs and pixel electrodes are arranged in a matrix, 17 is a gate terminal, 18 is a source terminal, 19 is a short pattern for anodization, and 20 is an enlarged view of the gate terminal 17 or the source terminal 18. The terminal portion 21 shown in FIG. 1 is a contact region formed in the terminal portion 20, and the lower metal wiring 3 and the terminal extraction wiring 13 through the contact hole 11 for terminal extraction formed in the gate insulating film 7 in FIG. It is a contact part. Reference numeral 22 denotes an opening formed in the lower metal wiring 3 of the terminal portion 20.
[0012]
Next, a manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment will be described.
First, as shown in FIG. 1A, a specific resistance such as an Al (hereinafter referred to as Al-0.2 wt% Cu) film containing 0.2% by weight of Cu on the surface of the transparent insulating substrate 1 is used. After forming a metal film having a small thickness of about 270 nm by sputtering or the like, patterning is performed using a resist formed by photolithography, thereby forming the gate electrode 2 and the lower layer metal wiring 3. At this time, as shown in FIG. 3B, a plurality of rectangular openings 22 are randomly formed in the lower metal wiring 3 in the portion that becomes the contact region 21 of the terminal portion 20. Etching solution mainly composed of phosphoric acid, acetic acid and nitric acid is used for etching the Al film. The composition of phosphoric acid, acetic acid and nitric acid is studied in advance, and the etching end face of the Al film is formed into a tapered shape. The covering property of the film formed in the upper layer can be improved.
[0013]
Next, a resist pattern 4 is formed to protect the terminal extraction region on the lower metal wiring 3, and then the resist pattern 4 is covered with a short pattern 19 that is electrically short-circuited with the gate electrode 2 and the lower metal wiring 3. A portion of the gate electrode 2 and the surface layer of the lower metal wiring 3 that are not covered are selectively anodized to form anodic oxide films 5 and 6 (FIG. 1B). At this time, since the anodic oxide film is not formed on the portion covered with the resist pattern 4, the process of removing the anodic oxide film in the terminal lead-out region is not required in the subsequent process. Thereafter, the resist pattern 4 is removed.
[0014]
Next, a silicon nitride film to be the gate insulating film 7 is formed by plasma CVD to a thickness of about 370 nm, an amorphous silicon film is about 120 nm, and an n ⁺ type amorphous silicon film doped with impurities is sequentially formed to a thickness of about 30 nm. The amorphous silicon film and the n ⁺ type amorphous silicon film are simultaneously patterned using the resist formed by the above steps, and the semiconductor layer 8 and the contact layer 9 of the TFT portion are formed above the gate electrode 2 (FIG. 1C).
Next, as shown in FIG. 1D, after forming an ITO film as a transparent conductive film to a thickness of about 100 nm by a sputtering method or the like, patterning is performed using a resist formed by a photoengraving method to form a pixel electrode 10. .
Next, as shown in FIG. 1E, the gate insulating film 7 in the terminal extraction region is etched by a dry etching method to form a contact hole 11 for terminal extraction.
[0015]
Next, as shown in FIG. 1F, in order to form the source / drain electrodes 12 and the source bus lines (not shown), first, n ⁺ Type amorphous silicon film and ITO film constituting pixel electrode 10 and Cr film with good ohmic contact are about 100 nm, Al-0.2 wt% Cu film with low specific resistance is about 300 nm in the intermediate layer, and Cr film is the top layer A three-layer film is formed continuously for about 50 nm. Next, the three-layer film is sequentially patterned using a resist formed by photolithography, thereby forming source / drain electrodes 12 and terminal lead-out wirings 13. At this time, the terminal lead-out wiring (upper layer metal wiring) 13 is electrically connected to the lower layer metal wiring 3 through the contact hole 11 for terminal lead-out.
Subsequently, the n ⁺ -type amorphous silicon film (contact layer 9) that is not covered with the source / drain electrodes 12 is etched by dry etching to form the channel portion 14.
[0016]
Finally, as shown in FIG. 1G, a passivation film 15 is formed by forming a silicon nitride film with a thickness of about 500 nm by plasma CVD or the like in order to protect the TFT portion.
An alignment film is formed on the surface of the TFT array substrate formed by the above steps and the opposite substrate on which the light shielding film, the counter electrode, etc. are formed on another transparent insulating substrate, and the liquid crystal material is injected therebetween. The liquid crystal display device is configured by sealing with a sealing material.
[0017]
In the manufacturing method of the TFT array substrate of the liquid crystal display device according to the present embodiment, when the pixel electrode 10 is formed, the etching solution used for patterning the ITO film constituting the pixel electrode 10 is, as shown in FIG. Even when the lower metal wiring 3 made of Al or Al alloy is corroded through the film defect portion of the gate insulating film 7 in the contact region 21 of 20, the corrosion region 23 is formed by the opening 22 formed in the lower metal wiring 3. Can be suppressed, and disconnection of the lower layer metal wiring 3 can be prevented.
[0018]
According to the present invention, a plurality of rectangular openings 22 are randomly formed in the lower metal wiring 3 in the portion that becomes the contact region 21 of the terminal portion 20 of the TFT array substrate, thereby forming the ITO constituting the pixel electrode 10. Even when the etching solution used for patterning the film penetrates through the film defect portion of the gate insulating film 7, the expansion of the corrosion region 23 of the lower layer metal wiring 3 due to the etching solution can be suppressed, and the disconnection of the lower layer metal wiring 3 can be prevented. Can be prevented.
[0019]
Embodiment 2. FIG.
In the first embodiment, a plurality of rectangular openings 22 are randomly formed in the lower metal wiring 3 in the portion that becomes the contact region 21 of the terminal portion 20 of the TFT array substrate. However, as shown in FIG. In addition, a plurality of rectangular openings 22 formed in the lower metal wiring 3 are arranged in several rows in a direction intersecting with the direction in which the terminal portion 20 is disconnected, thereby patterning the ITO film constituting the pixel electrode 10. Even when the etching solution used penetrates through the film defect portion of the gate insulating film 7, as shown in FIG. 5B, the corrosion region 23 of the lower metal wiring 3 by the etching solution can be kept within a smaller range. it can.
[0020]
Embodiment 3 FIG.
In the second embodiment, a plurality of rectangular openings 22 are arrayed in the direction intersecting with the direction in which the terminal portion 20 is disconnected in the lower layer metal wiring 3 in the portion to be the contact region 21 of the terminal portion 20 of the TFT array substrate. However, as shown in FIG. 6A, the openings formed in the lower metal wiring 3 are made into a plurality of slit-like openings 24 having a length longer than the length of the contact region 21, and the terminal portion 20 is disconnected. Even when the etching solution used for patterning the ITO film constituting the pixel electrode 10 permeates through the film defect portion of the gate insulating film 7 by arranging in the direction crossing the direction, as shown in FIG. In addition, the corroded area 23 of the lower metal wiring 3 by the etching solution can be retained between the two slit-shaped openings 24.
[0021]
【The invention's effect】
As described above, according to the present invention , the pixel electrode on the gate insulating film is formed by etching using the etching solution, and the lower layer metal wiring is formed of the metal etched by the etching solution. the, the portion covered by only the gate insulating film at the time of etching of the pixel electrode, so to form a plurality of openings, the etching solution used in the patterning of the pixel electrodes is, film of the insulating film covering the lower metal interconnect when penetrated through the defect, the corrosion area of the lower metal wiring by the etchant can be suppressed is to expand, thereby preventing breakage of the lower metal interconnect, obtain Viewing device of high reliability and high aperture ratio Can do.
Further, a plurality of openings formed in the lower layer metal wiring is long chair slit shape than the length of the region covered by only the gate insulating film at the time of etching of the pixel electrode, intersects the direction in which the disconnection of the terminal portion by arranging the direction, even if the etchant against the pixel electrodes has permeated through the membrane defect portion of the insulating film covering the lower metal wiring, fasten the corrosion region of the lower metal wiring due to the etching solution within the range smaller than be able to.
[Brief description of the drawings]
1 is a cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device according to Embodiment 1 of the present invention;
FIG. 2 is a schematic plan view showing a TFT array substrate of the liquid crystal display device according to Embodiment 1 of the present invention.
FIG. 3 is a plan view showing a terminal portion of a TFT array substrate of the liquid crystal display device according to Embodiment 1 of the present invention.
FIG. 4 is a plan view for explaining an effect of the liquid crystal display device according to the first embodiment of the invention.
FIG. 5 is a plan view for explaining the structure of a terminal portion of a TFT array substrate of a liquid crystal display device according to Embodiment 2 of the present invention and the effect of the present embodiment;
6 is a plan view for explaining the structure of a terminal portion of a TFT array substrate of a liquid crystal display device according to Embodiment 3 of the present invention and the effect of the present embodiment; FIG.
FIG. 7 is a cross-sectional view showing a manufacturing process of a TFT array substrate of this type of conventional liquid crystal display device.
FIG. 8 is a schematic plan view showing a TFT array substrate of a conventional liquid crystal display device.
FIG. 9 is a plan view showing a terminal portion of a TFT array substrate of a conventional liquid crystal display device.
FIG. 10 is a plan view showing a manufacturing process of a terminal portion of a TFT array substrate of a conventional liquid crystal display device.
FIG. 11 is a plan view showing a manufacturing process of a terminal portion of a TFT array substrate of a conventional liquid crystal display device.
FIG. 12 is a plan view showing problems in a conventional liquid crystal display device.
[Explanation of symbols]
1 transparent insulating substrate, 2 gate electrode, 3 lower layer metal wiring,
4 resist pattern, 5, 6 anodized film, 7 gate insulating film,
8 semiconductor layer, 9 contact layer, 10 pixel electrode,
11 contact holes, 12 source / drain electrodes,
13 terminal extraction wiring, 14 channel part, 15 passivation film,
16 display, 17 gate terminal, 18 source terminal,
19 Short pattern for anodization, 20 terminal area, 21 contact area,
22 rectangular opening, 23 corrosion area, 24 slit opening.

Claims (5)

And the insulation substrate,
Switching elements arranged in a matrix on Kize' edge substrate, the switching element and electrically connected to the pixel electrode, and the scanning lines formed around the pixel electrode (gate bus line) and the signal lines ( A display unit consisting of a source bus line),
And the lower layer metal wiring in the peripheral portion of the display portion of the upper Kize' edge of the substrate, a method of manufacturing a display device having a terminal portion having a contact hole formed in the gate insulating film formed on the lower metal interconnect Because
The pixel electrode above the gate insulating film is formed by etching using an etchant,
The lower layer metal wiring is formed by a metal film etched with the etching solution,
Above the terminal portions of the lower metal wiring, the area covered only by the gate insulating film at the time of etching of the pixel electrode, a manufacturing method of a plurality of Viewing device you and forming an opening. A plurality of openings, the production method of Viewing apparatus according to claim 1, wherein that you randomly arranged to form a lower layer metal wiring. A plurality of openings formed in the lower layer metal wiring manufacturing method of Viewing apparatus according to claim 1, wherein that you arranged in sequence in the direction intersecting the direction to break the ends of the terminal portion. A plurality of openings formed in the lower layer metal wiring is long chair slit shape than the length of the region covered by only the gate insulating film at the time of etching of the pixel electrodes in a direction intersecting the direction to break the ends of the terminal portion method for producing Viewing apparatus according to claim 1, wherein that you array. The pixel electrode formed of ITO film, the lower metal lines, production of Viewing apparatus according to any one of claims 1 to 4, characterized that you an alloy mainly containing Al or Al Method.

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