KR20140075920A - Display Device - Google Patents

Abstract

The present invention provides a display device which includes a display panel; a gate driving part which supplies a gate signal to the display panel; a data driving part which supplies data signal to the display panel; lines which are formed in the non-display region of the display panel; and conductive patterns which have an protrusion part which is adjacent to the lines in the non-display region of the display panel and has a point which includes an edge and an apex to induce static electricity coming from the outside.

Description

[0001]

An embodiment of the present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Currently, display devices such as a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device are being implemented to a small size, a medium size and a large size.

The display device as described above includes a display panel including sub-pixels arranged in a matrix form, a driver for driving the display panel, and a timing controller for controlling the driver. The driver includes a gate driver for supplying a gate signal to the display panel and a data driver for supplying a data signal to the display panel.

In some of the above-described display devices, various signal wirings, power supply wirings, and the like are formed on the outer bezel area of the display panel. The signal wiring and the power wiring located on the outer bezel area of the display panel are vulnerable to static electricity flowing in the upper, lower, left, and right sides.

The static electricity flows through various paths from the outside such as the dry etching in the manufacturing process of the display panel or the flow in the substrate transfer. When static electricity flows into the signal wiring and the power wiring, the adjacent wirings are short-circuited or disconnected, resulting in display failure of the display device.

The present invention for solving the above-mentioned problems of the background art provides a display device capable of effectively solving and preventing the problem of short-circuiting or disconnection of wirings adjacent to each other due to static electricity flowing from the outside, .

According to an aspect of the present invention, A gate driver for supplying a gate signal to the display panel; A data driver for supplying a data signal to the display panel; Wirings formed in a non-display area of the display panel; And a conductive pattern formed adjacent to the wirings in the non-display area of the display panel and having protrusions each including a corner or a vertex to induce static electricity introduced from the outside.

The conductive patterns can be formed on the outside, inside or outside and inside of the wirings.

The conductive patterns can be electrically connected by a conductive wiring having a wiring width that is thinner than the wiring.

The conductive wiring may be electrically connected to a pad or electrode that carries a voltage lower than the high-potential voltage.

The conductive patterns and the conductive wiring can be melted or removed by the introduced static electricity.

The conductive patterns may be formed spaced apart or adjacent to each other and may be electrically floated.

The conductive patterns may be formed of one selected from a triangular shape, a rectangular shape, a rhombic shape, a hexagon shape, and a random shape, or a combination thereof.

The conductive patterns may be formed along the route in which the wirings are wired or may be formed in some area.

The conductive patterns may be formed between the wirings by being divided into N (N is an integer of 2 or more) groups.

The wirings may include signal wiring and power wiring for transmitting signals to the gate driver and the display panel.

Disclosure of the Invention Problems to be Solved by the Invention The present invention provides a display device in which a pattern or wiring capable of inducing static electricity is formed in a non-display area of a display panel, And the like can be solved.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention;
Fig. 2 is a schematic view showing the subpixel shown in Fig. 1. Fig.
3 is a configuration diagram of the display device shown in Fig.
4 is an enlarged view for explaining a main part of a display device according to the first embodiment of the present invention;
5 is a modification of the first embodiment;
6 is an enlarged view for explaining a main part of a display device according to a second embodiment of the present invention;
Fig. 7 is a modification of the second embodiment; Fig.
8 is an enlarged view for explaining a main part of a display device according to a third embodiment of the present invention;
Fig. 9 is a modification of the third embodiment. Fig.
10 is an enlarged view for explaining a main part of a display device according to a fourth embodiment of the present invention;
11 is a modification of the fourth embodiment.
12 is an enlarged view for explaining a main part of a display device according to a fifth embodiment of the present invention;
13 is a modification of the fifth embodiment.
14 shows various examples of conductive patterns.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a display device according to an embodiment of the present invention. FIG. 2 is a schematic view of subpixels shown in FIG. 1, .

The display device according to an embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a gate driving unit 130, a data driving unit 140, a display panel 150, and a power supply unit 160.

The image processing unit 110 supplies the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, the clock signal CLK and the data signal DATA to the timing control unit 120 do.

The timing control unit 120 uses a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a clock signal CLK supplied from the image processing unit 110 And controls the operation timings of the data driver 140 and the gate driver 130.

The timing controller 120 supplies the data driver 140 with the data signal DATA supplied from the image processor 110 using the timing signal. The timing control unit 120 can determine the frame period by counting the data enable signal DE in one horizontal period so that the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the image processing unit 110 are omitted .

The control signals generated by the timing controller 120 include a gate timing control signal GDC for controlling the operation timing of the gate driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140. [ ). The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The data timing control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and the like.

The gate driver 130 outputs the gate signal while shifting the level of the gate voltages in response to the gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 supplies a gate signal to the sub-pixels SP included in the display panel 150 through the gate lines GL.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, and converts the sampled data signal into a gamma reference voltage. The data driver 140 supplies the data signal DATA to the sub-pixels SP included in the display panel 150 through the data lines DL.

The display panel 150 displays an image corresponding to the gate signal supplied from the gate driver 130 and the data signal DATA supplied from the data driver 140. The display panel 150 includes sub-pixels SP for controlling light to display an image.

One subpixel includes a switching transistor SW connected to the gate line GL1 and the data line DL1 and a capacitor Cst for storing the data signal DATA supplied through the switching transistor SW as a data voltage, And a pixel circuit (PC) that operates in response to the data voltage stored in the data line (Cst). According to the configuration of the pixel circuit PC, the sub-pixels SP may be constituted by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element.

When the display panel 150 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 150 is formed of an organic light emitting display panel, the display panel 150 may be implemented as a top emission type, a bottom emission type, or a dual emission type. In addition, the display panel 150 is composed of an electrophoretic display panel as well as a liquid crystal display panel or an organic light emitting display panel.

The power supply unit 160 outputs a high potential voltage, a low potential voltage, a gate high voltage, and a gate low voltage. The high potential voltage is output through the first power supply line (VCC), the low potential voltage is output through the second power supply line (GND), the gate high voltage is output through the gate high voltage line (VGH) The voltage is output through the gate-low voltage wiring (VGL).

The high and low potential voltages are supplied to at least one of the timing controller 120, the gate driver 130, the data driver 140, and the display panel 150. The gate voltages including the gate high voltage and the gate low voltage are supplied to the gate driver 130.

The display device described above is configured as follows.

The display panel 150 defines a display area AA and a non-display area NA. In the display area AA, subpixels SP are formed. Gate drivers 130a and 130b and data drivers 140a and 140b are formed in the non-display area NA.

The gate drivers 130a and 130b are mounted in an IC (Integrated Circuit) form in a non-display area NA defined by the left, right, or right and left outer bezel areas of the display panel 150. [ The gate drivers 130a and 130b are mounted on the gate pad portion formed on the display panel 150 in a COG (Chip On Glass) form so as to be in electrical contact with each other.

The data drivers 140a and 140b are mounted on the upper or lower outer side of the display panel 150 in the form of an integrated circuit (IC). The data drivers 140a and 140b are mounted in a COG (Chip On Glass) form so as to be in electrical contact with data pad portions formed on the display panel 150. [

One end of the flexible circuit board 170 is connected to a connection pad portion formed on the lower outer side of the display panel 150. The flexible circuit board 170 electrically connects the printed circuit board 180 and the display panel 150 and transmits signals therebetween. The flexible circuit board 170 is connected to the display panel 150, the gate drivers 130a and 130b, and the display panel 150. The flexible printed circuit board 170 includes various components, such as a timing controller 120 and a power supply unit 160, To the data drivers 140a and 140b.

The printed circuit board 180 is connected to one side of the connection pad portion formed on the other side of the flexible circuit board 170. On the printed circuit board 180, a timing control unit 120 and a power supply unit 160 are formed. The timing control unit 120 and the power supply unit 160 are mounted on the printed circuit board 180 in the form of an integrated circuit (IC). In addition, the image processing unit 110 is mounted on a main circuit board (or a system board) connected to the printed circuit board 180 in the form of an IC (Integrated Circuit), but illustration thereof is omitted.

Meanwhile, the configuration of the display device shown and described above is only for facilitating understanding of the present invention, and the configuration and arrangement of the device according to the present invention are not limited thereto. For example, in the present invention, the gate driving units 130a and 130b and the data driving units 140a and 140b are mounted in the non-display area NA of the display panel 150 in the form of an integrated circuit (IC). However, one or more of the gate drivers 130a and 130b and the data drivers 140a and 140b may be mounted on an external substrate, such as the flexible circuit board 180. And may be formed in a non-display area NA of the display panel 150 in a gate in panel (GIP) manner in the case of the gate drivers 130a and 130b.

Hereinafter, the present invention will be described more specifically with reference to an enlarged view of the "EA" area shown in Fig.

≪ Embodiment 1 >

FIG. 4 is an enlarged view for explaining a main part of a display device according to the first embodiment of the present invention, and FIG. 5 is a modification of the first embodiment.

The non-display area NA of the display panel 150 includes a pattern area PA, a wiring area WA, and a pad area PADA. The pad region PADA is located inside the wiring region WA. The wiring region WA is located between the pattern region PA and the pad region PADA. The pattern area PA is located outside the wiring area WA. That is, the pattern area PA is located at the outermost one of the non-display areas NA of the display panel 150.

The pad region PADA is formed with a gate pad portion PAD on which the gate driver is mounted. The gate pad portion PAD is divided and connected to the signal lines VGH, GSP and VGL formed in the wiring region WA and the power lines VCC and GND.

Signal lines VGH, GSP and VGL connected to the gate pad unit PAD and power lines VCC and GND are separately formed in the wiring region WA. The power supply lines (VCC, GND) include a first power supply line (VCC) for transferring a high potential voltage and a second power supply line (GND) for transferring a low potential voltage. The signal wirings VGH, GSP and VGL are connected to the gate high voltage wiring VGH for transferring the gate high voltage, the gate start wiring GSP for transferring the gate start pulse and the gate low voltage wiring VGL for transferring the gate low voltage, And the like.

Since the gate high voltage wiring VGH and the gate low voltage wiring VGL are wirings for transferring a voltage, they can have a wiring width that is thicker than the gate start wiring GSP. Since the first power supply line VCC and the first power supply line VCC are wirings for transmitting power, they can have a wider width than the gate start line GSP. On the other hand, since the gate start wiring GSP is a wiring for transmitting a signal, it can have a thinner wiring width than the gate high voltage wiring VGH and the gate low voltage wiring VGL.

The signal lines VGH, GSP, and VGL and the power lines VCC and GND may be formed in a multi-layer structure. The first layer wiring which constitutes each of the signal wirings VGH, GSP and VGL and the power supply wiring VCC and GND is wired in the y axis direction and the second layer wiring is wired in the y axis direction, And is electrically connected to the gate pad portion (PAD). Thus, in the case of the second layer wiring constituting the signal wirings (VGH, GSP, VGL) and the power supply wirings (VCC, GND), each of the second layer wirings has the overlap region OVL overlapping the first layer wirings constituting the other wirings . The first layer wiring and the second layer wiring located in the overlap area OVL are electrically insulated by the insulating film.

On the other hand, in FIG. 4, a wiring located between the gate high voltage wiring VGH and the gate low voltage wiring VGL is defined as a gate start wiring GSP in order to simply illustrate wirings formed in the wiring area WA. However, the wiring located between the gate high voltage wiring VGH and the gate low voltage wiring VGL further includes not only the gate start wiring GSP but also other wiring for transmitting signals. That is, signal wirings VGH, GSP, and VGL and power supply wirings VCC and GND formed in the wiring region WA are merely examples, and the present invention is not limited thereto.

Conductive patterns PTN are formed in the pattern region PA. The conductive patterns PTN are formed to be spaced apart from each other or adjacent to each other. The conductive patterns PTN serve to induce static electricity (ESD) flowing into the signal lines VGH, GSP, VGL and the power lines VCC, GND located on the bezel region.

On the other hand, electrostatic discharge (ESD) flows through various paths from the outside such as a dry etching process in the manufacturing process of the display panel or a flow in the substrate transferring process. When ESD flows into the signal wiring and the power wiring, the adjacent wirings are short-circuited or disconnected, resulting in poor display of the display device.

However, when the conductive patterns PTN are formed in the pattern area PA as in the first embodiment of the present invention, the ESD in which the conductive patterns PTN are introduced can be induced first, And is prevented. To this end, the conductive patterns PTN are formed to be electrically connected to each other by the conductive wiring PL as shown in FIG. 4 or to be electrically floating as shown in FIG.

The conductive wiring (PL) may be connected to a pad, an electrode, or the like formed on a display panel, a flexible circuit board, and / or a printed circuit board. The conductive wiring PL may be connected to a pad or an electrode to which a negative voltage or a voltage lower than the high potential voltage is supplied. For example, the conductive wiring line PL may be connected to a second power line (GND) formed on a display panel, a flexible circuit board, and / or a printed circuit board. The conductive wiring line PL and the second power line GND can be electrically connected in various regions according to the structure of the display device and the wiring layout, and therefore, illustration thereof will be omitted.

When a specific voltage is supplied to the conductive wiring (PL), it is possible to prevent interference or noise with the adjacent wiring. However, the conductive wiring line PL must have a thin wiring width with respect to the signal lines VGH, GSP, and VGL and the power lines VCC and GND so that the introduced static electricity ESD can be induced first. That is, the conductive wiring (PL) must have the thinnest wiring width among the wirings formed on the display panel (150). The reason why the conductive wiring (PL) is formed in this way is that the static electricity (ESD) flows through the various paths from the outside, but once it flows through the specific wiring, the path is formed in the wiring having the thinnest wiring width .

The first embodiment of the present invention is characterized in that conductive patterns PTN are formed in a shape having a sharp triangular shape in the region facing the signal lines VGH, GSP, and VGL in order to effectively prevent and prevent problems caused by static electricity do. In addition to electric and magnetic fields, static electricity is most strongly induced in the corners or protruding protrusions. When the conductive patterns PTN are formed into a sharp triangular shape by using this principle, it is possible to easily induce the electrostatic discharge (ESD) on the same principle as the lightning rod.

When the conductive patterns PTN have a sharp triangular shape in the region facing the signal lines VGH, GSP, and VGL, the static electricity ESD flowing in the right, upper, and lower directions can be easily induced. The conductive patterns PTN and the conductive wirings PL are formed along the path in which the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are wired or formed only in a part of the area.

On the other hand, in the first embodiment of the present invention, the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are formed in the wiring region WA. However, depending on the structure and characteristics of the display device, only the power supply lines VCC and GND may be formed in the wiring region WA, or wirings other than the lines defined by the signal lines VGH, GSP and VGL may be formed.

Meanwhile, the conductive patterns PTN and the conductive lines PL according to the present invention can be formed anywhere other than the wiring or the pattern, if the area corresponds to the non-display area NA of the display panel 150. The conductive patterns PTN and the conductive lines PL according to the present invention can be formed not only on the non-display area NA of the display panel 150 but also on a flexible circuit board or a printed circuit board.

On the other hand, when the signal lines VGH, GSP and VGL and the power lines VCC and GND are formed in a multi-layer structure, the conductive patterns PTN and the conductive lines PL are electrically connected to the signal lines VGH, May be formed corresponding to the lower wiring layer or the upper wiring layer constituting the wiring (VCC, GND) or may be formed corresponding to the upper wiring and the lower wiring.

On the other hand, the conductive patterns (PTN) and the conductive wiring (PL) can be selected as a material from which the pattern or wiring can be melted or removed by the introduced static electricity (ESD). When the conductive patterns (PTN) and the conductive wiring (PL) are melted or removed, the problem of signal interference with the wiring adjacent thereto can be solved.

≪ Embodiment 2 >

FIG. 6 is an enlarged view for explaining a main part of a display device according to a second embodiment of the present invention, and FIG. 7 is a modification of the second embodiment.

The non-display area NA of the display panel 150 includes a pattern area PA, a wiring area WA, and a pad area PADA. The pad region PADA is located inside the wiring region WA. The wiring region WA is located between the pattern region PA and the pad region PADA. The pattern area PA is located outside the wiring area WA. That is, the pattern area PA is located at the outermost one of the non-display areas NA of the display panel 150.

According to the second embodiment of the present invention, the conductive patterns PTN are formed to be electrically connected to each other by the conductive wiring PL as shown in FIG. 6 or to be electrically floating as shown in FIG. The conductive patterns PTN and the conductive wirings PL are formed along the route in which the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are wired in the same or similar manner as in the first embodiment, .

However, the conductive patterns PTN are formed in a rectangular shape unlike the first embodiment. When the conductive patterns PTN have a rectangular shape, it is possible to easily induce the static electricity flowing in the upper right, lower right, lower left, and upper left directions. That is, when the conductive patterns PTN have a rectangular shape, the electrostatic induction function in the diagonal direction will be improved.

≪ Third Embodiment >

FIG. 8 is an enlarged view for explaining a main part of a display device according to a third embodiment of the present invention, and FIG. 9 is a modification example of the third embodiment.

The non-display area NA of the display panel 150 includes a pattern area PA, a wiring area WA, and a pad area PADA. The pad region PADA is located inside the wiring region WA. The wiring region WA is located between the pattern region PA and the pad region PADA. The pattern area PA is located outside the wiring area WA. That is, the pattern area PA is located at the outermost one of the non-display areas NA of the display panel 150.

According to the third embodiment of the present invention, the conductive patterns PTN are formed to be electrically connected to each other by the conductive wiring PL as shown in FIG. 8 or to be electrically floating as shown in FIG. The conductive patterns PTN and the conductive wirings PL are formed along the route in which the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are wired in the same or similar manner as in the first embodiment, .

However, the conductive patterns PTN are formed in a rhombic shape unlike the second embodiment. When the conductive patterns PTN have a rhombic shape, it is possible to easily induce the static electricity flowing in the upper, lower, left, and right directions.

<Fourth Embodiment>

FIG. 10 is an enlarged view for explaining a main part of a display device according to a fourth embodiment of the present invention, and FIG. 11 is a modification example of the fourth embodiment.

The non-display area NA of the display panel 150 includes a pattern area PA, a wiring area WA, and a pad area PADA. The pad region PADA is located inside the wiring region WA. The wiring region WA is located between the pattern region PA and the pad region PADA. The pattern area PA is located in the wiring area WA.

According to the fourth embodiment of the present invention, the conductive patterns (PTN) are formed to be electrically connected to each other by the conductive wiring (PL) as shown in FIG. 10 or to be electrically floating as shown in FIG. The conductive patterns PTN and the conductive wirings PL are formed along the route in which the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are wired in the same or similar manner as in the first embodiment, .

However, the conductive patterns PTN, the conductive patterns PTN, and the conductive wiring PL are formed in the signal wirings VGH, GSP, and VGL. That is, not only the signal lines VGH, GSP, and VGL and the power lines VCC and GND connected to the gate pad unit PAD but also the conductive patterns PTN included in the pattern area PA are formed in the wiring area WA. Or conductive patterns (PTN) and a conductive wiring (PL) are formed.

For example, a pattern area PA including conductive patterns PTN, conductive patterns PTN, and conductive wiring PL is located between the gate high voltage wiring VGH and the gate start wiring GSP. However, this is only an example. The pattern area PA can be selectively positioned between the gate start wiring GSP and the gate low voltage wiring VGL, between the gate low voltage wiring VGL and the first power wiring VCC, have.

<Fifth Embodiment>

FIG. 12 is an enlarged view for explaining a main part of a display device according to a fifth embodiment of the present invention, and FIG. 13 is a modification of the fifth embodiment.

The non-display area NA of the display panel 150 includes a pattern area PA, a wiring area WA, and a pad area PADA. The pad region PADA is located inside the wiring region WA. The wiring region WA is located between the pattern region PA and the pad region PADA. The pattern regions PA1 and PA2 are divided into N (N is an integer of 2 or more) groups in the wiring region WA.

According to the fifth embodiment of the present invention, the conductive patterns PTN are formed to be electrically connected to each other by the conductive wiring PL as shown in FIG. 12 or to be electrically floating as shown in FIG. The conductive patterns PTN1 and PTN2 and the conductive wirings PL1 and PL2 are formed along the path in which the signal wirings VGH, GSP and VGL and the power supply wirings VCC and GND are wired in the same or similar manner as in the first embodiment Or only in some regions.

However, the conductive patterns PTN1 and PTN2, the conductive patterns PTN1 and PTN2 and the conductive wirings PL1 and PL2 are formed in the signal wirings VGH, GSP, and VGL in a group of N (N is an integer of two or more) do. For example, not only the signal wirings VGH, GSP, and VGL and the power wirings VCC and GND connected to the gate pad portion PAD are included in the first and second pattern regions PA1 and PA2, The conductive patterns PTN1 and PTN2, the conductive patterns PTN1 and PTN2, and the conductive wirings PL1 and PL2 are formed.

For example, the first pattern area PA1 including the first conductive patterns PTN1, the first conductive patterns PTN1, and the first conductive interconnection PL1 is connected to the gate high voltage wiring VGH and the gate start wiring GSP). The second pattern region PA2 including the second conductive patterns PTN2 and the second conductive patterns PTN2 and the second conductive wiring PL2 is electrically connected to the gate low voltage wiring VGL and the first power wiring VCC). The first and second pattern regions PA1 and PA2 are provided between the gate start wiring GSP and the gate low voltage wiring VGL and between the first power wiring VCC and the second power wiring GND, And the like.

The conductive patterns PTN1 and PTN2 included in the first and second pattern regions PA1 and PA2 are formed in a combination of triangular, rhombic, rectangular, and hexagonal shapes. The first conductive patterns PTN1 included in the first pattern area PA1 are connected to the first conductive wiring PL1 while the second conductive patterns PT1 included in the second pattern area PA2 are formed to be connected to the first conductive wiring PL1. The second conductive wiring line PTN2 may be formed in a floating state with the second conductive wiring line PL2 omitted.

Conversely, the first conductive patterns PTN1 included in the first pattern area PA1 are formed in a floating state with the first conductive wiring PL1 omitted, while the first conductive patterns PTN1 included in the second pattern area PA2 2 conductive patterns PTN2 may be formed so as to be connected to the second conductive wiring PL2.

Hereinafter, various shapes that can be selected as the conductive patterns PTN1 and PTN2 will be described.

14 shows various examples of the conductive patterns.

The conductive patterns PTN may have a star shape as shown in Fig. 14 (a), an octagonal shape as shown in Fig. 14 (b), and an octagonal shape as shown in Fig. 14 (c) as well as the shapes described in the first to fifth embodiments. A parallelogram shape as shown in FIG. 14A, and a right triangle shape as shown in FIG. 14D. In addition, the shape of the conductive patterns PTN is not limited to this, since any one of the conductive patterns PTN has a random (anomalous shape) shape having a sharp portion such as an edge or a vertex.

As described above, when the conductive patterns are formed on the inner side or the outer side of the wiring region where the signal wiring and the power wiring are wired, the static electricity introduced from the outside can be efficiently induced, absorbed and discharged. Accordingly, it is an object of the present invention to provide a display device capable of effectively preventing and reducing the problem of short-circuiting or disconnection of mutually adjacent wirings due to static electricity introduced from the outside by forming a pattern or wiring for inducing static electricity in a non- And a display device capable of solving display defects and the like can be provided.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

120: timing controller 130: gate driver
140: Data driver 150: Display panel
160: Power supply unit AA: Display area
NA: non-display area PA: pattern area
WA: wiring area PADA: pad area
VGH, GSP, VGL: Signal wiring VCC, GND: Power supply wiring
PTN: conductive patterns PL: conductive wiring

Claims (10)

Display panel;
A gate driver for supplying a gate signal to the display panel;
A data driver for supplying a data signal to the display panel;
Wirings formed in a non-display area of the display panel; And
And conductive patterns formed adjacent to the wirings in the non-display area of the display panel and having protrusions each having a corner or a vertex to induce static electricity introduced from the outside. The method according to claim 1,
The conductive patterns
And the second wiring is located outside, inside, outside, and inside of the wirings. The method according to claim 1,
The conductive patterns
And electrically connected by a conductive wiring having a wiring width that is thinner than the wiring. The method of claim 3,
The conductive wiring
And electrically connected to a pad or an electrode that transmits a voltage lower than a high potential voltage. The method according to claim 1,
The conductive patterns and the conductive wiring
And is melted or removed by the introduced static electricity. The method according to claim 1,
The conductive patterns
Spaced apart or adjacent to each other and being electrically floated. The method according to claim 1,
The conductive patterns
A triangular shape, a rectangular shape, a rhombic shape, a hexagonal shape, and a random shape, or a combination thereof. The method according to claim 1,
The conductive patterns
Wherein the wirings are formed along the wired path or formed in a part of the area. The method according to claim 1,
The conductive patterns
And N (N is an integer equal to or larger than 2) groups and is formed between the wirings. The method according to claim 1,
The wirings
And a signal wiring and a power wiring for transmitting signals to the gate driver and the display panel.

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