JP3457278B2 - Active matrix device and electronic device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit formed by using a thin film semiconductor element. In particular, like liquid crystal display devices and dynamic RAM (DRAM),
It has a matrix structure and M is used as its switching element.
An active matrix circuit having an OS type or MIS (metal-insulator-semiconductor) type field effect element (hereinafter collectively referred to as a MOS type element) and a drive circuit for driving the same are formed on the same substrate. The present invention relates to a monolithic active matrix device. In particular, the present invention relates to a device using a thin film semiconductor transistor formed on an insulating surface at a relatively low temperature as a MOS type element.

[0002]

2. Description of the Related Art Recently, in a display device such as a liquid crystal having a matrix structure, an insulating gate type semiconductor device having a thin film active layer (also called an active region), a so-called thin film transistor (TFT) is used for switching each pixel. The matrix circuits used, so-called active matrix circuits are being researched. Above all, an integrated type (monolithic type) active matrix device in which not only the active matrix circuit but also peripheral circuits for driving the same are formed on the same substrate by TFTs has been attracting attention. In the monolithic active matrix device, it is not necessary to connect a huge number of terminals, so that it is possible to increase the density of the matrix and it is expected that the manufacturing yield will be improved.

For such a purpose, it was necessary to use a TFT using crystalline silicon in the active layer. This is because the driving circuit is required to operate at a very high speed. In order to obtain such a TFT, the conventional semiconductor technology may be used as it is, but in that case, a material capable of withstanding a high temperature of 900 ° C. or higher was required as a substrate material. However, such a material is limited to quartz glass and the like, and the substrate cost is greatly increased in a large area.

When an inexpensive substrate is used,
The maximum temperature of the manufacturing process is lower, that is, 800 ℃
Hereafter, it was necessary to set the temperature to preferably 600 ° C. or lower. Also, even if there is room to use an expensive board,
Sometimes it was necessary to process at lower temperatures due to the heat resistance issues of the other materials that make up the circuit. Therefore, the active layer is crystallized from amorphous silicon by thermal annealing for a long time of 800 ° C. or lower, or optical annealing (laser annealing, etc.) that instantaneously crystallizes by irradiating strong light such as laser light. Used. Moreover, since the thermal oxide film used in the normal semiconductor process is not used as the gate insulating film,
A film made of silicon oxide, silicon nitride, silicon oxynitride, or the like was formed at a temperature of 800 ° C. or lower by a vapor deposition method such as a plasma CVD method, an atmospheric pressure CVD method, or a sputtering method.

On the other hand, in a TFT using non-single crystal silicon such as polycrystalline silicon, there has been a problem that the drain current (leakage current) is large when a reverse bias voltage is applied to the gate electrode. Regarding this point, the gate electrode does not overlap the drain (offset state)
It is known that a significant improvement can be achieved by designing such that Such a transistor is called an offset gate type transistor. However, it was impossible to realize such an offset state with good reproducibility by a photolithography process. JP-A-5-11
4724 and 5-267167 provide an answer to this problem, and as shown therein, by anodizing the gate electrode, the increment due to the anodization can be used successfully to form an offset. It was

Further, even if the offset electrode is not intended to cover the periphery of the gate electrode with the anodic oxide, the gate electrode is made of a material having insufficient heat resistance such as aluminum. In this case, there was an effect of suppressing the generation of hillocks in the subsequent heating process (for example, laser irradiation, a film forming process by the CVD method, etc.).

[0007]

The object of the invention is to, however, even if
For example, since the insulating film formed by the vapor deposition method has poor film quality and the interface between the surface of the silicon film and the gate insulating film is not good, the interface between the charge trap center (trap center) and silicon is poor. Many were present inside the insulating film.
In particular, there were many centers that captured electrons. As a result, when the TFT formed of such a material is used for a long time, many electrons are trapped in the trap center, which adversely affects the characteristics of the TFT.

Further, for example, the anodic oxide left for offset formation also has many trap levels,
In particular, aluminum oxide, which is an anodic oxide of aluminum, was easy to trap electrons. Due to such a problem, the characteristics are deteriorated by using the TFT for a long time. Specifically, in an N-channel TFT, a weak P-type region was formed at the boundary between the drain and the channel formation region by the trapped electrons as shown in FIG. 7A. This hinders the drain current in the N-channel TFT.

The formation of such a weak P type region was remarkable in the offset gate type TFT. This is because, when formed directly under the gate electrode, it was possible to reduce this region by the applied voltage of the gate electrode in the actual operation. However, when it occurs in the offset region, the influence of the gate electrode is small, and it is far from the drain region, and the region becomes completely uncontrollable. Further, for example, the anodic oxide formed around the gate electrode has the same problem. In particular, when the drain voltage is weak, the inversion layer (channel) that should originally extend from the source to the drain is blocked by this weak P-type region, and the drain voltage is low, so that carriers moving in the channel formation region are caused. (Because it is an N-channel type TFT, the speed of electrons) was also small, and the drain current was reduced as compared with the normal state.
(Fig. 7 (B))

When the drain voltage is sufficiently high, the inversion layer itself recedes toward the source side even in a normal state, and the electron velocity is also high. There was no problem, and the characteristics were the same as in the normal state. Such a phenomenon is caused by N-channel type T
This means a change in the threshold voltage of the FT. That is,
Applications that require stable threshold voltage, for example, switching elements of active matrix circuits,
Or, it means that it cannot be used for the analog switch element of the peripheral drive circuit. In the P-channel TFT, such trapped electrons only spread the region of the same conductivity type as the drain in the channel region, and as a result, the characteristic deterioration was not serious.

Therefore, if the circuit is a complementary circuit (CMOS) of an N-channel type TFT and a P-channel type TFT, there is a problem that the N-channel type TFT deteriorates due to long-term use and does not function as a complementary type circuit. It was
In a monolithic active matrix device ,
For example, analog switches are required at the output terminals of the active matrix circuit and the source driver, but the above problems must be taken into consideration when forming analog switches. Further, in a monolithic active matrix device , US Pat.
In the logic circuit of the peripheral drive circuit, such as 82395,
Although a CMOS circuit is used, it is also necessary to consider the above deterioration problem. The present invention is intended to provide an answer to such a difficult task.

That is, the silicon film surface of the TFT and the gate
The charge trap center (port) is formed at the interface with the edge film and inside the gate insulating film.
If a lap center occurs, the TFT characteristics are adversely affected.
Extend. Particularly, in the N-channel TFT, the charge trapping is performed.
The drain and chi
A weak P-type region is formed at the boundary of the channel formation region.
Be done. This is due to the
Current is disturbed and the characteristics are adversely affected. Therefore, CM
In the drive circuit using the OS circuit, the N-channel TFT
It is said that it does not function as a complementary circuit due to deterioration of characteristics.
There's a problem. Such a problem is caused especially in liquid crystal display devices and the like.
A material whose light transmittance and reflectivity change due to the effect of an electric field
And place these materials between the opposing electrodes.
Image by applying an analog electric field between it and the counter electrode.
An active matrix circuit for displaying and its
It has a peripheral circuit for driving it on the same substrate.
Product circuit, that is, a monolithic active matrix
First of all, in the device,
there were.

[0013]

[Means for Solving the Problems]

The first aspect of the present invention is to provide a matrix on the same substrate.
Pixels arranged in a stripe shape and using thin film transistors,
Shift using thin film transistor for driving the pixel
A thin film transistor formed on the substrate and having a resistor.
All the transistors are P-channel type, and the shift register
This thin film transistor is an enhancement type thin film transistor.
Transistor and depletion type thin film transistors
And the thin film transistor of the pixel is an enhancement
Type thin film transistor
Live matrix device. The second aspect of the present invention is the same substrate.
The thin film transistors arranged in a matrix on top
Pixel used and thin film transistor for driving the pixel
Has a shift register with a resistor, said substrate
All of the thin film transistors formed in
The shift register thin film transistor is
A thin film transistor of the pixel type,
Transistor is an enhancement type thin film transistor
An active matrix device characterized in that
It Note that the resistance is the pixel and the shift register.
Island thin film semiconductors to be the active layer of a thin film transistor
Simultaneously patterned using island-shaped thin film semiconductor
It may be made. The island-shaped thin film semiconductor is
Of the pixel and the thin film transistor of the shift register
The same concentration as that of the source and drain
It may contain a pure element. The island-shaped thin film semiconductor
The body is a thin film transistor of the pixel and the shift register.
With the same concentration as the source and drain of the transistor, with P type
A region containing an impurity element to give, and a concentration lower than the region
And a region containing an impurity element imparting P-type
You may stay. Incidentally, the pixel includes a pixel electrode, wherein
Contact with the source or drain of the pixel thin film transistor
Electrode and the pixel electrode are in contact with the surface of the same insulating film
And the electrode is in contact with the pixel electrode.
You may have. A third aspect of the present invention is that a thin film is formed on the same substrate.
Driving a DRAM using a transistor and the DRAM
To a shift register using a thin film transistor, the
The thin film transistor formed on the substrate has
P-channel type, thin film transistor of the shift register
Is an enhancement type thin film transistor or
And a depletion type of thin film transistor, before
The DRAM thin film transistor is an enhancement type.
Active thin film transistor
It is a matrix device. The fourth aspect of the present invention is on the same substrate.
And a DRAM using a thin film transistor and the DRA.
Shift using thin film transistor and resistor to drive M
A thin film transistor formed on the substrate and having a resistor.
All the transistors are P-channel type, and the shift register
The thin film transistor of the star is an enhancement type thin film.
A transistor, a thin film transistor of the DRAM
Is an enhancement type thin film transistor
Is an active matrix device. In addition,
The resistance of the DRAM and the shift register is
Simultaneously with the island-shaped thin film semiconductor that becomes the active layer of the thin film transistor
Is formed using an island-shaped thin film semiconductor that is patterned into
May be. The island-shaped thin film semiconductor is the DRAM
And the source of the thin film transistor of the shift register
And an impurity source that imparts P-type with the same concentration as the drain
It may contain elements. In addition, the island-shaped thin film semiconductor,
Thin film transistor of the DRAM and the shift register
Add P-type with the same concentration as the source and drain of the star
Area containing the impurity element and
And a region containing an impurity element imparting P-type
May be. In addition, using the active matrix device
It may be an electronic device characterized by the above. In addition, before
A CMOS type semiconductor chip is used for the active matrix device.
An electronic device characterized in that
Yes.

[0015]

According to the first to fourth aspects of the present invention, an actuator is mounted on the same substrate.
And Restorative matrix circuit, the active matrix circuit
And a shift register for driving, formed on the substrate.
All thin film transistors are P-channel type
It is an active matrix device. Active matri
Pixel circuits or DRs arranged in a matrix.
AM.

In the P-channel type thin film transistor,
The electrons trapped by the trap center are trapped in the channel region.
Only by expanding the area of the same conductivity type as rain,
Degradation is not a serious problem.

The first and third aspects of the present invention are shift registers.
As a P-channel type thin film transistor that constitutes a
Enhancement type thin film transistor and depletion
Both types of thin film transistors are used.
Instrument type thin film transistor only
The number of power supply lines can be smaller than that of transistors.

The second and fourth aspects of the present invention are shift registers.
The enhancement type thin film transistor and resistor
The thin film transistor of the enhancement type
Compared to a shift register consisting of only transistors,
The number can be reduced.

[0019]

EXAMPLES [Example 1] An example in which a monolithic liquid crystal display is manufactured using the present invention will be described. FIG. 8 shows a block diagram of the monolithic liquid crystal display of this embodiment. TFTs used in the element circuits that make up the liquid crystal display, that is, shift registers X (for source driver) and Y (for gate driver), source driver analog switches, analog buffers, and active matrix circuits are all P-channel. It is a type. FIG. 5 shows the shift register (1
Shows a circuit diagram of (stage).

In this circuit, the power supply line is
Three of V _DD , V _SS and V _GG are required. In this case, V _DD
> V _SS . The optimum value of V _GG is determined in consideration of the TFT characteristics, and is preferably about V _SS or
Below that. A circuit manufacturing process of such a monolithic liquid crystal display will be described below with reference to FIG. As the substrate, it is desirable to use low alkali glass such as Corning No. 7059 or NH Techno Glass Co. NA35 or NA45, or non-alkali glass. The substrate may be subjected to an appropriate heat treatment in order to prevent it from shrinking in the heating step of the TFT manufacturing process. On this substrate 101, a silicon oxide film 102 having a thickness of 100 to 500 nm , for example, 200 nm was deposited as a base film.

Further, the thickness is 30 to 150 nm , for example,
Deposit an amorphous silicon film of 50 nm , and
It was crystallized by performing a thermal annealing treatment at 600 ° C. At this time, a small amount of a metal element such as nickel that promotes crystallization may be added to lower the crystallization temperature and further shorten the thermal annealing time. For example, when nickel is mixed at 1 × 10 ¹⁸ atoms / cm ³ or more, 5
Crystallization was completed at 50 ° C for 4 to 8 hours. After the crystallization step, the crystallinity may be improved by irradiating a laser or strong light equivalent thereto.

Of course, in this crystallization step, the amorphous silicon film may be crystallized by irradiating a laser or intense light equivalent thereto, that is, so-called optical annealing.
Then, the crystallized silicon film was etched to form island regions 103, 104, and 105. Here, the regions 103 and 104 are used for TFTs forming a peripheral driving circuit (source driver or gate driver), and the region 105 is used for a TFT forming an active matrix circuit. Then, a silicon oxide film 106 having a thickness of 100 to 150 nm , for example, 120 nm was deposited by the plasma CVD method, and this was used as a gate insulating film. Further, an aluminum film is formed by sputtering to 30
The gate electrodes 107, 108, and 109 were formed by depositing 0 to 800 nm , for example, 500 nm , and etching this. (Fig. 1 (A))

Thereafter, a voltage is applied to the gate electrodes 107 to 109 in an electrolytic solution under the same conditions as in JP-A-5-114724 or 5-267167, and the side surfaces and the top surface of the gate electrodes are coated with anodic oxide films 110 and 111. , 112
Was formed. The thickness of the anodic oxide is 150 to 300 nm ,
For example, it is set to 200 nm . Further, this thickness is T used for the TFT used for the shift register and the analog buffer.
FT, TFT used for active matrix circuit, T, etc.
It could have been different depending on the purpose of the FT. This is because the thickness of the anodic oxide is a factor that determines the width of the offset region as described in JP-A-5-114724, and the TFT characteristics differ depending on the difference in offset width. (Fig. 1 (B))

Then, after dividing the wiring connected to the gate electrode as needed, the entire surface was doped with boron by an ion doping method (also called a plasma doping method). As the doping device, a device manufactured by Nissin Electric Co. was used. The dose amount at this time is 2 × 10 ^{14 to} 5 × 1
It was set to 0 ¹⁵ atoms / cm ² , for example, 5 × 10 ¹⁴ atoms / cm ² . Further, the accelerating voltage is 30 to 80 kV, for example, because it is necessary to be injected into the silicon film through the gate insulating film.
It was set to 65 kV. After the doping, the entire surface was irradiated with laser light to activate the doped boron. A KrF or XeCl excimer laser was used as the laser. Laser energy density is 15
It was set to 0 to 350 mJ / cm ² , for example, 200 mJ / cm ² . At this time, if the substrate is heated to 200 to 400 ° C.,
It had the effect of lowering the energy density of the laser.
In this way, the P-type regions (source / drain) 113 in which the silicon regions 103 to 105 are self-aligned with boron using the gate electrode and the anodic oxide as a mask,
114 and 115 were formed. (Fig. 1 (C))

After that, a layer having a thickness of 3 is formed on the entire surface as an interlayer insulator.
A silicon oxide film or a silicon nitride film 116 having a thickness of 00 to 800 nm , for example, 500 nm is deposited. Furthermore, the thickness is 50 to 150 nm , for example, 50 by a sputtering method.
nm transparent conductive coating, such as an indium tin oxide coating (ITO) was deposited. Then, this was etched to form pixel electrodes 117 in the active matrix circuit region (pixel region). (Fig. 1 (D)) After that, each T
Contact holes are formed in the source / drain of the FT and a gate electrode (not shown), and electrodes / wirings 118, 1 are formed by a multilayer film of a titanium nitride film and an aluminum film.
19, 120, 121 and 122 were formed. As described above, the TFTs 123 and 124 in the peripheral driving circuit area (see FIG.
(See FIG. 8) and the TFT 125 (see FIG. 8) in the pixel region. All of these TFTs are P-channel type.
(Fig. 1 (E))

Example 2 An example of producing a monolithic liquid crystal display using the present invention will be described. The block diagram of the monolithic liquid crystal display of this embodiment is the same as that of the first embodiment (FIG. 8). FIG. 6 shows a circuit diagram of the shift register (one stage) of this embodiment. In this embodiment, all the TFTs are of P-channel type, but in addition to enhancement type TFTs, depletion type T is used as a load.
The feature is that FT is also used. In this circuit, only two power supply lines, V _DD and V _SS , are required as the power supply line.
V _GG is not required. Therefore, it is preferable in terms of circuit integration. In addition, the operating speed is generally higher than that of the first embodiment. _Again , V _DD > V _SS .

A circuit manufacturing process of such a monolithic liquid crystal display will be described below with reference to FIGS. Non-alkali glass was used as the substrate. This board 2
As a base film, a silicon oxide film 202 having a thickness of 100 to 500 nm , for example, 200 nm was deposited on 01. Further, an amorphous silicon film 203 having a thickness of 30 to 150 nm , for example, 50 nm , which has the lowest possible concentration of an element that imparts conductivity, such as boron or phosphorus, is deposited , and a thickness of 100 to 300 nm , for example, is deposited thereon . , A 200 nm thick silicon oxide film 204 was deposited. And photoresist 2
Masked with 05. This is because the silicon oxide film 204 prevents the surface of the amorphous silicon film from being roughened by the step of implanting boron ions.

Then, boron was selectively implanted into the silicon film by an ion doping method or an ion implantation method (ion implantation method). Here, using the ion doping method, boron is implanted at an acceleration voltage of 65 kV and a dose amount of 1 × 10 ¹³ to 2 × 10 ¹⁴ atoms / cm ² to form a weak P-type region 206. A depletion type TFT is formed in this region. (Fig. 2 (A))
After that, the photoresist mask 205 and the silicon oxide film 204 were removed, and the amorphous silicon film 202 was crystallized by a process such as thermal annealing or laser irradiation.

Then, the crystallized silicon film was etched to form island regions 207, 208 and 209.
Here, the regions 207 and 208 are used for TFTs forming a peripheral driving circuit (source driver or gate driver), and the region 209 is used for a TFT forming an active matrix circuit. Furthermore, the area 207
Is a depletion type TFT, and regions 208, 20
9 is used for an enhancement type TFT. afterwards,
A gate insulating film is deposited, and gate electrodes 210 and 21 whose side surfaces and upper surface are covered with anodic oxide as in Example 1 are formed.
1, 212 was formed. (Fig. 2 (B))

Then, after dividing the wiring connected to the gate electrode as needed, the entire surface was doped with boron by an ion doping method. The dose amount at this time was 5 × 10 ¹⁴ atoms / cm ² . The acceleration voltage was set to 65 kV. After the doping, the entire surface was irradiated with laser light to activate the doped boron. Thus, the P-type regions (source / drain) 21 in which the silicon regions 207 to 209 are implanted with boron in a self-aligned manner using the gate electrode and the anodic oxide as a mask.
3, 214, 215 were formed. (FIG. 2C) After that, a 500 nm thick silicon oxide film or silicon nitride film 216 is deposited on the entire surface as an interlayer insulator, and a pixel is formed in the active matrix circuit region (pixel region) by a transparent conductive film. The electrode 217 was formed. (Fig. 2 (D))

Then, a contact hole is formed in the source / drain gate electrode / wiring of each TFT, and the electrode / wiring 21 is formed by a multilayer film of a titanium nitride film and an aluminum film.
8, 219, 220, 221, 222 were formed. As described above, the TFTs 223 and 224 in the peripheral drive circuit area
(See FIG. 6) and the TFT 225 in the pixel region are formed. Although all of these TFTs are P-channel type,
Reference numeral 223 denotes a depletion type transistor which is a P type having a weak channel formation region. On the other hand, the TFTs 224 and 225 are enhancement type transistors in which the channel formation region is intrinsic or substantially intrinsic.
(Fig. 2 (E))

Example 3 An example of producing a monolithic liquid crystal display using the present invention will be described. The block diagram of the monolithic liquid crystal display of this embodiment is the same as that of the first embodiment (FIG. 8). FIG. 4 shows a circuit diagram of the shift register (one stage) of this embodiment. In this embodiment, all TFTs are of P-channel type, but the feature is that a resistor is used as a load. In this circuit as well, as in the second embodiment, only two power supply lines, V _DD and V _SS , are required. In addition, the operating speed is generally higher than that of the first embodiment. _Again , V _DD > V _SS . A cross-sectional view of such a circuit is shown in FIG. These circuits are the first embodiment.
And the integrated circuit manufacturing technique described in the second embodiment. The details are omitted here.

In FIG. 3A, a region 301 is a resistor, a region 302 is a TFT of a peripheral drive circuit, and a region 303.
Is a TFT in the pixel area. The resistor 301 uses an intrinsic silicon region as a resistor. To form such a resistance, the TFT 123 shown in FIG. 1 may be doped to form the source / drain, and then the gate electrode thereof may be removed. However, in this case, since intrinsic silicon is used as the resistor, the resistance value is generally large, and is usually 1 MΩ or more. Therefore, there is a problem that the operation speed of the circuit is slow.

In FIG. 3B, a region 304 is a resistor, a region 305 is a TFT of a peripheral driving circuit, and a region 306.
Is a TFT in the pixel area. The resistor 304 uses a weak P-type silicon region as a resistor. To form such a resistor, the source / source of the TFT 223 shown in FIG.
After doping to form the drain,
The gate electrode may be removed. Weak P in this case
Since type silicon is used as a resistor, the resistance is usually about 100 kΩ.

In FIG. 3C, a region 307 is a resistor, a region 308 is a TFT of a peripheral driving circuit, and a region 309.
Is a TFT in the pixel area. The resistor 307 uses a P-type silicon region as a resistor. In order to form such a resistance, the gate electrode may be removed during the process of forming the TFT 123 shown in FIG. 1 and then boron doping may be performed. However, in this case, since P-type silicon is used as the resistor, the resistance value is generally small and usually 10 kΩ or less. Therefore, there is a problem that the power consumption of the circuit is large.

To form the structure of FIG. 3C,
Gate electrode formation / anodization process (see, for example, FIG.
Since there is a step of dividing the wiring connected to the gate electrode between (B)) and the step of boron doping (FIG. 1C), it may be performed at the same time. However, FIG.
In order to form the structures of (A) and (B), the gate electrode must be removed after doping, which increases the number of photolithography steps by one.

[Embodiment 4] The above Embodiments 1 to 3 relate only to the monolithic active matrix liquid crystal display. Of course, a more sophisticated system can be constructed using the active matrix liquid crystal display thus formed. FIG. 9 shows a block diagram of such a system.

In the example of FIG. 9, by fixing a semiconductor chip mounted on a main board of an ordinary computer on at least one substrate of a liquid crystal display having a structure in which a liquid crystal is sandwiched between a pair of substrates, This is an example of downsizing, weight reduction, and thinning. In particular, these chips are mounted on a substrate with active matrix circuits. In the present invention, since only the P-channel type TFT is used for the active matrix circuit and its peripheral driving circuit, there is a drawback that the power consumption becomes large as compared with the case of using a normal CMOS type peripheral driving circuit. Therefore, in such a system, it is necessary to reduce the power consumption by using CMOS chips for the chips other than the liquid crystal display panel. A substrate having an active matrix circuit has the monolithic active matrix circuit of the present invention.

Hereinafter, FIG. 9 will be described. The substrate 15 is also the substrate of the liquid crystal display, and the TFT is formed on it.
(11) The active matrix circuit 14 in which a large number of pixels each including the pixel electrode 12 and the auxiliary capacitance 13 are formed, the X decoder / driver, the Y decoder / driver, and the XY branch circuit for driving the active matrix circuit 14 are formed by TFTs. ing.

However, in the present invention, on the substrate 15,
Attach another chip. Then, these chips are connected to the circuit on the substrate 15 by means such as a wire bonding method or a COG (chip on glass) method. In FIG. 9, correction memory, memory, CP
U and the input port are chips attached in this way, and various chips may be attached in addition to this.

In FIG. 9, the input port is a circuit for reading a signal input from the outside and converting it into an image signal. The correction memory is a memory unique to the panel for correcting an input signal and the like according to the characteristics of the active matrix panel. In particular, this correction memory has information unique to each pixel as a non-volatile memory,
It is for individual correction. That is, when a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the pixel has the same brightness as the surrounding pixels. Since the pixel defect information is different for each panel, the information stored in the correction memory is different for each panel.

The CPU and the memory have the same functions as those of an ordinary computer, and in particular, the memory has an image memory corresponding to each pixel as a RAM. All of these chips are CMOS type.

FIG. 10 shows an example of a concrete configuration of the present invention. A substrate 19 is provided so as to face the substrate 20, and a liquid crystal is sandwiched between them. Further, on the substrate 20, an active matrix circuit 21 and peripheral drive circuits 22, 23 and 24 for driving the active matrix circuit 21 are configured by using TFTs. The main memory chip 26, MPU (micro arithmetic circuit) 2 is formed on the surface on which these circuits are formed.
7. The correction memory 28 was adhered and each chip was connected to the circuit on the substrate 20. For example, when chips are connected by the COG (chip on glass) method, the substrate 20
Wirings such as 29 shown in FIG.
5 formed.

As the specific contact shape, the shape shown in FIG. 11 or 12 was used. In the method of FIG. 11, the wiring 31 on the substrate 30 and the conductive protrusions (bumps) 34 provided on the electrode portion 33 of the chip 32 are brought into contact with each other, and the substrate 30 and the chip 32 are fixed with the organic resin 35. . As the bump, gold formed by electroless plating may be used.

In the method of FIG. 12, the substrate 40 and the chip 42 are
The substrate and the chip are bonded with an organic resin in which conductive particles (for example, gold particles) 44 are dispersed between
The circuit was connected by the contact between the upper wiring 41 and the conductive particles 44 existing between the electrode portions 43 of the chip 42. As the organic resin used for adhesion, a photocurable or thermosetting resin or a natural curable resin was used. The liquid crystal may be injected into the liquid crystal display after the chip is bonded.

Through these steps, even a CPU and a memory were formed on the liquid crystal display substrate, and a single substrate could constitute an electronic device such as a simple personal computer. Further, a known wire bonding method may be used as a chip connecting method. Implementation
In Examples 1 to 4, the monolithic active mat is used.
We were able to improve the reliability of the ricks machine. Other
Active matrix device using ordinary CMOS circuit
Effect of process simplification compared with the case of forming
There is also. For example, in the first embodiment, a CMOS is formed.
Compared to the case where
Eliminates photolithography process and N-type impurity implantation process
Abbreviated. However, in Example 2, weak P
A photolithography process to form the mold region
Since each doping step is required once,
Requires the same number of steps as when forming a CMOS
It However, as a doping mask, the photo
Use a resist, etc., and do not apply a high dose of ions.
When pinged, the photoresist is carbonized and removed.
Difficult to operate, and usually requires a long ashing process.
However, in the case of the second embodiment, the
The dose itself is small, and the silicon oxide film 204 (FIG. 2) is removed.
The photoresist 205 by etching
It can be removed by the soft-off method. For this reason, normal CM
Compared to OS process, photoresist after doping
The mask removal process is easy.

[0047]

According to the present invention, the active matrix is formed on the same substrate.
Drives trix circuit and active matrix circuit
A thin film having a shift register and formed on the substrate
All transistors are P-channel type
Live matrix device. P-channel thin film transistor
In the transistor, since the deterioration of the characteristics does not become a serious problem,
Possible to improve the reliability of the active matrix device Ru can <br/>. The present invention relates to a P channel which constitutes a shift register.
Enhancement type thin film transistor
Thin film transistor and depletion type thin film transistor
Enhancement type by using both
The shift register consisting only of thin film transistors of
Since the number of source lines can be reduced, the shift register circuit
Can be integrated. Also, the operation of the shift register
The speed can be increased. In addition, the present invention
Resistor enhancement type thin film transistor and resistor
By configuring the
Power supply rather than shift register consisting of only film transistors
Since the number of lines can be reduced, the shift register
The path can be integrated and the shift register
The operating speed can be increased. Furthermore, the resistance value of the resistor
Power consumption and operating speed
A lanced shift register is obtained.

As described above, the present invention is industrially useful.

[Brief description of drawings]

FIG. 1 shows an outline of a cross section of an integrated circuit manufacturing process according to a first embodiment .

2A to 2C show an outline of a cross section of an integrated circuit manufacturing process of Example 2. FIG.

FIG. 3 shows an outline of a cross section of an integrated circuit of Example 3 .

FIG. 4 is a circuit diagram of a shift register used in the integrated circuit of the third embodiment .

FIG. 5 shows a circuit diagram of a shift register used in the integrated circuit of the first embodiment .

FIG. 6 is a circuit diagram of a shift register used in the integrated circuit of the second embodiment .

FIG. 7 illustrates deterioration of a conventional N-channel TFT.

FIG. 8 shows a block diagram of a monolithic liquid crystal display of the present invention.

FIG. 9 shows a block diagram of a system of Example 4.

FIG. 10 shows the configuration of the fourth embodiment.

FIG. 11 shows a configuration example of the COG method in the fourth embodiment.

FIG. 12 shows a configuration example of the COG method in the fourth embodiment.

[Explanation of symbols]

101 .. Substrate 102 .. Base films 103, 104 .. Island silicon region (for peripheral drive circuit) 105 ..... Island silicon region (for pixel circuit) 106. ... Gate insulating films 107, 108 ... Gate electrode (for peripheral drive circuit) 109 ... Gate electrode (for pixel circuit) 110-112 ... Anodic oxide coating 113-115 ... P Mold region 116 ... Interlayer insulator 117 ... Pixel electrodes 118 to 122 ... Electrode / wiring

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 27/108 H01L 21/8242 G02F 1/1368

Claims (13)

(57) [Claims] 1. Use of thin film transistors arranged in a matrix on the same substrate .
Pixel and shift using thin film transistor for driving the pixel
Includes a register, a thin film transistor formed on the substrate is whole by P-channel type thin film transistor of the shift register is enhanced main <br/> cement type thin film transistor and the depletion type thin film transistor, the pixel of the thin film transistor active matrix device, characterized in that an enhancement type TFT. 2. Use of thin film transistors arranged in a matrix on the same substrate .
Pixel, using a thin film transistor and a resistor for driving the pixel
Includes a shift register, a thin film transistor formed on the substrate is whole by P-channel type thin film transistor of the shift register is enhanced main <br/> cement type thin film transistor, the thin film transistor of the pixel enhancement Type thin film transistor , an active matrix device characterized by the above-mentioned. 3. The thin film according to claim 2, wherein the resistor is a thin film of the pixel and the shift register.
At the same time as the island-shaped thin film semiconductor that becomes the active layer of the transistor,
It is formed using an island-shaped thin film semiconductor that is turned.
And an active matrix device. 4. The island-shaped thin film semiconductor according to claim 3 , wherein the pixel and the shift register are
Same as source and drain of thin film transistor
Characterized by containing an impurity element imparting P-type at a concentration
Active matrix device. 5. The island-shaped thin film semiconductor according to claim 3 , wherein the pixel and the shift register are
Same as source and drain of thin film transistor
A region containing an impurity element imparting P-type at a concentration,
A region containing an impurity element imparting P-type at a concentration lower than that of the region
And an active matrix characterized by
apparatus. 6. The odor according to any one of claims 1 to 5.
The pixel has a pixel electrode, and a source or a drain of the thin film transistor of the pixel.
The contacting electrode and the pixel electrode are on the same insulating film surface.
The electrodes are arranged in contact with each other, and the electrodes are the pixel electrodes.
Active matrix device characterized by being in contact with
Place 7. A same substrate, using a DRAM using a thin film transistor to drive the DRAM, the thin film transistors
Includes a shift register, a thin film transistor formed on the substrate is whole by P-channel type thin film transistor of the shift register is enhanced main <br/> cement type thin film transistor and the depletion type thin film transistor, the active matrix device TFT of the DRAM, which is a enhancement type TFT. 8. A DRAM using a thin film transistor, and a thin film transistor and a resistor for driving the DRAM on the same substrate .
Has had a shift register with a thin film transistor formed on the substrate is whole by P-channel type thin film transistor of the shift register is enhanced main <br/> cement type thin film transistor, the thin film transistor of the DRAM is An active matrix device characterized by being an enhancement type thin film transistor. 9. The resistor according to claim 8, wherein the resistor is one of the DRAM and the shift register.
Simultaneously with the island-shaped thin film semiconductor that becomes the active layer of the thin film transistor
Is formed using an island-shaped thin film semiconductor that is patterned into
An active matrix device characterized in that 10. The island-shaped thin film semiconductor according to claim 9, wherein the island-shaped thin film semiconductor is the DRAM and the shift.
With the source and drain of the thin film transistor of the register
It has the same concentration and contains an impurity element that imparts P-type.
Active matrix device to collect. 11. The island-shaped thin film semiconductor according to claim 9, wherein the island-shaped thin film semiconductor is the DRAM and the shift.
With the source and drain of the thin film transistor of the register
A region containing an impurity element imparting p-type at the same concentration,
An impurity element which imparts P-type is contained at a concentration lower than that of the region
The active matrix is characterized by
Equipment. 12. An electronic device using the active matrix device according to claim 1. Description: 13. The method according to any one of claims 1 to 11.
Electronic device characterized by CMOS-type semiconductor chips are connected to the active matrix device according.