JPH10223903A - Thin-film transistor, manufacture of the same, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display device capable of preventing lower yield and generation of defective display. SOLUTION: A surface of polycrystalline silicon film 11 becoming an active layer of a TFT(thin-film transistor) 106 is flat, and its thickness corresponding to a drain region 82 and a source region 83 is thicker than the thickness corresponding to a channel region 93. The grain size in every part of the polycrystalline silicon film 11 is nearly uniform and this makes an element characteristic of the TFT106 uniform. This also optimizes a sheet resistance of each region, 82a and 83a, and makes an ON-current of the TFT106 uniform. This resultingly prevents lower yield and generation of defective display.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a thin film transistor,
The present invention relates to a method for manufacturing a thin film transistor and a display device.

[0002]

2. Description of the Related Art In recent years, thin film transistors (TFTs) have been developed.
Active matrix liquid crystal display (LCD; Liquid Crystal Displ) using Film Transistor
ay) has attracted attention as a high-quality display device.

In the active matrix method, a pixel driving element (active element) and a signal storage element (pixel capacitance) are integrated in each pixel arranged in a matrix, and each pixel performs a kind of storage operation to prepare a liquid crystal. This is a static drive method. That is, the pixel driving element functions as a switch whose on / off state is switched by the scanning signal. Then, the data signal (display signal) is transmitted to the display electrode via the pixel drive element in the ON state,
The liquid crystal is driven. Thereafter, when the pixel driving element is turned off, the data signal applied to the display electrode is stored in the signal storage element in a state of electric charge, and the liquid crystal is continuously driven until the pixel driving element is turned on next. Therefore, even if the number of scanning lines increases and the driving time allocated to one pixel decreases, the driving of the liquid crystal is not affected and the contrast does not decrease.

As a pixel driving element, a TFT is generally used. In a TFT, a semiconductor thin film formed on an insulating substrate is used as an active layer. Commonly used active layers are an amorphous silicon film and a polycrystalline silicon film.
A TFT using an amorphous silicon film as an active layer is called an amorphous silicon TFT, and a TFT using a polycrystalline silicon film is used.
The FT is called a polycrystalline silicon TFT. Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than amorphous silicon TFTs. Therefore, the polycrystalline silicon TFT can be used not only as a pixel driving element but also as an element forming a logic circuit. Therefore, if a polycrystalline silicon TFT is used, not only a pixel portion but also a peripheral drive circuit portion disposed therearound can be integrally formed on the same substrate. That is, a polycrystalline silicon TFT as a pixel driving element arranged in the pixel portion and a polycrystalline silicon TFT forming the peripheral driving circuit portion are formed in the same process.

FIG. 10 shows a block configuration of a general active matrix type LCD. In the pixel portion (liquid crystal panel) 101, each scanning line (gate wiring) G1... Gn, Gn +
1 ... Gm and each data line (drain wiring) D1 ... Dn, Dn +
1... Dm. Each gate wiring G1 to Gm
And the drain wirings D1 to Dm are orthogonal to each other, and a pixel 102 is provided at the orthogonal portion. Each of the gate lines G1 to Gm is connected to a gate driver 103 so that a gate signal (scanning signal) is applied. Each of the drain wirings D1 to Dm is connected to a drain driver (data driver) 104 so that a data signal (video signal) is applied. By these drivers 103 and 104, the peripheral drive circuit unit 10
5 are configured. Then, each of the drivers 103 and 10
An LCD in which at least one of the four is formed on the same substrate as the pixel portion 101 is generally called a driver-integrated (built-in driver) LCD. Note that the gate driver 103 may be provided on both sides of the pixel portion 101 in some cases. In addition, the drain driver 104 is
May be provided on both sides.

FIG. 11 shows an equivalent circuit of the pixel 102 provided at a portion orthogonal to the gate line Gn and the drain line Dn. The pixel 102 has a TFT as a pixel driving element
106, a liquid crystal cell LC and an auxiliary capacity (storage capacity or additional capacity) SC. The gate wiring Gn has T
The gate of the FT 106 is connected, and the drain of the TFT 106 is connected to the drain wiring Dn. And T
The display electrode (pixel electrode) of the liquid crystal cell LC and the storage capacitor SC are connected to the source of the FT. The liquid crystal cell LC and the storage capacitor SC constitute the signal storage element. The voltage Vcom is applied to the common electrode (the electrode on the opposite side of the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitor SC, an electrode (hereinafter, referred to as a storage electrode) on the opposite side to an electrode (hereinafter, referred to as a storage electrode) connected to the source of the TFT.
A constant voltage VR is applied to the storage capacitor electrode. The common electrode of the liquid crystal cell LC is an electrode which is literally common to all the pixels 102. Further, a capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. The auxiliary capacitance electrode of the auxiliary capacitance SC may be connected to the adjacent gate line Gn + 1 in some cases.

In the pixel 102 thus configured, when the gate line Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT 106, the TFT 106 is turned on.
Then, with the data signal applied to the drain wiring Dn,
The capacitance of the liquid crystal cell LC and the auxiliary capacitance SC are charged. Conversely, the gate line Gn is set to a negative voltage to
When a negative voltage is applied to the gate of No. 6, the TFT 106 is turned off, and the voltage applied to the drain wiring Dn at that time is held by the capacitance of the liquid crystal cell LC and the auxiliary capacitance SC. As described above, by supplying a data signal to be written to the pixel 102 to the drain wirings D1 to Dm and controlling the voltages of the gate wirings G1 to Gm, the pixel 10
2 can hold an arbitrary data signal.
The transmittance of the liquid crystal cell LC changes according to the data signal held by the pixel 102, and an image is displayed.

Here, important characteristics of the pixel 102 include a writing characteristic and a holding characteristic. What is required for the writing characteristics is that a desired video signal voltage is sufficiently written to the signal storage elements (the liquid crystal cell LC and the storage capacitor SC) within a unit time determined from the specifications of the pixel portion 101. Is that it can be done. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitor SC is provided to increase the capacitance of the signal storage element and improve the holding characteristics. That is, due to its structure, the liquid crystal cell LC has a limit in increasing the capacitance. Therefore, the shortage of the capacitance of the liquid crystal cell LC is compensated for by the auxiliary capacitance SC.

FIG. 12 shows a schematic cross section of a pixel 102 (pixel portion 101) in a conventional LCD having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as the TFT 106.

A liquid crystal layer 73 filled with liquid crystal is formed between the transparent insulating substrates 71 and 72 facing each other. A display electrode 74 of the liquid crystal cell LC is provided on the transparent insulating substrate 71 side, and a common electrode 75 of the liquid crystal cell LC is provided on the transparent insulating substrate 72 side.
3 are opposed to each other.

On the surface of the transparent insulating substrate 71 on the liquid crystal layer 73 side, a gate electrode 76 of a TFT 106 constituting a gate wiring Gn is formed. On the gate electrode 76 and the transparent insulating substrate 71, a lower silicon nitride film 78
A gate insulating film 80 having a two-layer structure of a silicon oxide film 79 and an upper silicon oxide film 79 is formed. On the gate insulating film 80, a polycrystalline silicon film 81 serving as an active layer of the TFT 106 is formed.
Are formed. The polycrystalline silicon film 81 has a TFT
A drain region 82 and a source region 83 of 106 are formed. The TFT 106 is an LDD (Lightly Dope
d Drain) structure, the drain region 82 and the source region 83 are composed of low concentration regions 82a and 83a and high concentration regions 82b and 83b, respectively. A channel region 93 is formed between the drain region 82 and the source region 83 in the polycrystalline silicon film 81.

In a portion of the transparent insulating substrate 71 adjacent to the TFT 106, an auxiliary capacitor SC is formed in the same step as the TFT 106 is formed. Transparent insulating substrate 7
The storage capacitor electrode 77 of the storage capacitor SC is formed on the surface of the liquid crystal layer 1 on the liquid crystal layer 73 side. A dielectric film 84 is formed on the auxiliary capacitance electrode 77, and a storage electrode 85 of the auxiliary capacitance SC is formed on the dielectric film 84. The auxiliary capacitance electrode 77 has the same configuration as the gate electrode 76 and is formed in the same step. Further, the dielectric film 84 is formed on the extension of the gate insulating film 80 and is formed in the same configuration and in the same process as the gate insulating film 80. The storage electrode 85 is formed on the polycrystalline silicon film 81 and is connected to the source region 83 of the TFT 106.

A stopper layer 94 made of a silicon oxide film is formed on each of the channel region 93 and the storage electrode 85 in the polycrystalline silicon film 81. On the TFT 106 including the stopper layer 94 and the storage capacitor SC, an interlayer insulating film 88 having a two-layer structure of a lower silicon oxide film 86 and an upper silicon nitride film 87 is formed. High concentration region 82b constituting drain region 82
Represents a contact hole 89 formed in the interlayer insulating film 88
Through the drain electrode 9 forming the drain wiring Dn
0 is connected. A planarization insulating film 91 is formed on the drain electrode 90 and the interlayer insulating film 88.
The display electrode 74 is formed on the planarization insulating film 91. The display electrode 74 is connected to the high-concentration region 83b forming the source region 83 via a contact hole 92 formed in the planarization insulating film 91 and the interlayer insulating film 88. The drain electrode 90 is a lower molybdenum layer 90.
a and an upper aluminum alloy layer 90b.
The material of the display electrode 74 is ITO (Indium Tin).
Oxide) is used.

On the surface of the transparent insulating substrate 72 on the liquid crystal layer 73 side, red, green, and blue (RGB; Red;
Green Blue) are provided. A black matrix 96 as a light shielding film is provided between the color filters 95 of the respective colors. Above the display electrode 74, a color filter 95 of any one of RGB is disposed. In the upper part of the TFT 106,
A black matrix 96 is arranged.

Next, the conventional LC constructed as described above is used.
The method of manufacturing the pixel 102 (pixel unit 101) in D will be described sequentially. Step 1 (see FIG. 13A): A chromium film 61 is formed on the transparent insulating substrate 71 by using a sputtering method.

Step 2 (see FIG. 13B); chromium film 6
A resist pattern 62 for forming a gate electrode 76 and an auxiliary capacitance electrode 77 is formed on the substrate 1. Step 3 (see FIG. 13C): The chromium film 61 is etched using a wet etching method using the resist pattern 62 as an etching mask, so that the gate electrode 76 and the auxiliary capacitance electrode 77 made of the chromium film 61 are formed.
To form

At this time, since the etchant enters the interface between both ends of the resist pattern 62 and the chromium film 61, an undercut 61a occurs in the chromium film 61 located at both ends of the resist pattern 62. Due to the undercut 61a generated in the chromium film 61, the cross-sectional shape of the gate electrode 76 and the auxiliary capacitance electrode 77 becomes a tapered shape in which the center is flat and both ends are inclined. In the following description, a flat portion at the center of the gate electrode 76 will be referred to as a flat portion 76a.
, And the inclined both ends are referred to as a tapered portion 76b.

Step 4 (see FIG. 13D); Plasma C
Using a VD (Chemical Vapor Deposition) method, a silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are continuously formed on each of the electrodes 76 and 77 and the transparent insulating substrate 71. As a result, a gate insulating film 80 including the films 78 and 79 is formed, and a device structure in which the amorphous silicon film 63 is formed thereon is obtained.

Next, annealing (processing temperature; about 400 ° C.) is performed to perform dehydrogenation processing for removing hydrogen taken in the amorphous silicon film 63. Subsequently, the surface of the amorphous silicon film 63 is irradiated with excimer laser light, so that the amorphous silicon film 63 is heated and crystallized to form a polycrystalline silicon film 81. As described above, the laser annealing method using excimer laser light is an ELA (Excimer La
ser Anneal) method.

Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 81, and the respective members shown in FIG. 12 are formed, thereby completing the pixel portion 101 including the pixels 102.

Incidentally, the gate electrode 76 has a tapered portion 76.
The b is provided because the gate insulating film 80 and the dielectric film 84 are provided.
This is for ensuring the withstand voltage of the semiconductor device. That is, when the gate electrode 76 does not have the tapered portion 76b, the gate electrode 7
6 tends to cause electrolytic concentration. If the gate electrode 76 does not have the tapered portion 76b, the gate electrode 7
The step coverage of the gate insulating film 80 located on the corners at both ends of the gate electrode 6 is deteriorated, and the thickness of the gate insulating film 80 in that portion is reduced. As a result, the withstand voltage of the gate insulating film 80 at the end of the gate electrode 76 may be reduced.
When the tapered portion 76b is provided in the gate electrode 76, the concentration of the electrolysis at the end of the gate electrode 76 is reduced, and the step coverage of the gate insulating film 80 at the end of the gate electrode 76 is improved. The thickness of the gate insulating film 80 can be prevented from being reduced.

[0023]

The gate electrode 76 is formed of a chromium film 61 having a high thermal conductivity. Therefore, the annealing temperature of the amorphous silicon film 63 formed on the gate electrode 76 depends on the heat release from the gate electrode 76 during the ELA method. The temperature is lower than the temperature of the silicon film 63.
The cross-sectional shape of the gate electrode 76 is tapered,
It has a central flat portion 76a and inclined tapered portions 76b at both ends. Since the degree of heat transfer from the tapered portion 76b of the gate electrode 76 is lower than that of the flat portion 76a, the annealing temperature of the amorphous silicon film 63 formed on the tapered portion 76b is lower than that of the flat portion 76a. Get higher.

That is, the amorphous silicon film 63 formed on the gate electrode 76 requires higher laser crystallization energy than the amorphous silicon film 63 formed on the transparent insulating substrate 71. . On the gate electrode 76, the amorphous silicon film 63 formed on the flat portion 76a has a higher laser crystallization energy than the amorphous silicon film 63 formed on the tapered portion 76b. Required. In other words, the laser crystallization energy required for the amorphous silicon film 63 decreases in the order of on the transparent insulating substrate 71 → on the tapered portion 76b → on the flat portion 76a.

The grain size (crystal grain size) of the polycrystalline silicon film 81 increases as the laser irradiation energy during ELA increases. Therefore, the grain size of polycrystalline silicon film 81 formed on gate electrode 76 is smaller than that of polycrystalline silicon film 81 formed on transparent insulating substrate 71. Then, on the gate electrode 76, the polycrystalline silicon film 8 formed on the flat portion 76a is formed.
1 has a smaller grain size than the polycrystalline silicon film 81 formed on the tapered portion 76b. That is, the grain size of the polycrystalline silicon film 81 becomes smaller on the transparent insulating substrate 71 → on the tapered portion 76b → on the flat portion 76a.

Here, the polycrystalline silicon film 81 formed on the flat portion 76a of the gate electrode 76 is
Corresponds to 3. Further, the tapered portion 76b of the gate electrode 76
The polycrystalline silicon film 81 formed on the low-concentration regions 82a and 83a of the drain region 82 or the source region 83
Corresponding to Then, the polycrystalline silicon film 81 formed on the transparent insulating substrate 71 corresponds to the high-concentration regions 82b and 83b of the drain region 82 or the source region 83. Therefore, the grain size of the polycrystalline silicon film 81 changes from the high-concentration regions 82b and 83b to the low-concentration regions 82a and 83a.
It becomes smaller in the order of the channel region 93.

FIG. 14 shows the relationship between the laser irradiation energy during ELA and the grain size of each part of the polycrystalline silicon film 81. In the polycrystalline silicon film 81, when the value of the laser crystallization energy is E1,
The grain size of the portion corresponding to b and 83b (the portion on the transparent insulating substrate 71) has a peak value. When the value of the laser crystallization energy is E2, the low concentration region 82
a, 83a (part on tapered portion 76b)
Has a peak value. When the value of the laser crystallization energy is E3, the channel region 93
(The portion on the flat portion 76a) has a peak value. These laser crystallization energy values E1, E2, and E3 have a relationship of E1 <E2 <E3.

As described above, when the grain size of the polycrystalline silicon film 81 becomes non-uniform in each part, the element characteristics of the TFT 106 become non-uniform. In particular, as the grain size on the tapered portion 76b becomes more uneven, the regions 82a, 83
The sheet resistance of “a” greatly varies, and the ON current of the TFT 106 fluctuates. This is because the sheet resistance of each of the regions 82a and 83a directly acts as a parasitic resistance.

The TFT 1 formed on the transparent insulating substrate 71
06, when the element characteristics of a certain number or more of the TFTs 106 become non-uniform or the on-current becomes less than a required value,
The pixel portion 101 using the transparent insulating substrate 71 has to be discarded as a defective product. Also, the transparent insulating substrate 71
When the element characteristics of some of the TFTs 106 formed above become non-uniform or the on-current becomes less than a required value, display unevenness occurs in the pixel portion 101. That is, TF
The non-uniformity of the element characteristics of T106 and the decrease of the on-current cause a decrease in the yield of the pixel portion 101 and a display defect.

The present invention has been made to solve the above problems, and has the following objects. 1) To provide a thin film transistor capable of preventing non-uniform element characteristics and a reduction in on-current.

2] Provided is a method of manufacturing a thin film transistor capable of preventing non-uniform element characteristics and a reduction in on-current. 3] To provide an active matrix type display device capable of preventing a decrease in yield and occurrence of display failure.

[0032]

According to a first aspect of the present invention, a polycrystalline silicon film is used as an active layer, and a grain size of a portion corresponding to a drain region, a source region, and a channel region of the polycrystalline silicon film is reduced. The gist is to be uniform.

According to a second aspect of the present invention, in the thin film transistor according to the first aspect, a gate electrode is formed on the insulating substrate, and the gate electrode is formed on the insulating substrate and the gate electrode via a gate insulating film as an active layer. A polycrystalline silicon film is formed, a polycrystalline silicon film formed on a gate electrode corresponds to a channel region, and a polycrystalline silicon film formed on an insulating substrate has a bottom gate structure corresponding to a drain region and a source region. That is the gist.

According to a third aspect of the present invention, in the thin film transistor according to the second aspect, the surface of the polycrystalline silicon film is flattened, and the thickness of the portion corresponding to the drain region and the source region is reduced to the channel region. The gist is that it is formed thicker than the film thickness of the corresponding part.

According to a fourth aspect of the present invention, there is provided the thin film transistor according to the second aspect, further comprising a high thermal conductive insulating film formed so as to sandwich the gate electrode.

According to a fifth aspect of the present invention, there is provided a thin film transistor according to the second aspect, further comprising a high heat conductive insulating film formed between the gate electrode and an insulating substrate.

According to a sixth aspect of the present invention, in the thin film transistor according to any one of the first to fifth aspects, the cross-sectional shape of the gate electrode has a tapered shape in which a central portion is flat and both ends are inclined. The polycrystalline silicon film formed on the central flat portion of the gate electrode corresponds to the channel region, and the polycrystalline silicon film formed on the inclined tapered portion of the gate electrode and on the insulating substrate corresponds to the drain region. The main point is to correspond to the source region.

According to a seventh aspect of the present invention, in the thin film transistor according to the sixth aspect, the polycrystalline silicon film formed on the tapered portion of the gate electrode corresponds to a low concentration region forming a drain region and a source region. The polycrystalline silicon film formed on the insulating substrate corresponds to an LDD corresponding to a high concentration region forming a drain region and a source region.
The point is to take the structure.

The invention according to claim 8 is a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film on the insulating substrate and the gate electrode, and a step of forming a flat surface on the gate insulating film. By forming the amorphous silicon film and irradiating the surface of the amorphous silicon film with laser light, the amorphous silicon film is heated and crystallized,
And forming a polycrystalline silicon film to be an active layer.

According to a ninth aspect of the present invention, there is provided a semiconductor device comprising: a step of forming a gate electrode on an insulating substrate; a step of forming a gate insulating film on the insulating substrate and the gate electrode; Forming a film, forming an insulating film with a flat surface on the amorphous silicon film, and irradiating the surface of the amorphous silicon film with a laser beam through the flat insulating film, A step of forming a polycrystalline silicon film to be an active layer by heating and crystallizing the crystalline silicon film.

According to a tenth aspect of the present invention, there is provided a process for forming a gate electrode sandwiched between high thermal conductive insulating films on an insulating substrate, and forming a gate insulating film on the insulating substrate, the gate electrode and the high thermal conductive insulating film. And forming an amorphous silicon film on the gate insulating film, and irradiating the surface of the amorphous silicon film with laser light to heat and crystallize the amorphous silicon film. And a step of forming a polycrystalline silicon film to be an active layer.

According to the eleventh aspect of the present invention, a step of forming a high thermal conductive insulating film on an insulating substrate, a step of forming a gate electrode on the high thermal conductive insulating film, and a step of forming a gate electrode on the high thermal conductive insulating film and the gate electrode Forming a gate insulating film, forming an amorphous silicon film over the gate insulating film, and irradiating the surface of the amorphous silicon film with laser light to heat the amorphous silicon film. A step of forming a polycrystalline silicon film to be an active layer by crystallization.

The twelfth aspect of the present invention is the eighth aspect of the present invention.
2. The method of manufacturing a thin film transistor according to any one of the items 1 to 3, further comprising a step of forming a cross-sectional shape of the gate electrode into a tapered shape in which a central portion is flat and both ends are inclined.

According to the thirteenth aspect of the present invention,
The gist is to use the thin film transistor according to any one of the above as a pixel driving element. According to a fourteenth aspect of the present invention, a thin film transistor manufactured by the method of manufacturing a thin film transistor according to any one of the eighth to twelfth aspects is used as a pixel driving element.

In the embodiments of the invention described below, the “highly heat conductive film” described in the claims or the means for solving the problems is composed of a silicon oxide film 22, "Is composed of the light-transmitting high heat conductive insulating films 33 and 42.

[0046]

Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same components as those in the conventional embodiment shown in FIGS. 10 to 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.

(First Embodiment) FIG. 1 shows a pixel 1 in an LCD of a first embodiment having a transmissive structure using a bottom gate polycrystalline silicon TFT as a TFT 106.
2 shows a schematic cross section of the pixel portion 101 (pixel portion 101).

The present embodiment differs from the conventional embodiment shown in FIG. 12 in the following points. [1] Polycrystalline silicon film 1 serving as active layer of TFT 106
1 is flattened, and the film thickness of the portion corresponding to the drain region 82 and the source region 83 is larger than the film thickness of the portion corresponding to the channel region 93.

[2] The grain size of each portion of the polycrystalline silicon film 11 is substantially uniform. Next, the manufacturing method of the present embodiment will be described sequentially.

Step 1 (see FIG. 2A) to Step 3 (see FIG.
(See (c)); the same as Step 1 (see FIG. 13A) to Step 3 (see FIG. 13C) of the conventional embodiment. Step 4 (see FIG. 2D);
On each of the electrodes 76 and 77 and the transparent insulating substrate 71, a silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 12 are continuously formed. As a result, a gate insulating film 80 including the films 78 and 79 is formed, and the amorphous silicon film 12 is formed thereon. Here, the amorphous silicon film 12 is formed to be thicker than the amorphous silicon film 63 of the conventional embodiment. Then, the surface of the amorphous silicon film 12 is planarized by using the entire surface etch back method.

Next, annealing (processing temperature: about 400 ° C.) is performed to perform dehydrogenation processing for removing hydrogen taken in the amorphous silicon film 12. Subsequently, by irradiating the surface of the amorphous silicon film 12 with excimer laser light using the ELA method, the amorphous silicon film 12 is heated and crystallized to form the polycrystalline silicon film 11. At this time, excimer laser light in the form of a sheet beam or a rectangular beam is pulse-irradiated. The irradiation area of the laser beam was set to about 150 × 0.3 mm, and the amorphous silicon film 12 on the transparent insulating substrate 71 was shifted while shifting the position of the laser beam.
Irradiate the entire surface of

Here, the surface of the amorphous silicon film 12 is flattened, and the drain region 82 and the source region 8 are formed.
The thickness of the portion corresponding to No. 3 is larger than the thickness of the portion corresponding to the channel region 93.

Therefore, the amorphous silicon film on each of the regions 82 and 83 requires a large irradiation energy for crystallization due to the large thickness, and the grain size of the crystallized polycrystalline silicon film is smaller than that of the conventional embodiment. Becomes smaller. Therefore, the difference in grain size between the conventional polycrystalline silicon film in the channel region and the polycrystalline silicon film in the drain / source region becomes smaller and narrower.

On the gate electrode 76, the amorphous silicon film 12 formed on the tapered portion 76b and the amorphous silicon film 1 formed on the flat portion 76a
2, higher irradiation energy is required, but the grain size difference of the polycrystalline silicon film is smaller than in the conventional embodiment. Further, on the gate electrode 76,
The amorphous silicon film 12 formed on the tapered portion 76b also requires higher irradiation energy for crystallization than the amorphous silicon film 12 formed on the flat portion 76a. The grain size difference of the polycrystalline silicon film is smaller than that of the polycrystalline silicon film.

That is, although the laser crystallization energy required for the amorphous silicon film 12 increases in the transparent insulating substrate 71, the tapered portion 76b, and the flat portion 76a, the grain size difference of the polycrystalline silicon film in each portion is small. , Compared to the conventional embodiment. That is, the amorphous silicon film 12
The surface of the amorphous silicon film 12 is planarized.
The laser crystallization energy applied to each part of the laser beam is brought close to the optimum condition.

As a result, the grain size of each portion of the polycrystalline silicon film 11 becomes smaller than that of the conventional polycrystalline silicon film 8.
1 is substantially uniform as compared with the grain size of each part. FIG. 3 shows the relationship between the laser irradiation energy during ELA and the grain size of each part of the polycrystalline silicon film 11.

In the polycrystalline silicon film 11, when the value of the laser crystallization energy is E1 ', the high concentration region 82
The grain size of the portion corresponding to b and 83b (the portion on the transparent insulating substrate 71) has a peak value. When the value of the laser crystallization energy is E2 ', the low concentration region 8
The grain size of the portion corresponding to 2a and 83a (the portion on the tapered portion 76b) has a peak value. When the value of the laser crystallization energy is E3, the grain size of the portion corresponding to the channel region 93 (the portion on the flat portion 76a) has a peak value. These laser crystallization energy values E1 ′, E2 ′, and E3 include E1 ′ <E2 ′.
<E3. However, each value E1 ', E2'
Is higher than the values E1 and E2 in the conventional embodiment. That is, the values E1 ′, E2 ′, E3 are closer,
The crystallized polycrystalline silicon film becomes more uniform.

Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 11 and the respective members shown in FIG. 1 are formed to complete the pixel portion 101 including the pixels 102.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) Polycrystalline silicon film 1 serving as an active layer of TFT 106
In 1, the grain size of each part is substantially uniform. Therefore, the element characteristics of the TFT 106 are made uniform. Further, the grain size of each of the regions 82a and 83a can be made uniform, and the ON current of the TFT 106 can be stabilized.

(2) According to the above (1), the transparent insulating substrate 71
The element characteristics of all the TFTs 106 formed thereon can be stabilized, and the ON current can be increased to a required value or more. Thus, a decrease in the yield of the pixel portion 101 and a display defect can be prevented.

(3) In order to make the grain size of each part of the polycrystalline silicon film 11 almost uniform as in the above (1), the amorphous silicon film 12 is formed thick and then its surface is flattened. Thus, it is only necessary to perform the ELA method as in the conventional embodiment. Therefore, its implementation is simple and easy.

(4) Since the surface of the amorphous silicon film 12 is flattened, it is easy to uniformly irradiate the entire surface of the amorphous silicon film 12 with excimer laser light.
Therefore, the laser crystallization energy applied to each portion of the amorphous silicon film 12 can be easily made uniform, and the above (1)
Function and effect can be further enhanced.

(Second Embodiment) FIG. 4 shows a pixel 1 in an LCD of a second embodiment having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as the TFT 106.
2 shows a schematic cross section of the pixel portion 101 (pixel portion 101).

The present embodiment is different from the conventional embodiment shown in FIG. 12 in that the grain size of each portion of the polycrystalline silicon film 21 serving as the active layer of the TFT 106 is substantially uniform. Next, the manufacturing method of the present embodiment will be described sequentially.

Step 1 (see FIG. 5A) to step 3 (see FIG.
(See (c)); the same as Step 1 (see FIG. 13A) to Step 3 (see FIG. 13C) of the conventional embodiment. Step 4 (see FIG. 5D);
On each of the electrodes 76 and 77 and the transparent insulating substrate 71, a silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are continuously formed. As a result, a gate insulating film 80 including the films 78 and 79 is formed, and an amorphous silicon film 63 is formed thereon.

Next, annealing (processing temperature: about 400 ° C.) is performed to perform dehydrogenation processing for removing hydrogen taken in the amorphous silicon film 63. Step 5 (see FIG. 5E): A thick silicon oxide film 22 is formed on the amorphous silicon film 63 by using the CVD method.
Then, the silicon oxide film 2 is
2 is flattened.

Subsequently, the surface of the amorphous silicon film 63 is irradiated with excimer laser light via the silicon oxide film 22 by using the ELA method, so that the amorphous silicon film 63 is heated and crystallized. A polycrystalline silicon film 21 is formed.

Here, the surface of silicon oxide film 22 is flattened, and drain region 82 and source region 83 are formed.
Is thicker than the film thickness of the portion corresponding to the channel region 93. Therefore, ELA
When performing the method, the laser irradiation energy is more attenuated by the silicon oxide film on the surface on the drain / source region than on the channel region. As a result, the crystallization energy that is effectively given to the amorphous silicon film becomes lower as the silicon oxide film on the surface becomes thicker, and it becomes more difficult to crystallize on the drain / source region (insulating substrate).

As the excimer laser light, it is desirable to use light having a wavelength easily absorbed by the silicon oxide film 22. Specifically, KrF excimer laser light (wavelength: 2
48 nm) or ArF excimer laser light (wavelength: 198 nm)
May be used.

As a result, the annealing temperature of each part of the amorphous silicon film 63 of the present embodiment should be substantially uniform as compared with the ultimate temperature of each part of the conventional amorphous silicon film 63. Becomes possible. That is, by forming the silicon oxide film 22 on the amorphous silicon film 63 and flattening the surface of the silicon oxide film 22, an effective laser crystallization applied to each part of the amorphous silicon film 63 is achieved. Energy is brought to optimal conditions. Therefore, the grain size of each portion of the polycrystalline silicon film 21 is substantially uniform as compared with the grain size of each portion of the conventional polycrystalline silicon film 81.

Thereafter, a photoresist film (not shown) is formed on the silicon oxide film 22, exposed from the back surface (the surface on which the TFT 106 is not formed) of the transparent insulating substrate 71, and developed, thereby forming the gate electrode 76 and the auxiliary capacitance. Only the photoresist film at the position corresponding to the electrode 77 is left. Then, the silicon oxide film 22 is formed by a wet etching method using the remaining photoresist film as an etching mask.
Is etched to form a stopper layer 94 made of the silicon oxide film 22.

Next, using the stopper layer 94 as a mask for ion implantation, the drain region 8 is formed in the polycrystalline silicon film 21.
2 and the source region 83 are formed. Subsequently, by forming the members shown in FIG. 4, the pixel portion 101 including the pixels 102 is completed.

As described above, according to the present embodiment, the following operations and effects can be obtained. {1} Polycrystalline silicon film 2 to be an active layer of TFT 106
In 1, the grain size of each part is substantially uniform. Therefore, the same operation and effect as (1) and (2) of the first embodiment can be obtained. {2} In order to make the grain size of each part of the polycrystalline silicon film 21 almost uniform as in the above {1}, the silicon oxide film 22 is formed thick on the amorphous silicon film 63 and then the surface thereof is flattened. And then use ELA
Just do the law. Therefore, its implementation is simple and easy.

{3} Since the silicon oxide film 22 becomes the stopper layer 94 in a later process, the formation of the silicon oxide film 22 does not complicate the entire process. (Third Embodiment) FIG. 6 shows a schematic cross section of a pixel 102 (pixel portion 101) in a LCD of a third embodiment having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as a TFT 106.

This embodiment differs from the conventional embodiment shown in FIG. 12 in the following points. (1) Gate electrode 31 of TFT 106 and storage capacitor SC
The cross-sectional shape of the auxiliary capacitance electrode 32 is rectangular.
No taper is provided unlike the conventional embodiment.

(2) Gate electrode 31 and auxiliary capacitance electrode 3
2, a light-transmitting high-thermal-conductivity insulating film 33 is formed. That is, the translucent high heat conductive insulating film 33 is formed by the gate electrode 3.
1 are sandwiched therebetween. And each electrode 31,
The surface composed of the light-transmissive high-thermal-conductivity insulating film 32 is flattened.

(3) The grain size of each part of the polycrystalline silicon film 34 which becomes the active layer of the TFT 106 is almost uniform. Further, the thickness of the polycrystalline silicon film 34 is uniform, and as shown in the above (2), the polycrystalline silicon film 34
The lower side (each of the electrodes 31 and 32 and the light-transmitting high-thermal-conductivity insulating film 33) is flattened, so that the polysilicon film 34
Is also flattened.

Next, the manufacturing method of this embodiment will be described sequentially. Step 1 (see FIG. 7A); a light-transmitting high-heat-conducting insulating film 33 is formed on the transparent insulating substrate 71. In addition, as the translucent high heat conductive insulating film 33, there is a diamond thin film or the like.

Step 2 (see FIG. 7B): The gate electrode 31 and the auxiliary capacitance electrode 3 are formed on the transparent high heat conductive insulating film 33.
Then, a resist pattern 35 for forming No. 2 is formed. Step 3 (see FIG. 7C): The light-transmitting high-thermal-conductivity insulating film 33 is etched using an anisotropic etching method using the resist pattern 35 as an etching mask.
A concave portion 33a is formed in the translucent high heat conductive insulating film 33, and the transparent insulating substrate 71 is exposed from the concave portion 33a.

Next, a chromium film 61 is formed on the transparent high heat conductive insulating film 33 and the transparent insulating substrate 71 exposed from the concave portion 33a by a sputtering method, and the concave portion 33a of the light transmissive high thermal conductive insulating film 33 is formed. Is embedded by a chromium film 61.

Step 4 (see FIG. 7D): The chromium film 61 formed on the light-transmitting high-thermal-conductivity insulating film 33 is removed by using the whole-surface etch-back method, so that The surface composed of 33 and the chromium film 61 is flattened. As a result, the concave portion 33a of the light-transmitting high heat conductive insulating film 33
A gate electrode 31 and an auxiliary capacitance electrode 32 made of a chromium film 61 embedded in the gate electrode 31 are formed.

Step 5 (see FIG. 7E): Plasma CV
Using method D, a silicon nitride film 78 and a silicon oxide film 7 are formed on each of the electrodes 31 and 32 and the translucent high heat conductive insulating film 33.
9. An amorphous silicon film 63 is continuously formed. As a result, a gate insulating film 80 including the films 78 and 79 is formed, and an amorphous silicon film 63 is formed thereon. Here, the electrodes 31 and 32 and the translucent high heat conductive insulating film 33 are used.
Is flattened, so that the surfaces of the films 78, 79, and 63 formed with a uniform thickness thereon are all flattened.

Next, annealing (processing temperature: about 400 ° C.) is performed to perform dehydrogenation processing for removing hydrogen taken in the amorphous silicon film 63. Subsequently, by irradiating the surface of the amorphous silicon film 63 with excimer laser light by using the ELA method, the amorphous silicon film 63 is heated and crystallized to form the polycrystalline silicon film 34.

Here, a translucent high heat conductive insulating film 33 is formed between the gate electrode 31 and the auxiliary capacitance electrode 32. Therefore, when performing the ELA method, heat escape from the amorphous silicon film on the insulating substrate to the substrate is not much different from heat escape from the amorphous silicon film on the gate electrode. Therefore, the annealing temperature of each part of the amorphous silicon film 63 can be made substantially uniform as compared with the annealing temperature of each part of the amorphous silicon film 63 in the conventional embodiment. That is, by providing the translucent high heat conductive insulating film 33 between the electrodes 31 and 32, the laser crystallization energy required for each portion of the amorphous silicon film 63 can be made closer to the optimum condition. Therefore, the grain size of each portion of the polycrystalline silicon film 34 is substantially uniform as compared with the grain size of each portion of the conventional polycrystalline silicon film 81.

Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 34, and the respective members shown in FIG. 6 are formed, thereby completing the pixel portion 101 including the pixels 102.

As described above, according to the present embodiment, the following operations and effects can be obtained. <1> Polycrystalline silicon film 34 to be an active layer of TFT 106
, The grain size of each part is substantially uniform. Therefore, the same operation and effect as (1) and (2) of the first embodiment can be obtained.

<2> As described in <1> above, the polycrystalline silicon film 3
In order to make the grain size of each portion of FIG. 4 almost uniform, a translucent high heat conductive insulating film 33 is provided between the gate electrode 31 and the auxiliary capacitance electrode 32, and the gate insulating film 80 and the amorphous silicon film are formed thereon. It is only necessary to perform the ELA method in the same manner as in the conventional embodiment after the 63s are sequentially formed. Therefore, its implementation is simple and easy.

<3> Since the surface of the amorphous silicon film 63 is flattened, it is easy to uniformly irradiate the entire surface of the amorphous silicon film 63 with excimer laser light. Accordingly, the laser crystallization energy applied to each portion of the amorphous silicon film 63 can be easily made uniform, and the function and effect of <1> can be further enhanced.

<4> Although the gate electrode 31 is not provided with a tapered portion, the surface composed of the electrodes 31 and 32 and the light-transmitting high-heat conductive insulating film 33 is flattened. Therefore, the surface of the gate insulating film 80 is also flattened, and the film thickness is made uniform and does not partially decrease. Also, no electrolytic concentration occurs at the end of the gate electrode 76. Therefore, the withstand voltage of the gate electrode 31 can be sufficiently ensured.

(Fourth Embodiment) FIG. 8 shows a pixel 1 in an LCD according to a fourth embodiment having a transmission type configuration using a bottom gate polycrystalline silicon TFT as the TFT 106.
2 shows a schematic cross section of the pixel portion 101 (pixel portion 101).

The present embodiment differs from the conventional embodiment shown in FIG. 12 in the following points. (1) The transparent high heat conductive insulating film 42 is formed on the entire surface of the transparent insulating substrate 71, and the transparent high heat conductive insulating film 42
A gate electrode 76 and an auxiliary capacitance electrode 77 are formed thereon.

(2) The grain size of each portion of the polycrystalline silicon film 41 serving as the active layer of the TFT 106 is substantially uniform. Next, the manufacturing method of the present embodiment will be described sequentially.

Step 1 (see FIG. 9A): A transparent high heat conductive insulating film 42 is formed on the transparent insulating substrate 71. In addition, as the translucent high heat conductive insulating film 42, there is a diamond thin film or the like. Next, a chromium film 61 is formed on the translucent high heat conductive insulating film 42 by a sputtering method.

Step 2 (see FIG. 9B) to Step 3 (see FIG. 9B)
(See (c)); the same as Step 2 (see FIG. 13 (b)) to Step 3 (see FIG. 13 (c)) of the conventional embodiment. Step 4 (see FIG. 9D);
A silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are successively formed on the electrodes 76, 77 and the translucent high heat conductive insulating film. As a result, a gate insulating film 80 composed of the films 78 and 79 is formed on the translucent high heat conductive insulating film 42, and an amorphous silicon film 63 is formed thereon.
Is obtained.

Next, annealing (processing temperature: about 400 ° C.) is performed to perform dehydrogenation processing for removing hydrogen taken in the amorphous silicon film 63. Subsequently, the surface of the amorphous silicon film 63 is irradiated with excimer laser light by using the ELA method, whereby the amorphous silicon film 63 is heated and crystallized to form the polycrystalline silicon film 41.

Here, since the translucent high heat conductive insulating film 42 is formed below the gate electrode 76, heat escapes from the amorphous silicon film on the insulating substrate to the substrate. Of heat from the amorphous silicon film. Therefore, the annealing temperature of each portion of the amorphous silicon film 63 can be made substantially uniform as compared with the annealing temperature of each portion of the amorphous silicon film 63 in the conventional embodiment. That is, by providing the translucent high heat conductive insulating film 33 between the electrodes 31 and 32, the laser crystallization energy required for each portion of the amorphous silicon film 63 can be made closer to the optimum condition. Therefore, the grain size of each portion of the polycrystalline silicon film 34 is smaller than the grain size of each portion of the polycrystalline silicon film 81 in the conventional mode.
Almost uniform.

Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 41, and each member shown in FIG. 8 is formed, thereby completing the pixel portion 101 including the pixels 102.

As described above, according to the present embodiment, the following operations and effects can be obtained. [1] Polycrystalline silicon film 41 to be an active layer of TFT 106
, The grain size of each part is substantially uniform. Therefore, the same operation and effect as (1) and (2) of the first embodiment can be obtained.

[2] As described in the above [1], the polycrystalline silicon film 4
In order to make the grain size of each portion substantially uniform, a light-transmitting high heat conductive insulating film 42 is formed on a transparent insulating substrate 71, and a gate electrode 76, a gate insulating film 80, an amorphous silicon film It is only necessary to perform the ELA method in the same manner as in the conventional embodiment after the 63s are sequentially formed. Therefore, its implementation is simple and easy.

The above embodiments may be modified as follows, and even in such a case, similar functions and effects can be obtained. [1] In step 4 of the first embodiment, plasma CVD
The amorphous silicon film 1 having a flat surface by using the bias sputtering
Form 2

[2] In step 4 of the second embodiment, C
The silicon oxide film 22 having a flat surface is formed by using the bias sputtering method instead of using the VD method and the entire surface etch-back method together.

[3] In step 4 of the second embodiment, T
By using the silicon oxide film 22 having a flat surface made of an EOS (TetraEthyl OrthSilicate) film, a flattening step by the entire etch-back method is omitted.

[4] In the first, second and fourth embodiments, the tapered portion 76b of the gate electrode 76 is omitted. In this case, the operation and effect provided by the provision of the tapered portion 76b as described above cannot be obtained, but the operation and effect described for each embodiment can be similarly obtained.

[5] The gate electrodes 76 and 31 and the auxiliary capacitance electrodes 77 and 32 are made of a high melting point metal (molybdenum, tungsten, tantalum, hafnium,
It is formed of a single film of zirconium, niobium, titanium, vanadium, rhenium, iridium, osmium, rhodium, etc.), a high melting point metal alloy film, or a plurality of layers of high melting point metal films.

[6] The TFT 106 has a single drain (single drain) structure or a multi-gate structure instead of the LDD structure. [7] The transparent insulating substrate 71 is replaced with an insulating layer such as a ceramic substrate or a silicon oxide film, and is applied to a contact type image sensor or a three-dimensional IC instead of an LCD.

[8] The TFT 106 is applied to a pixel drive element in an active matrix display device using an electroluminescence element for a pixel. that's all,
Although each embodiment has been described, technical ideas other than the claims that can be grasped from each embodiment will be described below together with their effects.

(A) The method for manufacturing a thin film transistor according to any one of claims 8 to 12, wherein the laser light is excimer laser light. In this case, efficient crystallization can be performed.

(B) The method for manufacturing a thin film transistor according to claim 9, wherein the laser light is an excimer laser light, and the excimer laser light has a wavelength easily absorbed by the flat insulating film. .

With this configuration, the excimer laser beam is partially absorbed by the insulating film, so that the effect of the ninth aspect of the present invention can be further enhanced.

[0110]

According to the present invention, the grain size of each portion of the polycrystalline silicon film can be made more uniform, so that the sheet resistance of the drain region and the source region varies. Can be reduced.
Therefore, it is possible to provide a thin film transistor capable of preventing nonuniform element characteristics and a reduction in on-current.

According to the second aspect of the present invention, a thin film transistor having a bottom gate structure can be obtained. According to the invention described in any one of claims 3 to 5, when forming a polycrystalline silicon film from an amorphous silicon film, the grain size of each portion of the polycrystalline silicon film becomes uniform.

According to the invention described in claim 6, the grain size of each portion of the polycrystalline silicon film formed on the flat portion and the tapered portion of the gate electrode and on the insulating substrate can be made uniform. . Further, since the gate electrode has the tapered portion, the thickness of the gate insulating film can be prevented from being reduced. Therefore, a sufficient withstand voltage can be ensured.

According to the seventh aspect of the present invention, in the thin film transistor having the LDD structure, the grain size of each portion of the polycrystalline silicon film including the high-concentration region and the low-concentration region constituting the drain region and the source region is reduced. It can be uniform.

According to the invention described in any one of the eighth to twelfth aspects, it is possible to provide a method of manufacturing a thin film transistor capable of preventing non-uniform element characteristics and a reduction in on-current.

According to the eighth aspect of the present invention, the third aspect is provided.
The same operation and effect as those of the invention described in (1) can be obtained. According to the ninth aspect, when forming a polycrystalline silicon film from an amorphous silicon film, the grain size of each portion of the polycrystalline silicon film becomes uniform.

According to the tenth aspect, the same operation and effect as those of the fourth aspect can be obtained. According to the eleventh aspect, the same operations and effects as those of the fifth aspect can be obtained.

According to the twelfth aspect, the same operation and effect as those of the sixth aspect can be obtained. According to the thirteenth or fourteenth aspect of the present invention, it is possible to provide an active matrix type display device capable of preventing a reduction in yield and a display failure.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a pixel according to a first embodiment.

FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 3 is a characteristic diagram for explaining the operation of the first embodiment.

FIG. 4 is a schematic sectional view of a pixel according to a second embodiment.

FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the second embodiment.

FIG. 6 is a schematic sectional view of a pixel according to a third embodiment.

FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 8 is a schematic sectional view of a pixel according to a fourth embodiment.

FIG. 9 is a schematic cross-sectional view for explaining a manufacturing process according to a fourth embodiment.

FIG. 10 is a block diagram of an active matrix type LCD.

FIG. 11 is an equivalent circuit diagram of a pixel.

FIG. 12 is a schematic cross-sectional view of a pixel in a conventional mode.

FIG. 13 is a schematic cross-sectional view for explaining a manufacturing process in a conventional mode.

FIG. 14 is a characteristic diagram for explaining the operation of the conventional embodiment.

[Explanation of symbols]

 11, 21, 34, 41: polycrystalline silicon film 12, 63: amorphous silicon film 22: silicon oxide film as a flat insulating film 33, 42: translucent high heat conductive insulating film 71: transparent insulating substrate 76, Reference Signs List 31 gate electrode 80 gate insulating film 82 drain region 83 source region 82a, 83a low concentration region 82b, 83b high concentration region 93 channel region 101 pixel portion 106 TFT

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 616T 617K 618C 621 627A 627G (72) Inventor Hiroyuki Kuriyama 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo (72) Inventor Katsuhito Aoki 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (14)

[Claims] 1. A polycrystalline silicon film is used as an active layer.
A thin film transistor having a uniform grain size at portions corresponding to the drain region, the source region, and the channel region of the polycrystalline silicon film. 2. The thin film transistor according to claim 1, wherein a gate electrode is formed on the insulating substrate, and a polycrystalline silicon film as an active layer is formed on the insulating substrate and the gate electrode via a gate insulating film; A thin film transistor having a bottom gate structure in which a polycrystalline silicon film formed over a gate electrode corresponds to a channel region and a polycrystalline silicon film formed over an insulating substrate corresponds to a drain region and a source region. 3. The thin film transistor according to claim 2, wherein a surface of said polycrystalline silicon film is flattened, and a film thickness of a portion corresponding to a drain region and a source region is equal to a film thickness of a portion corresponding to a channel region. A thin film transistor formed thicker than that. 4. The thin film transistor according to claim 2, further comprising a high thermal conductive insulating film formed so as to sandwich the gate electrode. 5. The thin film transistor according to claim 2, further comprising a high thermal conductive insulating film formed between the gate electrode and an insulating substrate. 6. The thin-film transistor according to claim 1, wherein a cross-sectional shape of the gate electrode has a tapered shape in which a central part is flat and both ends are inclined, and a central part of the gate electrode is formed. The polycrystalline silicon film formed on the flat portion corresponds to the channel region, and the polycrystalline silicon film formed on the inclined tapered portion of the gate electrode and on the insulating substrate corresponds to the drain region and the source region. . 7. The thin film transistor according to claim 6, wherein the polycrystalline silicon film formed on the tapered portion of the gate electrode corresponds to a low concentration region forming a drain region and a source region, and is formed on the insulating substrate. A thin film transistor having an LDD structure in which the formed polycrystalline silicon film corresponds to a high concentration region forming a drain region and a source region. 8. A step of forming a gate electrode on the insulating substrate, a step of forming a gate insulating film on the insulating substrate and the gate electrode, and forming an amorphous silicon film having a flat surface on the gate insulating film And irradiating the surface of the amorphous silicon film with laser light to heat and crystallize the amorphous silicon film.
Forming a polycrystalline silicon film to be an active layer. 9. A step of forming a gate electrode on the insulating substrate, a step of forming a gate insulating film on the insulating substrate and the gate electrode, a step of forming an amorphous silicon film on the gate insulating film, Forming a flat insulating film on the amorphous silicon film, and irradiating the surface of the amorphous silicon film with laser light through the flat insulating film to heat the amorphous silicon film. Forming a polycrystalline silicon film to be an active layer by crystallizing the thin film. 10. A step of forming a gate electrode sandwiched between high thermal conductive insulating films on an insulating substrate, a step of forming a gate insulating film on the insulating substrate, the gate electrode, and the high thermal conductive insulating film; Forming an amorphous silicon film thereon, and irradiating the surface of the amorphous silicon film with a laser beam to heat and crystallize the amorphous silicon film.
Forming a polycrystalline silicon film to be an active layer. 11. A step of forming a high thermal conductive insulating film on an insulating substrate, a step of forming a gate electrode on the high thermal conductive insulating film, and a step of forming a gate insulating film on the high thermal conductive insulating film and the gate electrode Forming an amorphous silicon film on the gate insulating film; and irradiating the surface of the amorphous silicon film with a laser beam to heat and crystallize the amorphous silicon film.
Forming a polycrystalline silicon film to be an active layer. 12. The method for manufacturing a thin film transistor according to claim 8, further comprising a step of forming a cross-sectional shape of the gate electrode into a tapered shape in which a central portion is flat and both ends are inclined. A method for manufacturing a thin film transistor. 13. An active matrix type display device using the thin film transistor according to claim 1 as a pixel driving element. 14. An active matrix type display device using a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 8 as a pixel driving element.