JP3833327B2 - Thin film transistor manufacturing method, display device, contact image sensor, three-dimensional IC - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionThinMembrane transistor manufacturing method, Display device, contact image sensor, 3D ICIt is about.
[0002]
[Prior art]
In recent years, an active matrix liquid crystal display (LCD) using a thin film transistor (TFT) has attracted attention as a high-quality display device.
[0003]
In the active matrix method, a pixel driving element (active element) and a signal storage element (pixel capacity) are integrated in each pixel arranged in the matrix, and a liquid crystal is driven quasi-statically by causing each pixel to perform a kind of storage operation. It is a method to do. That is, the pixel driving element functions as a switch that is switched on and off by a scanning signal. Then, a data signal (display signal) is transmitted to the display electrode through the pixel driving element in the on state, and the liquid crystal is driven. Thereafter, when the pixel driving element is turned off, the data signal applied to the display electrode is stored in the signal storage element in a charge state, and the liquid crystal is continuously driven until the pixel driving element is turned on next time. For this reason, even if the number of scanning lines increases and the driving time allocated to one pixel decreases, the driving of the liquid crystal is not affected and the contrast does not decrease.
[0004]
As the pixel driving element, a TFT is generally used. In a TFT, a semiconductor thin film formed on an insulating substrate is used as an active layer. Typical active layers are amorphous silicon films and polycrystalline silicon films. A TFT using an amorphous silicon film as an active layer is called an amorphous silicon TFT, and a TFT using a polycrystalline silicon film is called a polycrystalline silicon TFT. Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than amorphous silicon TFTs. Therefore, the polycrystalline silicon TFT can be used not only as a pixel driving element but also as an element constituting a logic circuit. Therefore, if a polycrystalline silicon TFT is used, not only the pixel portion but also the peripheral drive circuit portion arranged in the periphery thereof can be integrally formed on the same substrate. That is, the polycrystalline silicon TFT as the pixel driving element arranged in the pixel portion and the polycrystalline silicon TFT constituting the peripheral driving circuit portion are formed in the same process.
[0005]
FIG. 10 shows a block configuration of a general active matrix LCD.
Each scanning line (gate wiring) G1... Gn, Gn + 1... Gm and each data line (drain wiring) D1... Dn, Dn + 1. The gate lines G1 to Gm and the drain lines D1 to Dm are orthogonal to each other, and the pixel 102 is provided in the orthogonal part. Each of the gate lines G1 to Gm is connected to the gate driver 103 so that a gate signal (scanning signal) is applied. Each drain wiring D1 to Dm is connected to a drain driver (data driver) 104 so that a data signal (video signal) is applied. These drivers 103 and 104 constitute a peripheral drive circuit unit 105. An LCD in which at least one of the drivers 103 and 104 is formed on the same substrate as the pixel unit 101 is generally called a driver integrated type (driver built-in type) LCD. Note that the gate driver 103 may be provided on both sides of the pixel portion 101 in some cases. In some cases, the drain driver 104 is provided on both sides of the pixel portion 101.
[0006]
FIG. 11 shows an equivalent circuit of the pixel 102 provided in the orthogonal portion between the gate wiring Gn and the drain wiring Dn.
The pixel 102 includes a TFT 106 as a pixel driving element, a liquid crystal cell LC, and an auxiliary capacitor (storage capacitor or additional capacitor) SC. The gate of the TFT 106 is connected to the gate wiring Gn, and the drain of the TFT 106 is connected to the drain wiring Dn. The source of the TFT 106 is connected to the display electrode (pixel electrode) of the liquid crystal cell LC and the auxiliary capacitor SC. The liquid crystal cell LC and the auxiliary capacitor SC constitute the signal storage element. A voltage Vcom is applied to the common electrode (electrode opposite to the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitance SC, a constant voltage VR is applied to an electrode (hereinafter referred to as an auxiliary capacitance electrode) opposite to an electrode connected to the TFT source (hereinafter referred to as a storage electrode). The common electrode of the liquid crystal cell LC is literally a common electrode for all the pixels 102. A capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. Note that the auxiliary capacitance electrode of the auxiliary capacitance SC may be connected to the adjacent gate wiring Gn + 1.
[0007]
In the pixel 102 configured as described above, when the gate line Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT 106, the TFT 106 is turned on. Then, the capacitance of the liquid crystal cell LC and the auxiliary capacitance SC are charged by the data signal applied to the drain wiring Dn. On the other hand, when the gate wiring Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT 106, the TFT 106 is turned off, and the voltage applied to the drain wiring Dn at that time becomes the capacitance and auxiliary capacitance of the liquid crystal cell LC. Held by SC. In this way, by applying a data signal to be written to the pixel 102 to the drain wirings D1 to Dm and controlling the voltages of the gate wirings G1 to Gm, the pixel 102 can hold an arbitrary data signal. The transmittance of the liquid crystal cell LC changes according to the data signal held by the pixel 102, and an image is displayed.
[0008]
Here, important characteristics of the pixel 102 include a writing characteristic and a holding characteristic. What is required for the writing characteristics is that a desired video signal voltage is sufficiently written to the signal storage element (the liquid crystal cell LC and the auxiliary capacitor SC) within a unit time determined from the specification of the pixel portion 101. Is whether or not Also, what is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a necessary time.
[0009]
The auxiliary capacitor SC is provided in order to increase the capacitance of the signal storage element and improve the holding characteristics. That is, the liquid crystal cell LC has a limit in increasing the capacitance because of its structure. Thus, the auxiliary capacitance SC compensates for the shortage of the capacitance of the liquid crystal cell LC.
[0010]
FIG. 12 shows a schematic cross section of a pixel 102 (pixel portion 101) in a conventional LCD having a transmissive configuration using a bottom-gate polycrystalline silicon TFT as the TFT 106. FIG.
[0011]
A liquid crystal layer 73 filled with liquid crystal is formed between the transparent insulating substrates 71 and 72 facing each other. A display electrode 74 of the liquid crystal cell LC is provided on the transparent insulating substrate 71 side, and a common electrode 75 of the liquid crystal cell LC is provided on the transparent insulating substrate 72 side. The electrodes 74 and 75 sandwich the liquid crystal layer 73. Opposite.
[0012]
A gate electrode 76 of the TFT 106 constituting the gate wiring Gn is formed on the surface of the transparent insulating substrate 71 on the liquid crystal layer 73 side. On the gate electrode 76 and the transparent insulating substrate 71, a gate insulating film 80 having a two-layer structure of a lower silicon nitride film 78 and an upper silicon oxide film 79 is formed. On the gate insulating film 80, a polycrystalline silicon film 81 that is an active layer of the TFT 106 is formed. A drain region 82 and a source region 83 of the TFT 106 are formed in the polycrystalline silicon film 81. The TFT 106 has an LDD (Lightly Doped Drain) structure, and the drain region 82 and the source region 83 are composed of low concentration regions 82a and 83a and high concentration regions 82b and 83b, respectively. A channel region 93 is formed between the drain region 82 and the source region 83 in the polycrystalline silicon film 81.
[0013]
In the transparent insulating substrate 71 adjacent to the TFT 106, an auxiliary capacitor SC is formed in the same process as the TFT 106 is formed. A storage capacitor electrode 77 of the storage capacitor SC is formed on the surface of the transparent insulating substrate 71 on the liquid crystal layer 73 side. A dielectric film 84 is formed on the auxiliary capacitance electrode 77, and a storage electrode 85 of the auxiliary capacitance SC is formed on the dielectric film 84. The auxiliary capacitance electrode 77 has the same configuration as the gate electrode 76 and is formed in the same process. The dielectric film 84 is on the extension of the gate insulating film 80, and is formed in the same process with the same configuration as the gate insulating film 80. The storage electrode 85 is formed on the polycrystalline silicon film 81 and connected to the source region 83 of the TFT 106.
[0014]
A stopper layer 94 made of a silicon oxide film is formed on each of the channel region 93 and the storage electrode 85 in the polycrystalline silicon film 81. On the TFT 106 including the stopper layer 94 and the auxiliary capacitor SC, an interlayer insulating film 88 having a two-layer structure of a lower silicon oxide film 86 and an upper silicon nitride film 87 is formed. The high concentration region 82 b constituting the drain region 82 is connected to the drain electrode 90 constituting the drain wiring Dn through a contact hole 89 formed in the interlayer insulating film 88. A planarization insulating film 91 is formed on the drain electrode 90 and the interlayer insulating film 88. A display electrode 74 is formed on the planarization insulating film 91. The display electrode 74 is connected to a high concentration region 83 b constituting the source region 83 through a contact hole 92 formed in the planarization insulating film 91 and the interlayer insulating film 88. The drain electrode 90 has a two-layer structure of a lower molybdenum layer 90a and an upper aluminum alloy layer 90b. The display electrode 74 is made of ITO (Indium Tin Oxide).
[0015]
On the surface of the transparent insulating substrate 72 on the liquid crystal layer 73 side, color filters 95 for each of the three primary colors of light, red, green, and blue (RGB; Red Green Blue) are provided. A black matrix 96 as a light shielding film is provided between the color filters 95 for each color. An RGB color filter 95 is disposed on the display electrode 74. A black matrix 96 is disposed on the TFT 106.
[0016]
Next, a method of manufacturing the pixel 102 (pixel unit 101) in the conventional LCD configured as described above will be sequentially described.
Step 1 (see FIG. 13A): A chromium film 61 is formed on the transparent insulating substrate 71 using a sputtering method.
[0017]
Step 2 (see FIG. 13B): A resist pattern 62 for forming the gate electrode 76 and the auxiliary capacitance electrode 77 is formed on the chromium film 61.
Step 3 (see FIG. 13C); the chromium film 61 is etched by wet etching using the resist pattern 62 as an etching mask, thereby forming the gate electrode 76 and the auxiliary capacitance electrode 77 made of the chromium film 61. To do.
[0018]
At this time, since the etching solution enters the interface between the both ends of the resist pattern 62 and the chromium film 61, an undercut 61 a is generated in the chromium film 61 located at both ends of the resist pattern 62. Due to the undercut 61 a generated in the chromium film 61, the cross-sectional shapes of the gate electrode 76 and the auxiliary capacitance electrode 77 are tapered with the center portion being flat and the both end portions being inclined. In the following description, the flat portion at the center of the gate electrode 76 is referred to as a flat portion 76a, and the inclined end portions are referred to as tapered portions 76b.
[0019]
Step 4 (see FIG. 13D): A silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film are formed on the electrodes 76 and 77 and the transparent insulating substrate 71 by using a plasma CVD (Chemical Vapor Deposition) method. 63 is formed continuously. As a result, a gate insulating film 80 composed of the respective films 78 and 79 is formed, and a device structure in which the amorphous silicon film 63 is formed thereon is obtained.
[0020]
Next, annealing (processing temperature; about 400 ° C.) is performed, and dehydrogenation processing for removing hydrogen taken into the amorphous silicon film 63 is performed.
Subsequently, by irradiating the surface of the amorphous silicon film 63 with excimer laser light, the amorphous silicon film 63 is heated and crystallized to form a polycrystalline silicon film 81. As described above, the laser annealing method using excimer laser light is called an ELA (Excimer Laser Anneal) method.
[0021]
Thereafter, the drain region 82 and the source region 83 are formed in the polycrystalline silicon film 81, and each member shown in FIG. 12 is formed, whereby the pixel portion 101 including each pixel 102 is completed.
[0022]
Incidentally, the tapered portion 76 b is provided in the gate electrode 76 in order to ensure the withstand voltage of the gate insulating film 80 and the dielectric film 84. That is, when the gate electrode 76 does not have the taper portion 76 b, electrolytic concentration tends to occur at the end portion of the gate electrode 76. In addition, when the gate electrode 76 does not have the taper portion 76b, the step coverage of the gate insulating film 80 located on the quad portions at both ends of the gate electrode 76 is deteriorated, and the thickness of the gate insulating film 80 in that portion is reduced. getting thin. As a result, the withstand voltage of the gate insulating film 80 at the end of the gate electrode 76 may be reduced. If the gate electrode 76 is provided with the tapered portion 76b, the electrolytic concentration at the end of the gate electrode 76 is eased and the step coverage of the gate insulating film 80 at the end of the gate electrode 76 is improved. It is possible to prevent the gate insulating film 80 from becoming thin.
[0023]
[Problems to be solved by the invention]
The gate electrode 76 is formed from a chromium film 61 having a high thermal conductivity. Therefore, the annealing temperature of the amorphous silicon film 63 formed on the gate electrode 76 is the amorphous temperature formed on the transparent insulating substrate 71 due to heat escape from the gate electrode 76 when performing the ELA method. It becomes lower than the temperature of the silicon film 63. The cross-sectional shape of the gate electrode 76 is tapered, and includes a flat portion 76a at the center and tapered portions 76b inclined at both ends. Since the heat transfer rate from the tapered portion 76b of the gate electrode 76 is smaller than that of the flat portion 76a, the annealing temperature of the amorphous silicon film 63 formed on the tapered portion 76b is higher than that on the flat portion 76a. Become higher.
[0024]
In other words, the amorphous silicon film 63 formed on the gate electrode 76 requires higher laser crystallization energy than the amorphous silicon film 63 formed on the transparent insulating substrate 71. On the gate electrode 76, the amorphous silicon film 63 formed on the flat portion 76a has higher laser crystallization energy than the amorphous silicon film 63 formed on the tapered portion 76b. Necessary. That is, the laser crystallization energy required for the amorphous silicon film 63 decreases in the order on the transparent insulating substrate 71 → on the tapered portion 76b → on the flat portion 76a.
[0025]
The higher the laser irradiation energy during ELA, the larger the grain size (crystal grain size) of the polycrystalline silicon film 81. Therefore, the grain size of the polycrystalline silicon film 81 formed on the gate electrode 76 is smaller than that of the polycrystalline silicon film 81 formed on the transparent insulating substrate 71. Then, on the gate electrode 76, the polycrystalline silicon film 81 formed on the flat portion 76a has a grain size smaller than that of the polycrystalline silicon film 81 formed on the tapered portion 76b. That is, the grain size of the polycrystalline silicon film 81 decreases in order of the transparent insulating substrate 71, the taper portion 76b, and the flat portion 76a.
[0026]
Here, the polycrystalline silicon film 81 formed on the flat portion 76 a of the gate electrode 76 corresponds to the channel region 93. The polycrystalline silicon film 81 formed on the tapered portion 76 b of the gate electrode 76 corresponds to the low concentration regions 82 a and 83 a of the drain region 82 or the source region 83. The polycrystalline silicon film 81 formed on the transparent insulating substrate 71 corresponds to the high concentration regions 82 b and 83 b of the drain region 82 or the source region 83. Therefore, the grain size of the polycrystalline silicon film 81 decreases in the order of the high concentration regions 82b and 83b → the low concentration regions 82a and 83a → the channel region 93.
[0027]
FIG. 14 shows the relationship between the laser irradiation energy during ELA and the grain size of each part of the polycrystalline silicon film 81.
In the polycrystalline silicon film 81, when the laser crystallization energy value is E1, the grain size of the portions corresponding to the high concentration regions 82b and 83b (portions on the transparent insulating substrate 71) has a peak value. When the laser crystallization energy value is E2, the grain size of the portions corresponding to the low concentration regions 82a and 83a (portions on the taper portion 76b) has a peak value. When the laser crystallization energy value is E3, the grain size of the portion corresponding to the channel region 93 (portion on the flat portion 76a) takes a peak value. These laser crystallization energy values E1, E2, and E3 have a relationship of E1 <E2 <E3.
[0028]
As described above, when the grain size of the polycrystalline silicon film 81 is nonuniform in each portion, the element characteristics of the TFT 106 become nonuniform. In particular, as the grain size on the taper portion 76b becomes non-uniform, the sheet resistances of the regions 82a and 83a vary greatly, and the on-current of the TFT 106 varies. This is because the sheet resistance of each of the regions 82a and 83a directly acts as a parasitic resistance.
[0029]
Of the TFTs 106 formed on the transparent insulating substrate 71, when the element characteristics of a certain number of TFTs 106 become non-uniform or the on-current becomes less than a required value, the pixel unit 101 using the transparent insulating substrate 71 is It must be discarded as a defective product. In addition, when some element characteristics of the TFTs 106 formed on the transparent insulating substrate 71 are not uniform or the on-current is less than a required value, display unevenness occurs in the pixel portion 101. That is, non-uniformity in the element characteristics of the TFT 106 and a decrease in on-state current cause a decrease in the yield of the pixel portion 101 and a display defect.
[0030]
The present invention has been made to solve the above problems, and has the following objects..
[0031]
  ElementaryProvided is a method for manufacturing a thin film transistor capable of preventing non-uniform characteristics and a decrease in on-state current.
  WalkActive matrix type display device capable of preventing yield loss and display failure, Contact image sensor, 3D ICI will provide a.
[0032]
[Means for Solving the Problems]
  The invention according to claim 1 is provided on an insulating substrate.Made of refractory metal or refractory metal alloyForming a gate electrode; forming a gate insulating film on the insulating substrate and on the gate electrode; forming an amorphous silicon film on the gate insulating film so as to have a flat surface; In the method of manufacturing a thin film transistor, the step of crystallizing the amorphous silicon film by irradiating the surface of the amorphous silicon film with a laser beam to form a polycrystalline silicon film is performed. In the step of forming the film, the drain and source regions in the polycrystalline silicon filmThe part corresponding toThe channel region in the polycrystalline silicon filmThe part corresponding toThe drain and source regions are formed to be thicker thanThe part corresponding toEnergy required for crystallization inWhenThe channel regionThe part corresponding toEnergy required for crystallization inAnd evenlyThe gist of the invention is to make the grain sizes of the drain, source region and channel region uniform.
[0033]
  The invention according to claim 2 is provided on an insulating substrate.Made of refractory metal or refractory metal alloyForming a gate electrode; forming a gate insulating film on the insulating substrate and on the gate electrode; forming an amorphous silicon film on the gate insulating film; and the amorphous silicon film A step of forming an insulating film with a flat surface on the surface and irradiating the surface of the amorphous silicon film with a laser beam through the flat insulating film to crystallize the amorphous silicon film to Forming a crystalline silicon film and etching the flat insulating film;Ion implantation maskAnd forming a drain, a source region, and a channel region in the polycrystalline silicon film.The insulating film on the amorphous silicon film is formed so that the film thickness of the part corresponding to the drain and source regions is larger than the film thickness of the part corresponding to the channel region.The gist.
  The invention according to claim 3Forming a gate electrode made of a refractory metal or a refractory metal alloy on an insulating substrate, forming a gate insulating film on the insulating substrate and the gate electrode, and forming an amorphous on the gate insulating film A step of forming a silicon film; a step of forming an insulating film having a flat surface on the amorphous silicon film; and irradiating the surface of the amorphous silicon film with the laser light through the flat insulating film. Thus, in the method of manufacturing a thin film transistor, the step of crystallizing the amorphous silicon film to form a polycrystalline silicon film, wherein the step of forming the polycrystalline silicon film includes: The insulating film is formed so that the film thickness of the portion corresponding to the drain and source regions is larger than the film thickness of the portion corresponding to the channel region, thereby corresponding to the drain and source regions. The gist of the present invention is to make the energy required for crystallization in a minute and the energy required for crystallization in a portion corresponding to the channel region uniform, and to make the grain sizes of the drain, source region, and channel region uniform. .
[0034]
  Claim4The invention described in claim 1~ClaimAny one item of 3In the method of manufacturing a thin film transistor described in (1), the gist is that the laser light is KrF excimer laser light or ArF excimer laser light.
[0035]
  Claim5The invention described in claim 14An active matrix display device using the thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of the above is the gist.
[0036]
  Claim6The invention described in claim 14The gist of the contact image sensor using the thin film transistor manufactured by the method of manufacturing a thin film transistor described in any one of the above.
[0037]
  Claim7The invention described in claim 14The gist is a three-dimensional IC using the thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of the above.
[0045]
In the embodiments of the invention described below, the “high thermal conductive film” described in the claims or means for solving the problems is composed of the silicon oxide film 22, and the “high thermal conductive insulating film” is also a transparent material. It is comprised from the photoconductive high heat conductive insulating films 33 and 42.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members as those in the conventional embodiment shown in FIGS. 10 to 13 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0047]
(First embodiment)
FIG. 1 shows a schematic cross section of a pixel 102 (pixel portion 101) in the LCD of the first embodiment having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as the TFT 106.
[0048]
The present embodiment is different from the conventional embodiment shown in FIG. 12 in the following points.
[1] The surface of the polycrystalline silicon film 11 serving as an active layer of the TFT 106 is flattened, and the film thickness of the portion corresponding to the drain region 82 and the source region 83 is equal to the film thickness of the portion corresponding to the channel region 93. It is thicker than that.
[0049]
[2] The grain size of each part of the polycrystalline silicon film 11 is substantially uniform.
Next, the manufacturing method of this embodiment is demonstrated sequentially.
[0050]
Step 1 (see FIG. 2 (a)) to step 3 (see FIG. 2 (c)); the same as the conventional step 1 (see FIG. 13 (a)) to step 3 (see FIG. 13 (c)). is there.
Step 4 (see FIG. 2D): A silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 12 are successively formed on the electrodes 76 and 77 and the transparent insulating substrate 71 using a plasma CVD method. Form. As a result, a gate insulating film 80 composed of the films 78 and 79 is formed, and the amorphous silicon film 12 is formed thereon. Here, the amorphous silicon film 12 is formed thicker than the conventional amorphous silicon film 63. Then, the surface of the amorphous silicon film 12 is flattened by using an entire etch back method.
[0051]
Next, annealing (processing temperature; about 400 ° C.) is performed, and dehydrogenation processing is performed to remove hydrogen taken into the amorphous silicon film 12.
Subsequently, by using the ELA method, the surface of the amorphous silicon film 12 is irradiated with excimer laser light, whereby the amorphous silicon film 12 is heated and crystallized to form the polycrystalline silicon film 11. At this time, the excimer laser beam having a sheet beam shape or a rectangular beam shape is irradiated with pulses. The irradiation area of the laser beam is about 150 × 0.3 mm, and the entire surface of the amorphous silicon film 12 on the transparent insulating substrate 71 is irradiated while shifting the position of the laser beam.
[0052]
Here, the surface of the amorphous silicon film 12 is flattened, and the thickness of the portion corresponding to the drain region 82 and the source region 83 is larger than the thickness of the portion corresponding to the channel region 93. Yes.
[0053]
Therefore, since the amorphous silicon film on each of the regions 82 and 83 has a large film thickness, it requires a large irradiation energy for crystallization, and the grain size of the crystallized polycrystalline silicon film is smaller than that of the conventional form. . Therefore, the difference in grain size between the polycrystalline silicon film in the channel region and the polycrystalline silicon film in the drain / source region in the conventional form becomes smaller and narrower.
[0054]
On the gate electrode 76, the amorphous silicon film 12 formed on the tapered portion 76b also requires higher irradiation energy than the amorphous silicon film 12 formed on the flat portion 76a. However, the grain size difference of the polycrystalline silicon film is smaller than that of the conventional configuration. Further, the amorphous silicon film 12 formed on the tapered portion 76b on the gate electrode 76 also has higher irradiation energy due to crystallization than the amorphous silicon film 12 formed on the flat portion 76a. Although necessary, the grain size difference of the polycrystalline silicon film is smaller than in the conventional embodiment.
[0055]
That is, although the laser crystallization energy required for the amorphous silicon film 12 is large in the transparent insulating substrate 71, the tapered portion 76b, and the flat portion 76a, the grain size difference of the polycrystalline silicon film in each portion is Smaller than the form. That is, by planarizing the surface of the amorphous silicon film 12, the laser crystallization energy applied to each portion of the amorphous silicon film 12 can be brought close to the optimum condition.
[0056]
As a result, the grain size of each part of the polycrystalline silicon film 11 is substantially uniform as compared with the grain size of each part of the polycrystalline silicon film 81 of the conventional form. FIG. 3 shows the relationship between the laser irradiation energy during ELA and the grain size of each part of the polycrystalline silicon film 11.
[0057]
In the polycrystalline silicon film 11, when the laser crystallization energy value is E1 ', the grain size of the portions corresponding to the high concentration regions 82b and 83b (portions on the transparent insulating substrate 71) has a peak value. When the laser crystallization energy value is E2 ', the grain size of the portion corresponding to the low concentration regions 82a and 83a (portion on the tapered portion 76b) takes a peak value. When the laser crystallization energy value is E3, the grain size of the portion corresponding to the channel region 93 (portion on the flat portion 76a) takes a peak value. These laser crystallization energy values E1 ', E2', and E3 have a relationship of E1 '<E2' <E3. However, the values E1 'and E2' are higher than the values E1 and E2 of the conventional form. That is, the values E1 ', E2', E3 are closer to each other, and the crystallized polycrystalline silicon film is made more uniform.
[0058]
Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 11, and each member shown in FIG. 1 is formed, whereby the pixel portion 101 including each pixel 102 is completed.
[0059]
Thus, according to this embodiment, the following operations and effects can be obtained.
(1) In the polycrystalline silicon film 11 serving as an active layer of the TFT 106, the grain size of each portion is substantially uniform. Therefore, the element characteristics of the TFT 106 are made uniform. Further, the grain sizes of the regions 82a and 83a can be made uniform, and the on-current of the TFT 106 can be stabilized.
[0060]
(2) From (1) above, it becomes possible to stabilize the element characteristics of all TFTs 106 formed on the transparent insulating substrate 71 and to increase the on-current to a required value or more, and to reduce the yield of the pixel portion 101. And display defects can be prevented.
[0061]
(3) As described in (1) above, in order to make the grain size of each part of the polycrystalline silicon film 11 substantially uniform, the amorphous silicon film 12 is formed thick and then the surface thereof is flattened. It is only necessary to perform the ELA method in the same manner as in the first embodiment. Therefore, its implementation is simple and easy.
[0062]
(4) Since the surface of the amorphous silicon film 12 is flattened, it is easy to uniformly irradiate the entire surface of the amorphous silicon film 12 with excimer laser light. Therefore, the laser crystallization energy applied to each portion of the amorphous silicon film 12 can be easily made uniform, and the function and effect (1) can be further enhanced.
[0063]
(Second Embodiment)
FIG. 4 shows a schematic cross section of the pixel 102 (pixel unit 101) in the LCD of the second embodiment having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as the TFT 106. FIG.
[0064]
In the present embodiment, the difference from the conventional form shown in FIG. 12 is that the grain size of each part of the polycrystalline silicon film 21 that becomes the active layer of the TFT 106 is substantially uniform.
Next, the manufacturing method of this embodiment is demonstrated sequentially.
[0065]
Step 1 (see FIG. 5 (a)) to step 3 (see FIG. 5 (c)); same as step 1 (see FIG. 13 (a)) to step 3 (see FIG. 13 (c)) of the conventional form. is there.
Step 4 (see FIG. 5D): Using the plasma CVD method, a silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are successively formed on the electrodes 76 and 77 and the transparent insulating substrate 71. Form. As a result, a gate insulating film 80 composed of the films 78 and 79 is formed, and an amorphous silicon film 63 is formed thereon.
[0066]
Next, annealing (processing temperature; about 400 ° C.) is performed, and dehydrogenation processing for removing hydrogen taken into the amorphous silicon film 63 is performed.
Step 5 (see FIG. 5E): A thick silicon oxide film 22 is formed on the amorphous silicon film 63 by CVD. Then, the entire surface of the silicon oxide film 22 is flattened by using the entire surface etch back method.
[0067]
Subsequently, the ELA method is used to irradiate the surface of the amorphous silicon film 63 through the silicon oxide film 22 with excimer laser light so that the amorphous silicon film 63 is heated and crystallized, and polycrystalline silicon is obtained. A film 21 is formed.
[0068]
Here, the surface of the silicon oxide film 22 is flattened, and the thickness of the portion corresponding to the drain region 82 and the source region 83 is larger than the thickness of the portion corresponding to the channel region 93. Therefore, when performing the ELA method, the laser irradiation energy is more attenuated on the drain / source region than on the channel region by the silicon oxide film on the surface. As a result, the crystallization energy effectively applied to the amorphous silicon film becomes lower as the surface silicon oxide film becomes thicker, and becomes harder to crystallize on the drain / source region (insulating substrate).
[0069]
As the excimer laser light, it is desirable to use light having a wavelength that is easily absorbed by the silicon oxide film 22, and specifically, KrF excimer laser light (wavelength: 248 nm) or ArF excimer laser light (wavelength: 198 nm). Use it.
[0070]
As a result, the annealing arrival temperature of each part of the amorphous silicon film 63 of this embodiment can be made substantially uniform as compared with the arrival temperature of each part of the amorphous silicon film 63 of the conventional form. Become. That is, by forming the silicon oxide film 22 on the amorphous silicon film 63 and flattening the surface of the silicon oxide film 22, effective laser crystallization given to each part of the amorphous silicon film 63. Energy can be brought close to optimal conditions. Therefore, the grain size of each part of the polycrystalline silicon film 21 is substantially uniform as compared with the grain size of each part of the polycrystalline silicon film 81 of the conventional form.
[0071]
Thereafter, a photoresist film (not shown) is formed on the silicon oxide film 22, exposed from the back surface (the surface on which the TFT 106 is not formed) of the transparent insulating substrate 71, and developed, whereby the gate electrode 76 and the auxiliary capacitance electrode 77 are formed. Only the photoresist film at the corresponding position is left. Then, the stopper layer 94 made of the silicon oxide film 22 is formed by etching the silicon oxide film 22 using a wet etching method using the remaining photoresist film as an etching mask.
[0072]
Next, the drain region 82 and the source region 83 are formed in the polycrystalline silicon film 21 using the stopper layer 94 as an ion implantation mask. Subsequently, by forming each member shown in FIG. 4, the pixel portion 101 including each pixel 102 is completed.
[0073]
Thus, according to this embodiment, the following operations and effects can be obtained.
{1} In the polycrystalline silicon film 21 serving as an active layer of the TFT 106, the grain size of each portion is substantially uniform. Therefore, the same operations and effects as the above (1) and (2) of the first embodiment can be obtained.
{2} As in {1} above, in order to make the grain size of each part of the polycrystalline silicon film 21 substantially uniform, the silicon oxide film 22 is formed thick on the amorphous silicon film 63 and then the surface thereof is flattened. Then, it is only necessary to perform the ELA method as in the conventional embodiment. Therefore, its implementation is simple and easy.
[0074]
Since the {3} silicon oxide film 22 becomes the stopper layer 94 in a later process, the formation of the silicon oxide film 22 does not complicate the entire process.
(Third embodiment)
FIG. 6 shows a schematic cross section of the pixel 102 (pixel portion 101) in the LCD of the third embodiment having a transmission type configuration using a bottom gate structure polycrystalline silicon TFT as the TFT 106. FIG.
[0075]
The present embodiment is different from the conventional embodiment shown in FIG. 12 in the following points.
(1) The cross-sectional shapes of the gate electrode 31 of the TFT 106 and the auxiliary capacitance electrode 32 of the auxiliary capacitance SC are rectangular, and no tapered portion as in the conventional configuration is provided.
[0076]
(2) A translucent high thermal conductive insulating film 33 is formed between the gate electrode 31 and the auxiliary capacitance electrode 32. That is, the translucent high thermal conductive insulating film 33 is formed so as to sandwich the gate electrode 31. And the surface which consists of each electrode 31 and 32 and the translucent high heat conductive insulating film 33 is planarized.
[0077]
(3) The grain size of each portion of the polycrystalline silicon film 34 that becomes the active layer of the TFT 106 is substantially uniform. The thickness of the polycrystalline silicon film 34 is uniform, and the lower side of the polycrystalline silicon film 34 (the electrodes 31 and 32 and the translucent high thermal conductive insulating film 33) is formed as described in (2) above. Since the surface is planarized, the surface of the polycrystalline silicon film 34 is also planarized.
[0078]
Next, the manufacturing method of this embodiment is demonstrated sequentially.
Step 1 (see FIG. 7A); A translucent high thermal conductive insulating film 33 is formed on the transparent insulating substrate 71. The translucent high heat conductive insulating film 33 includes a diamond thin film.
[0079]
Step 2 (see FIG. 7B): A resist pattern 35 for forming the gate electrode 31 and the auxiliary capacitance electrode 32 is formed on the translucent high thermal conductive insulating film 33.
Step 3 (see FIG. 7C): The light-transmitting high heat conductive insulating film 33 is etched by etching the light transmitting high heat conductive insulating film 33 using an anisotropic etching method using the resist pattern 35 as an etching mask. A recess 33a is formed on the transparent insulating substrate 71 from the recess 33a.
[0080]
Next, using a sputtering method, a chromium film 61 is formed on the transparent insulating substrate 71 exposed from the translucent high heat conductive insulating film 33 and the concave portion 33a, and the concave portion 33a of the translucent high heat conductive insulating film 33 is formed into the chromium film. Embed by 61.
[0081]
Step 4 (see FIG. 7D): The entire surface etch-back method is used to remove the chromium film 61 formed on the light-transmitting high heat conductive insulating film 33, so that the light transmitting high heat conductive insulating film 33 and chromium are removed. The surface made of the film 61 is flattened. As a result, the gate electrode 31 and the auxiliary capacitance electrode 32 made of the chromium film 61 embedded in the concave portion 33a of the translucent high thermal conductive insulating film 33 are formed.
[0082]
Step 5 (see FIG. 7 (e)): A silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are formed on the electrodes 31, 32 and the translucent high thermal conductive insulating film 33 by using a plasma CVD method. Are formed continuously. As a result, a gate insulating film 80 composed of the films 78 and 79 is formed, and an amorphous silicon film 63 is formed thereon. Here, since the device surface comprising the electrodes 31 and 32 and the translucent high thermal conductive insulating film 33 is flattened, the surfaces of the films 78, 79 and 63 formed with a uniform film thickness thereon are also included. All are flattened.
[0083]
Next, annealing (processing temperature; about 400 ° C.) is performed, and dehydrogenation processing for removing hydrogen taken into the amorphous silicon film 63 is performed.
Subsequently, by using the ELA method, the surface of the amorphous silicon film 63 is irradiated with excimer laser light, whereby the amorphous silicon film 63 is heated and crystallized to form a polycrystalline silicon film 34.
[0084]
Here, between the gate electrode 31 and the auxiliary capacitance electrode 32, a translucent high thermal conductive insulating film 33 is formed. Therefore, when performing the ELA method, the heat escape from the amorphous silicon film on the insulating substrate to the substrate is not significantly different from the heat escape from the amorphous silicon film on the gate electrode. Therefore, the annealing temperature of each part of the amorphous silicon film 63 can be made substantially uniform as compared with the annealing temperature of each part of the amorphous silicon film 63 of the conventional form. That is, by providing the translucent high thermal conductive insulating film 33 between the electrodes 31 and 32, the laser crystallization energy required for each part of the amorphous silicon film 63 can be made closer to the optimum condition. Therefore, the grain size of each part of the polycrystalline silicon film 34 is substantially uniform as compared with the grain size of each part of the polycrystalline silicon film 81 of the conventional form.
[0085]
Thereafter, a drain region 82 and a source region 83 are formed in the polycrystalline silicon film 34, and each member shown in FIG. 6 is formed, whereby the pixel portion 101 including each pixel 102 is completed.
[0086]
Thus, according to this embodiment, the following operations and effects can be obtained.
<1> In the polycrystalline silicon film 34 serving as an active layer of the TFT 106, the grain size of each portion is substantially uniform. Therefore, the same operations and effects as the above (1) and (2) of the first embodiment can be obtained.
[0087]
<2> In order to make the grain size of each part of the polycrystalline silicon film 34 substantially uniform as described in <1> above, a translucent high thermal conductive insulating film 33 is provided between the gate electrode 31 and the auxiliary capacitance electrode 32. Then, after the gate insulating film 80 and the amorphous silicon film 63 are sequentially formed thereon, it is only necessary to perform the ELA method as in the conventional embodiment. Therefore, its implementation is simple and easy.
[0088]
<3> Since the surface of the amorphous silicon film 63 is planarized, it is easy to uniformly irradiate the entire surface of the amorphous silicon film 63 with excimer laser light. Therefore, the laser crystallization energy applied to each part of the amorphous silicon film 63 can be easily made uniform, and the operation and effect of the above <1> can be further enhanced.
[0089]
<4> Although the gate electrode 31 is not provided with a taper portion, the surface composed of the electrodes 31 and 32 and the light-transmitting high thermal conductive insulating film 33 is flattened. Therefore, the surface of the gate insulating film 80 is also flattened, the film thickness is made uniform, and it is not partially thinned. Further, no electrolytic concentration occurs at the end of the gate electrode 76. Therefore, a sufficient withstand voltage of the gate electrode 31 can be ensured.
[0090]
(Fourth embodiment)
FIG. 8 shows a schematic cross section of the pixel 102 (pixel portion 101) in the LCD of the fourth embodiment having a transmissive configuration using a bottom gate polycrystalline silicon TFT as the TFT 106. FIG.
[0091]
The present embodiment is different from the conventional embodiment shown in FIG. 12 in the following points.
(1) A translucent high thermal conductive insulating film 42 is formed on the entire surface of the transparent insulating substrate 71, and a gate electrode 76 and an auxiliary capacitance electrode 77 are formed on the translucent high thermal conductive insulating film 42.
[0092]
(2) The grain size of each portion of the polycrystalline silicon film 41 that becomes the active layer of the TFT 106 is substantially uniform.
Next, the manufacturing method of this embodiment is demonstrated sequentially.
[0093]
Step 1 (see FIG. 9A); A translucent high thermal conductive insulating film 42 is formed on the transparent insulating substrate 71. The translucent high thermal conductive insulating film 42 includes a diamond thin film. Next, a chromium film 61 is formed on the translucent high thermal conductive insulating film 42 by sputtering.
[0094]
Step 2 (see FIG. 9B) to Step 3 (see FIG. 9C); the same as Step 2 (see FIG. 13B) to Step 3 (see FIG. 13C) of the conventional form. is there.
Step 4 (see FIG. 9D): A silicon nitride film 78, a silicon oxide film 79, and an amorphous silicon film 63 are formed on the electrodes 76 and 77 and the light-transmitting high thermal conductive insulating film 42 by using a plasma CVD method. Are formed continuously. As a result, a device structure is obtained in which the gate insulating film 80 composed of the respective films 78 and 79 is formed on the translucent high thermal conductive insulating film 42 and the amorphous silicon film 63 is formed thereon.
[0095]
Next, annealing (processing temperature; about 400 ° C.) is performed, and dehydrogenation processing for removing hydrogen taken into the amorphous silicon film 63 is performed.
Subsequently, by using an ELA method, the surface of the amorphous silicon film 63 is irradiated with excimer laser light, whereby the amorphous silicon film 63 is heated and crystallized to form a polycrystalline silicon film 41.
[0096]
Here, since the translucent high thermal conductive insulating film 42 is formed on the lower side of the gate electrode 76, the heat escape from the amorphous silicon film on the insulating substrate to the substrate is caused by the amorphous on the gate electrode. The heat escape and large difference from the quality silicon film are eliminated. Therefore, the annealing temperature of each part of the amorphous silicon film 63 can be made substantially uniform as compared with the annealing temperature of each part of the amorphous silicon film 63 of the conventional form. That is, by providing the translucent high thermal conductive insulating film 33 between the electrodes 31 and 32, the laser crystallization energy required for each part of the amorphous silicon film 63 can be made closer to the optimum condition. Therefore, the grain size of each part of the polycrystalline silicon film 34 is substantially uniform as compared with the grain size of each part of the polycrystalline silicon film 81 of the conventional form.
[0097]
Thereafter, the drain region 82 and the source region 83 are formed in the polycrystalline silicon film 41, and each member shown in FIG. 8 is formed, whereby the pixel portion 101 including each pixel 102 is completed.
[0098]
Thus, according to this embodiment, the following operations and effects can be obtained.
[1] In the polycrystalline silicon film 41 serving as an active layer of the TFT 106, the grain size of each portion is substantially uniform. Therefore, the same operations and effects as the above (1) and (2) of the first embodiment can be obtained.
[0099]
[2] As described in [1] above, in order to make the grain size of each part of the polycrystalline silicon film 41 substantially uniform, a translucent high thermal conductive insulating film 42 is formed on the transparent insulating substrate 71, and on it. After the gate electrode 76, the gate insulating film 80, and the amorphous silicon film 63 are sequentially formed, the ELA method may be performed as in the conventional embodiment. Therefore, its implementation is simple and easy.
[0100]
Each of the above embodiments may be modified as follows, and even in that case, the same operation and effect can be obtained.
[1] In step 4 of the first embodiment, the amorphous silicon film 12 having a flat surface is formed by using a bias sputtering method, instead of using the plasma CVD method and the entire surface etchback method.
[0101]
[2] In step 4 of the second embodiment, the silicon oxide film 22 having a flat surface is formed by using a bias sputtering method, instead of using the CVD method and the entire surface etchback method.
[0102]
[3] In the step 4 of the second embodiment, the planarization step by the entire etch back method is omitted by using the silicon oxide film 22 having a flat surface made of a TEOS (TetraEthyl OrthSilicate) film.
[0103]
[4] In the first, second, and fourth embodiments, the tapered portion 76b of the gate electrode 76 is omitted. In this case, although the operation and effect obtained by providing the tapered portion 76b as described above cannot be obtained, the operation and effect described for each embodiment can be similarly obtained.
[0104]
[5] The gate electrodes 76 and 31 and the auxiliary capacitance electrodes 77 and 32 are made of refractory metals other than the chromium film 61 (molybdenum, tungsten, tantalum, hafnium, zirconium, niobium, titanium, vanadium, rhenium, iridium, osmium, rhodium, etc. ) A single film, a refractory metal alloy film, or a multi-layered refractory metal film.
[0105]
[6] The TFT 106 has a single drain structure or a multi-gate structure instead of the LDD structure.
[7] The transparent insulating substrate 71 is replaced with an insulating layer such as a ceramic substrate or a silicon oxide film, and applied to a contact image sensor or a three-dimensional IC instead of an LCD.
[0106]
[8] The TFT 106 is applied to a pixel driving element in an active matrix display device using an electroluminescence element as a pixel.
Each embodiment has been described above, but technical ideas other than the claims that can be grasped from each embodiment will be described below together with their effects.
[0107]
  (I)in frontThe laser beam is an excimer laser beam.
  In this way, efficient crystallization can be performed.
[0108]
  (B)in frontThe laser beam is an excimer laser beam, and the excimer laser beam is a method for manufacturing a display device having a wavelength that is easily absorbed by the flat insulating film.
[0109]
  In this way, excimer laser light is partially absorbed by the insulating film., EffectThe fruit can be further enhanced.
[0110]
【The invention's effect】
  Claims 1 to4According to the invention described in (1), when the polycrystalline silicon film is formed from the amorphous silicon film, the grain size of each portion of the polycrystalline silicon film becomes uniform.
[0114]
  Also,It is possible to provide a method for manufacturing a thin film transistor capable of preventing nonuniform element characteristics and a decrease in on-state current.
[0117]
  Claim5~7According to the invention described in (1), it is possible to provide an active matrix type display device, a contact image sensor, and a three-dimensional IC capable of preventing a decrease in yield and display failure.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a pixel according to a first embodiment.
FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.
FIG. 3 is a characteristic diagram for explaining the operation of the first embodiment.
FIG. 4 is a schematic cross-sectional view of a pixel according to a second embodiment.
FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the second embodiment.
FIG. 6 is a schematic cross-sectional view of a pixel according to a third embodiment.
FIG. 7 is a schematic cross-sectional view for explaining a manufacturing process of the third embodiment.
FIG. 8 is a schematic cross-sectional view of a pixel according to a fourth embodiment.
FIG. 9 is a schematic cross-sectional view for explaining a manufacturing process of the fourth embodiment.
FIG. 10 is a block diagram of an active matrix LCD.
FIG. 11 is an equivalent circuit diagram of a pixel.
FIG. 12 is a schematic cross-sectional view of a conventional pixel.
FIG. 13 is a schematic cross-sectional view for explaining a conventional manufacturing process.
FIG. 14 is a characteristic diagram for explaining the operation of a conventional embodiment.
[Explanation of symbols]
11, 21, 34, 41 ... polycrystalline silicon film
12, 63 ... amorphous silicon film
22: Silicon oxide film as a flat insulating film
33, 42 ... Translucent high thermal conductive insulating film
71 ... Transparent insulating substrate
76, 31 ... gate electrode
80 ... Gate insulating film
82 ... Drain region
83 ... Source region
82a, 83a ... low concentration region
82b, 83b ... high concentration region
93 ... Channel region
101: Pixel portion
106 ... TFT

Claims (7)

Forming a gate electrode made of a refractory metal or a refractory metal alloy on an insulating substrate;
Forming a gate insulating film on the insulating substrate and the gate electrode;
Forming an amorphous silicon film on the gate insulating film so as to have a flat surface;
In the method of manufacturing a thin film transistor, the step of crystallizing the amorphous silicon film by irradiating the surface of the amorphous silicon film with a laser beam to form a polycrystalline silicon film,
In the step of forming the polycrystal silicon film, the film thickness of the portion corresponding to the drain and source regions in the polycrystal silicon film is made thicker than the thickness of the portion corresponding to the channel region in the polycrystal silicon film. in said drain, a uniform and energy required for crystallization in the portion corresponding to the energy and the channel region necessary for crystallization of the part corresponding to the source region, the drain, grain size of the source region and the channel region A method of manufacturing a thin film transistor, characterized by making the thickness uniform. Forming a gate electrode made of a refractory metal or a refractory metal alloy on an insulating substrate;
Forming a gate insulating film on the insulating substrate and the gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming an insulating film having a flat surface on the amorphous silicon film;
Irradiating the surface of the amorphous silicon film with a laser beam through the flat insulating film to crystallize the amorphous silicon film to form a polycrystalline silicon film;
Forming an ion implantation mask by etching the flat insulating film;
Forming a drain, source region, and channel region in the polycrystalline silicon film, and the insulating film on the amorphous silicon film has a thickness corresponding to the drain and source regions corresponding to the channel region. A method for manufacturing a thin film transistor, wherein the thin film transistor is formed so as to be thicker than a film thickness of a portion to be processed. Forming a gate electrode made of a refractory metal or a refractory metal alloy on an insulating substrate;
Forming a gate insulating film on the insulating substrate and the gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming an insulating film having a flat surface on the amorphous silicon film;
Irradiating the surface of the amorphous silicon film with a laser beam through the flat insulating film to crystallize the amorphous silicon film to form a polycrystalline silicon film;
In the method of manufacturing a thin film transistor for performing
In the step of forming the polycrystalline silicon film, the insulating film on the amorphous silicon film is formed such that the thickness of the portion corresponding to the drain and source regions is larger than the thickness of the portion corresponding to the channel region. By forming the drain region, the energy necessary for crystallization in the portion corresponding to the drain and source regions and the energy necessary for crystallization in the portion corresponding to the channel region are made uniform, and the drain, source region, and channel region are formed. A method for producing a thin film transistor, wherein the grain size of the thin film transistor is made uniform . Any Oite to the method of manufacturing the thin film transistor according to item 1, the method of manufacturing the thin film transistor wherein the laser beam is a KrF excimer laser or ArF excimer laser light in the claims 1 to 3. An active matrix type display device using, as a pixel driving element, a thin film transistor manufactured by the thin film transistor manufacturing method according to claim 1 . A contact image sensor using a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1 . A three-dimensional IC using a thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 1 to 4 .

Images