JP3239024B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3239024B2
JP3239024B2 JP23552194A JP23552194A JP3239024B2 JP 3239024 B2 JP3239024 B2 JP 3239024B2 JP 23552194 A JP23552194 A JP 23552194A JP 23552194 A JP23552194 A JP 23552194A JP 3239024 B2 JP3239024 B2 JP 3239024B2
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film
step
forming
layer
electrode
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JPH0895085A (en
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英二 田口
清 米田
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三洋電機株式会社
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D70/00Techniques for reducing energy consumption in wireless communication networks

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device .

[0002]

2. Description of the Related Art In recent years, thin film transistors (TFTs) have been developed.
Active matrix liquid crystal display (LCD; Liquid Crystal Displ) using Film Transistor
ay) has attracted attention as a high-quality display device.

[0003] There are a simple matrix system and an active matrix system in a dot matrix LCD which performs display by dots arranged in a matrix. The simple matrix method is a method in which the liquid crystal of each pixel arranged in a matrix is directly driven from the outside in synchronization with a scanning signal. A pixel portion (liquid crystal panel), which is a display portion of the LCD, is composed of only electrodes and liquid crystal. ing. Therefore, when the number of scanning lines increases, the driving time (duty) assigned to one pixel decreases, and there is a disadvantage that the contrast decreases.

On the other hand, in the active matrix system, a pixel driving element (active element) and a signal storage element (pixel capacitance) are integrated in each pixel arranged in a matrix, and each pixel performs a kind of storage operation to perform liquid crystal. Is driven quasi-statically. That is, the pixel driving element functions as a switch whose on / off state is switched by the scanning signal. Then, a data signal (display signal) is transmitted to the pixel via the pixel driving element in the ON state, and the liquid crystal is driven. Thereafter, when the pixel driving element is turned off, the data signal applied to the pixel is stored in the signal storage element in a state of electric charge, and the liquid crystal is continuously driven until the pixel driving element is turned on next. Therefore, even if the number of scanning lines increases and the driving time allocated to one pixel decreases, the driving of the liquid crystal is not affected and the contrast does not decrease. Therefore, according to the active matrix system, display with much higher image quality can be performed as compared with the simple matrix system.

The active matrix method is roughly classified into a transistor type (three-terminal type) and a diode type (two-terminal type) depending on a difference in a pixel driving element. Although the transistor type is difficult to manufacture as compared with the diode type, it has a feature that it is easy to increase the contrast and resolution and can realize a high-quality LCD comparable to a CRT.

[0006] As a transistor type pixel driving element,
Generally, a TFT is used. In a TFT, a semiconductor thin film formed on an insulating substrate is used as an active layer. Cadmium selenide (CdSe) or tellurium (T
Although studies using e) and the like have been made, amorphous silicon films and polycrystalline silicon films are generally used. A TFT using an amorphous silicon film as an active layer is called an amorphous silicon TFT, and a TF using a polycrystalline silicon film is used.
T is called a polycrystalline silicon TFT. Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than amorphous silicon TFTs. Therefore, the polycrystalline silicon TFT can be used not only as a pixel driving element but also as an element forming a logic circuit. Therefore, if a polycrystalline silicon TFT is used, not only the pixel portion but also the peripheral drive circuit portion disposed therearound can be integrally formed on the same substrate.

FIG. 7 shows a block configuration of a general active matrix type LCD. In the pixel section 50, scanning lines (gate lines) G1... Gn, Gn + 1... Gm and data lines (drain lines) D1... Dn, Dn + 1. Each gate line and each drain line are orthogonal to each other, and a pixel is provided at the orthogonal portion. Each gate wiring is connected to a gate driver 51 so that a gate signal (scan signal) is applied.
Each drain wiring is connected to a drain driver (data driver) 52 so that a data signal (video signal) is applied. These drivers 51, 5
2 constitutes a peripheral drive circuit unit 53. An LCD in which at least one of the drivers 51 and 52 is formed on the same substrate as the pixel unit 50 is called a driver-integrated (built-in driver) LCD.

FIG. 8 shows a gate wiring Gn and a drain wiring D
5 shows an equivalent circuit of a pixel 60 provided in a portion orthogonal to n. The gate of the TFT 61 is connected to the gate wiring Gn, and the drain of the TFT 61 is connected to the drain wiring Dn. The source of the TFT 61 is connected to a display electrode (pixel electrode) of the liquid crystal cell LC and an auxiliary capacitance (storage capacitance or additional capacitance) CS. The liquid crystal cell LC and the auxiliary capacitance CS constitute the signal storage element. The voltage Vcom is applied to the common electrode (the electrode on the opposite side of the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitance CS, a constant voltage VR is applied to an electrode (hereinafter, referred to as a counter electrode) opposite to an electrode (hereinafter, referred to as a storage electrode) connected to a source of the TFT. The common electrode of the liquid crystal cell LC is an electrode common to all the pixels 60 literally. And the liquid crystal cell L
An electrostatic capacitance is formed between the C display electrode and the common electrode. Incidentally, the counter electrode of the auxiliary capacitance CS may be connected to the adjacent gate wiring Gn + 1 in some cases.

In the pixel 60 thus configured,
When a positive voltage is applied to the gate of the TFT 61 by setting the gate line Gn to a positive voltage, the TFT 61 is turned on. Then
The data signal applied to the drain wiring Dn charges the capacitance of the liquid crystal cell LC and the auxiliary capacitance CS. Conversely, when the gate line Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT 61, the TFT 61 is turned off, and the voltage applied to the drain line Dn at that time changes the capacitance and the auxiliary capacitance of the liquid crystal cell LC. And CS. In this manner, by supplying a data signal to be written to the pixel 60 to the drain wiring and controlling the voltage of the gate wiring, the pixel 60 can hold an arbitrary data signal. The transmittance of the liquid crystal cell LC changes according to the data signal held by the pixel 60, and an image is displayed.

Here, important characteristics of the pixel 60 include a writing characteristic and a holding characteristic. What is required for the writing characteristics is that a desired video signal voltage is sufficiently written to the signal storage elements (the liquid crystal cell LC and the auxiliary capacitance CS) within a unit time determined from the specifications of the pixel unit 50. Is that it can be done. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitance CS is provided to increase the capacitance of the signal storage element to improve the writing characteristics and the holding characteristics. That is, the liquid crystal cell L
Due to its structure, C has a limit in increasing the capacitance. Therefore, the insufficient capacitance of the liquid crystal cell LC is compensated for by the auxiliary capacitance CS.

FIG. 9 shows a planar type polycrystalline silicon TF.
A conventional L having a transmission type configuration using T as the TFT 61
1 shows a schematic cross section of a pixel 60 in a CD. A liquid crystal layer 3 filled with liquid crystal is provided between the opposing transparent insulating substrates 1 and 2.
Are formed. The display electrode 4 of the liquid crystal cell LC is provided on the transparent insulating substrate 1, and the liquid crystal cell L is provided on the transparent insulating substrate 2.
A common electrode 5 of C is provided, and the electrodes 4 and 5 are opposed to each other with the liquid crystal layer 3 interposed therebetween.

On the surface of the transparent insulating substrate 1 on the liquid crystal layer 3 side, a polycrystalline silicon film 6 serving as an active layer of the TFT 61 is formed. A gate insulating film 7 is formed on polycrystalline silicon film 6. On the gate insulating film 7, a gate electrode 8 constituting the gate wiring Gn is formed. A drain region 9 and a source region 10 are formed in the polycrystalline silicon film 6 to form a TFT 61. In addition, TFT
Reference numeral 61 denotes an LDD (Lightly Doped Drain) structure, and the drain region 9 and the source region 10 are composed of low concentration regions 9a, 10a and high concentration regions 9b, 10b, respectively.

In a portion of the transparent insulating substrate 1 adjacent to the TFT 61, an auxiliary capacitance CS is formed in the same step as the TFT 61 is formed. The storage electrode 11 of the storage capacitor CS is formed in the polycrystalline silicon film 6 and is connected to the source region 10 of the TFT 61. A dielectric film 12 is formed on the storage electrode 11, and a counter electrode 22 of the auxiliary capacitance CS is formed on the dielectric film 12. The dielectric film 1
Reference numeral 2 is an extension of the gate insulating film 7 and is formed in the same configuration and in the same process as the gate insulating film 7. In addition, the counter electrode 2
2 has the same configuration as the gate electrode 8 and is formed in the same step. An insulating film 13 is formed on the side walls of the counter electrode 22 and the gate electrode 8, and an insulating film 14 is formed on the counter electrode 22 and the gate electrode 8.

An interlayer insulating film 15 is formed on the entire surface of the TFT 61 and the storage capacitor CS. The high-concentration region 9b forming the drain region 9 and the high-concentration region 10b forming the source region 10 are respectively connected to the drain line Dn via the contact holes 16 and 17 formed in the interlayer insulating film 15. It is connected to the electrode 18 and the source electrode 19. An insulating film 20 is formed on the entire surface of the device including the drain electrode 18 and the source electrode 19. The source electrode 19 is connected to the display electrode 4 via a contact hole 21 formed in the insulating film 20.
The drain electrode 18 and the source electrode 19 are generally made of an aluminum alloy, and the display electrode 4 is generally made of ITO (Indium Tin Oxide). The electrodes 4, 18, and 19 are generally formed by a sputtering method.

As described above, the source region 10 and the display electrode 4
Are connected via the source electrode 19 in order to make ohmic contact between the source region 10 and the display electrode 4. That is, when the source electrode 19 is omitted, the source region 10 made of the polycrystalline silicon film 6 is directly connected to the display electrode 4 made of ITO. As a result, an energy gap due to a band gap difference occurs due to a heterojunction between the source region 10 and the display electrode 4, and a favorable ohmic contact cannot be obtained. If the source region 10 and the display electrode 4 are not in ohmic contact, the data signal applied to the drain wiring Dn
0 is not accurately written, and the image quality of the LCD is degraded.

[0017]

When an aluminum alloy is used for the source electrode 19, the source region 10 and the display electrode 4 are not used because the resistance of aluminum oxide is extremely high.
It is important that the surface of the source electrode 19 is not oxidized in order to obtain good ohmic contact. In recent years, by increasing the aperture ratio of the pixel unit 50, L
There is a demand for further improving the image quality (brightness) of CDs. To do so, the diameter of the contact hole 21 must be reduced, and the contact area between the source electrode 19 and the display electrode 4 must be reduced. Therefore, it is increasingly important to reduce the contact resistance between the source electrode 19 and the display electrode 4 and to obtain good ohmic contact between the source region 10 and the display electrode 4.

However, since the aluminum alloy is easily oxidized even in the air, the aluminum oxide film is formed on the surface of the source electrode 19 only by exposing the LCD to the air after the source electrode 19 is formed .

Further, when ITO is used as the display electrode 4, in order to form a low-resistance and high-quality display electrode 4, it is necessary to form an ITO film by a sputtering method in a mixed gas atmosphere of oxygen and argon. . Therefore, even if the aluminum oxide film is removed from the surface of the source electrode 19 before the formation of the display electrode 4, the surface of the source electrode 19 is oxidized by the mixed gas atmosphere of oxygen and argon when the display electrode 4 is formed. An aluminum oxide film is formed again on source electrode 19.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of making ohmic contact between a semiconductor layer and an ITO film. There is .

[0021]

[Means for Solving the Problems]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a layer made of aluminum alone, an aluminum alloy or doped polysilicon connected to a semiconductor layer, and forming an oxide film formed on the surface of this layer. Removing by dry etching , forming a conductive film that is conductive even if oxidized or not conductive on the layer from which the oxide film has been removed, and forming an ITO film on the conductive film The point is that the process is provided.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a layer made of aluminum alone, an aluminum alloy or doped polysilicon connected to a semiconductor layer, and forming an oxide film formed on the surface of this layer. A step of removing by dry etching, a step of forming a conductive film or a non-oxidizing conductive film on the layer from which the oxide film has been removed, in addition to having a low reflectance and exhibiting conductivity even when oxidized. IT on film
The gist of the present invention is to include a step of forming an O film.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a layer made of aluminum alone, an aluminum alloy or doped polysilicon connected to a semiconductor layer, and forming an oxide film formed on the surface of this layer. Removing by dry etching, forming a conductive film made of a high-melting metal alone or a high-melting metal compound on the layer from which the oxide film has been removed, and forming an ITO film on the conductive film. The gist is to have

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a layer made of aluminum alone, an aluminum alloy or doped polysilicon connected to a semiconductor layer, and forming an oxide film formed on the surface of this layer. Removing by dry etching, forming a conductive film made of titanium alone on the layer from which the oxide film has been removed,
The gist of the present invention is to include a step of forming an O film.

[0033]

[0034]

According to the invention as set forth in any one of claims 1 to 4 , by providing the conductive film, a semiconductor layer and an IT
Ohmic contact with the O film can be obtained. Contract
According to the invention described in claim 2 or 4 , since the reflectance of the conductive film is low, it is easy to pattern the conductive film.

According to the third aspect of the present invention, since the resistance value of the high melting point metal alone or the high melting point metal compound is low and does not change even if oxidized, the ohmic contact between the semiconductor layer and the ITO film is improved. Can be taken.

[0036]

[0037]

According to the invention as set forth in claim 8 or claim 9, by providing the conductive film, the semiconductor layer and the
According to the invention of any one of claims 9 to 11, which can make an ohmic contact with the O film, the reflectance of the conductive film is low, so that the conductive film can be easily patterned. Become.

According to the tenth aspect of the present invention, since the resistivity of the conductive film is low, the ohmic contact between the semiconductor layer and the ITO film can be made favorable.
According to the first aspect of the present invention, even if the resistivity of the ultrathin film is relatively high, the resistance value is low because the ultrathin film is an ultrathin film, and good ohmic contact between the semiconductor layer and the ITO film can be obtained. According to the twelfth aspect of the present invention, since the resistance value of the high melting point metal alone or the high melting point metal compound is low and does not change even if oxidized, good ohmic contact between the semiconductor layer and the ITO film can be obtained. According to the invention of claim 13, since the resistance value of the thin film of titanium alone is low and does not change even if it is oxidized, the ohmic contact between the semiconductor layer and the ITO film can be made well. . Further, since the reflectance of the thin film of titanium alone is low, it is easy to pattern the conductive film.

According to the invention as set forth in any one of claims 14 to 17, since the layer consisting of aluminum alone or an aluminum alloy and the film are continuously formed, the surface of the layer may be oxidized. In addition, an ohmic contact between the ITO film and the layer can be made well. Claim 14
The inventions described in (1) to (17) have the same functions as the inventions described in claims 8 to 11, respectively.

According to the invention described in claim 18 or claim 19, by using a semiconductor device having good ohmic contact as a pixel driving element, it is possible to accurately transmit a signal to a pixel. Thus, a display device having excellent image quality can be obtained.

Japanese Patent Application Laid-Open No. Hei 5-27248 discloses a semiconductor layer (corresponding to the source region 10 in this embodiment) of a thin film transistor (corresponding to the TFT 61 in this embodiment) and a pixel electrode (display in this embodiment). There is disclosed a liquid crystal display device in which an extremely thin metal film is interposed at a connection portion with the electrode 4 (corresponding to the electrode 4). The ultra-thin metal film includes titanium,
It is disclosed that a metal having a high melting point, such as tungsten, molybdenum, and chromium, which is hard to be oxidized and is stable, is used.

However, the publication does not disclose any configuration corresponding to the source electrode 19 made of an aluminum alloy in this embodiment. Instead, the publication discloses a configuration in which the display electrode 4 is formed up to the inside of the contact hole 17 in the present embodiment. But,
Since the step coverage of the ITO thin film is low, it is difficult to completely form the display electrode 4 up to the inside of the contact hole 17, and good contact between the source region 10 and the display electrode 4 cannot be obtained. In particular, when the diameter of the contact hole 17 is reduced in order to increase the aperture ratio of the pixel unit 50, the possibility that the display electrode 4 is disconnected inside the contact hole 17 increases.

Further, in the same publication, since an ultrathin metal film is formed up to the interlayer insulating film 15 in this embodiment,
The thickness of the ultra-thin metal film must be made as small as possible so as not to cause insulation failure. However, if the thickness of the ultrathin metal film is small, the contact resistance between the semiconductor layer and the pixel electrode cannot be sufficiently reduced.

Therefore, according to the invention disclosed in this publication, the operation and effect of the present invention cannot be obtained at all, and
Nor is it predictable. By the way, Japanese Patent Application Laid-Open No. 5-243
No. 579 discloses a semiconductor device having at least a layer made of a titanium compound between an ITO thin film and a silicon region.

However, in Example 1 of the publication, "Ti compound 107" and "Ti2
07 and "Ti layer 207" are described in a mixed manner, and "Ti 207" and "Ti layer 20" are described.
It is unclear whether "7" is a description of "Ti compound 107" in which "compound" is omitted or whether it includes titanium alone.

In the third embodiment of the publication, it is described that "Al111" corresponding to the source electrode 19 and "TiN or TiON107" corresponding to the titanium thin film 23 are continuously sputtered in the present embodiment. I have. But,
There is no description as to whether or not “TiN or TiON107” contains titanium alone. Furthermore, there is no description about the function provided by providing “TiN or TiON 107”, and it is difficult even for those skilled in the art to come up with the function and effect provided by providing the titanium thin film 23 in this embodiment.

Since the resistance value of a titanium compound such as titanium nitride or titanium oxynitride is much higher than that of titanium alone, it is not possible to obtain a good ohmic contact as in the case of using titanium alone. Further, the titanium compound has a disadvantage that hillocks are easily generated.

The gazette does not even suggest whether the “titanium compound” described in the claims refers to a compound alone or to a substance containing titanium alone.

Therefore, in the invention disclosed in this publication, the operation and effect of the present invention cannot be obtained at all,
Nor is it predictable.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. In this embodiment, FIGS.
The same components as those in the conventional example shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows a planar type polycrystalline silicon TF.
1 shows a schematic cross section of a pixel 60 in an LCD of this embodiment having a transmission type configuration using T as a TFT 61. This embodiment is different from the conventional example shown in FIG. 9 in that a thin film of titanium alone (hereinafter abbreviated as titanium thin film) 23 (thickness: 1000 °) is formed on the drain electrode 18 and the source electrode 19. It is just a point. That is, in this embodiment,
A titanium thin film 23 is formed between the source electrode 19 and the display electrode 4.

Next, the manufacturing method of the present embodiment will be described sequentially. Step 1 (see FIG. 2A): A non-doped polycrystalline silicon film 6 (thickness: 500 °) is formed on a transparent insulating substrate 1 (quartz glass, high heat-resistant glass).

There are the following methods for forming the polycrystalline silicon film 6. A method for directly forming the polycrystalline silicon film 6; a CVD method or a PVD method is used. The CVD method includes a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, a photo-excitation CVD method, and the like. The PVD method includes a vapor deposition method and EB (Electron Bea).
m) Evaporation, MBE (Molecular Beam Epitaxy), sputtering, etc.

Among them, a reduced pressure CV utilizing thermal decomposition of monosilane (SiH 4 ) or disilane (Si 2 H 6 ) is used.
D method is generally used, and the highest quality polycrystalline silicon film 6 is used.
Can be formed. In the low pressure CVD method, the film becomes amorphous at a processing temperature of 550 ° C. or lower, and becomes polycrystalline at a processing temperature of 620 ° C. or higher.

Also, a plasma CVD method utilizing thermal decomposition of monosilane or disilane in plasma is used. The processing temperature of the plasma CVD method is about 300 ° C. When hydrogen is added, the reaction is accelerated and an amorphous silicon film is formed. When an inert gas (helium, neon, argon, krypton, xenon, radon) is added, plasma is excited, and a polycrystalline silicon film is formed even at the same processing temperature.

A method of forming a polycrystalline silicon film 6 by forming an amorphous silicon film and then performing polycrystallization; a solid phase growth method or a melt recrystallization method is used. The solid phase growth method is a method in which a polycrystalline silicon film is obtained by subjecting an amorphous silicon film to polycrystallization in a solid state by performing a long-time heat treatment at about 600 ° C. for about 20 hours.

In the melt recrystallization method, only the surface of the amorphous silicon film is melted and the substrate temperature is raised to 60 while recrystallization is performed.
0 ° C or lower, such as laser annealing or RTA.
(Rapid Thermal Annealing) method. The laser annealing method is a method in which a surface of an amorphous silicon film is irradiated with a laser to be heated and melted. The RTA method is a method in which a surface of an amorphous silicon film is irradiated with lamp light to be heated and melted.

As described above, by using the solid phase growth method or the melt recrystallization method so that the substrate temperature does not exceed 600 ° C., a high heat-resistant glass can be used as the transparent insulating substrate. Quartz glass becomes extremely expensive as the size increases, and the size of the glass is limited at present, so that the size of the substrate is restricted. Therefore, cost-effective LCD
Has a panel size of 2 inches or less and can be used sufficiently for a viewfinder of a video camera or a liquid crystal projector, but cannot be used for direct viewing because the panel size is too small. On the other hand, ordinary glass (high heat-resistant glass) is about 1/10 the price of quartz glass and has no size restrictions. At present, high heat resistant glass (for example, “7059” manufactured by Corning Inc., USA) having a heat resistant temperature of about 600 ° C. is commercially available for LCDs. Therefore, polycrystalline silicon T is used so that ordinary glass (high heat resistant glass) can be used for the transparent insulating substrate.
It is required to form FT using a low-temperature process of about 600 ° C. or less (called a low-temperature process). still,
When a polycrystalline silicon TFT is formed in a process at a high temperature of about 1000 ° C., it is called a high temperature process as opposed to a low temperature process.

Next, a gate insulating film 7 and a dielectric film 12 (thickness: 1000 °) are simultaneously formed on the polycrystalline silicon film 6. There are the following methods for forming the gate insulating film 7 and the dielectric film 12.

[1] A method of forming a silicon oxide film using an oxidation method; a high-temperature oxidation method (a dry oxidation method using dry oxygen, a wet oxidation method using wet oxygen, an oxidation method in a steam atmosphere), and a low-temperature oxidation method. An oxidation method (an oxidation method in a high-pressure steam atmosphere, an oxidation method in an oxygen plasma), an anodic oxidation method, or the like is used.

[2] A method of forming a silicon oxide film, a silicon nitride film, and a silicon oxynitride film (SiO x N y ) by using a deposition method; a CVD method or a PVD method is used. There is also a method of combining each film to form a multilayer structure.

For the formation of the silicon oxide film by the CVD method, thermal decomposition of monosilane or disilane, thermal decomposition of organic oxysilane (such as TEOS), hydrolysis of silicon halide, and the like are used. For forming a silicon nitride film by the CVD method, ammonia and dichlorosilane (SiH 2 C
l 2 ), thermal decomposition of ammonia and monosilane, nitrogen and monosilane, and the like. The silicon oxynitride film has characteristics of both an oxide film and a nitride film, and can be formed by introducing a small amount of nitrogen oxide (N 2 O) into a system for forming a silicon nitride film by a CVD method.

The method for forming the gate insulating film 7 and the dielectric film 12 includes a high-temperature process and a low-temperature process.
In the high-temperature process, the above-described high-temperature oxidation method is generally used. On the other hand, in the low-temperature process, the oxidation method or the deposition method in oxygen plasma described above is generally used, and the processing temperature is suppressed to about 600 ° C. or less.

Step 2 (not shown): A resist pattern is formed only on the gate insulating film 7 excluding the dielectric film 12. Next, the storage electrode 11 is formed on the polycrystalline silicon film 6 using the resist pattern as a mask. The formation method of the storage electrode 11 also includes a high-temperature process and a low-temperature process. In the high-temperature process, high-temperature heat treatment is performed after ion implantation of impurities to activate the impurities. In the low temperature process, phosphine gas (PH 3 ) or diborane gas (B
By irradiating an ion shower with a mixed gas of 2 H 6 ) and hydrogen gas, impurity implantation and activation are simultaneously performed without providing a special heat treatment step. In the low-temperature process, there is a method of activating the impurities by performing a heat treatment for several hours to several tens of hours at a low temperature of about 600 ° C. or less after implantation of the impurity ions. At this time, since the resist pattern is formed on the gate insulating film 7,
No impurity is implanted into the lower polycrystalline silicon film 6 (the source region 10 and the drain region 9 and the channel region between the respective regions 9 and 10). Will be kept as it is.

Subsequently, the resist pattern is removed. Step 3 (see FIG. 2B): A gate electrode 8 and a counter electrode 22 (thickness: 3000 °) are simultaneously formed on the gate insulating film 7 and the dielectric film 12, respectively, and patterned into a desired shape. The materials of the gate electrode 8 and the counter electrode 22 include polycrystalline silicon (doped polysilicon) doped with impurities, metal silicide, polycide, and the like.
A simple substance of a high melting point metal or another metal is used, and a CVD method or a PVD method is used for its formation.

Next, an insulating film 14 is formed on the gate electrode 8 and the counter electrode 22. As the insulating film 14, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is used, and a CVD method or a PVD method is used for the formation thereof.

Subsequently, the insulating film 14 is formed by a self-alignment technique.
And polycrystalline silicon film 6 using gate electrode 8 as a mask
Then, low concentration regions 9a and 10a are formed. Low concentration area 9
The method of forming the a and 10a is the same as that of the storage electrode 11 except that the concentration of the impurity to be implanted is low.

The reason why the insulating film 14 is formed is to prevent impurities from being implanted into the gate electrode 8 and the counter electrode 22 when the low concentration regions 9a and 10a are formed. In particular, when doped polysilicon is used for the gate electrode 8 and the counter electrode 22, the low-concentration region 9a,
If impurities are implanted during the formation of 10a, the resistance value may increase, so the insulating film 14 is indispensable.

Step 4 (see FIG. 2C); Gate electrode 8
Then, the insulating film 13 is formed on the side wall of the counter electrode 22. The method of forming the insulating film 13 is the same as that of the insulating film 14. Next, a resist pattern RP as a sidewall spacer is formed on each of the insulating films 13 and 14.

Subsequently, high-concentration regions 9b and 10b are formed in the polycrystalline silicon film 6 using the resist pattern RP as a mask by a self-alignment technique. The method of forming the high concentration regions 9b and 10b is the same as that of the storage electrode 11.

After that, the resist pattern RP is removed. Step 5 (see FIG. 3); an interlayer insulating film 15 is formed on the entire surface of the device.
To form As the interlayer insulating film 15, a silicon oxide film,
A silicon nitride film, a silicon oxynitride film, a silicate glass, or the like is used, and a CVD method or a PVD method is used for the formation. There is also a method of combining each film to form a multilayer structure. For example, a non-doped silicon oxide film (hereinafter, referred to as an NSG film) is used to form a BPSG (Boron-doped Phosphor).
ospho-Silicate Glass) Structure sandwiching a film (NSG / BP)
SG / NSG) to form the interlayer insulating film 15 and perform reflow after forming the BPSG film.
There is a method for improving the step coverage of the above.

Next, contact holes 16 and 17 are formed in interlayer insulating film 15 by anisotropic etching. Subsequently, the device is exposed to hydrogen plasma, so that the polycrystalline silicon film 6 is hydrogenated. Hydrogenation is a method in which hydrogen atoms are bonded to crystal defect portions of polycrystalline silicon to reduce defects, stabilize the crystal structure, and increase field-effect mobility. This allows
The element characteristics of the TFT 61 can be improved.

Step 6 (see FIG. 4):
An aluminum alloy film (Al-1% Si-0.5% Cu) is deposited on the entire surface of the device including the insides of the contact holes 16 and 17, and a titanium thin film 23 is continuously deposited on the aluminum alloy film. Next, the drain electrode 18 and the source electrode 19 are formed by patterning the aluminum alloy film and the titanium thin film 23 into desired shapes.

At this time, the aluminum alloy film and the titanium thin film 23
Are continuously formed in the same metal sputtering apparatus,
The surface of the aluminum alloy film is not oxidized. Therefore, formation of an aluminum oxide film on the surfaces of the drain electrode 18 and the source electrode 19 can be prevented.
Further, the resistance value of titanium alone is extremely low, and the thickness of the titanium thin film 23 is extremely small. Therefore, the titanium thin film 23
, The contact resistance between the source electrode 19 and the display electrode 4 does not increase.

The reason why the aluminum alloy film contains 1% of supersaturated silicon is to prevent silicon from being taken into the drain electrode 18 and the source electrode 19 from the polycrystalline silicon film 6. The reason why copper is added to the aluminum alloy film is to improve the electromigration resistance and the stress migration resistance of the drain electrode 18 and the source electrode 19.

Further, since the reflectance of the titanium thin film 23 is lower than that of the aluminum alloy film, the fine shape can be accurately patterned when the titanium thin film 23 is provided as compared with the case where only the aluminum alloy film is patterned. Can be.

Step 7 (see FIG. 5): An insulating film 20 (film thickness: 10000 Å) is formed on the entire surface of the device. As the insulating film 20, a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like is used.
Method D is used. Step 8 (see FIG. 6): A contact hole 21 is formed in the insulating film 20 by anisotropic etching.

Next, an ITO film 24 is deposited on the entire surface of the device including the inside of the contact hole 21 by sputtering. At this time, in order to form a low-resistance and high-quality ITO film 24, it is necessary to perform a sputtering method in a mixed gas atmosphere of oxygen and argon. Therefore, the titanium thin film 2 is formed by the mixed gas atmosphere of oxygen and argon when the ITO film 24 is formed.
3 is oxidized to form a titanium oxide film. However, since the resistance value of titanium oxide is as low as that of titanium alone, even if the surface of the titanium thin film 23 is oxidized to form a titanium oxide film, the contact resistance between the source electrode 19 and the display electrode 4 is reduced. It does not increase.

Step 9 (see FIG. 1): The ITO film 24 is patterned into a desired shape and the display electrode 4 (thickness: 2000 °)
To form Next, the TFT 61 is manufactured by the above manufacturing process.
A transparent insulating substrate 1 having a storage capacitor CS formed thereon and a transparent insulating substrate 2 having a common electrode 5 formed on the surface thereof are opposed to each other, and a liquid crystal is sealed therebetween to form a liquid crystal layer 3, thereby forming an LCD. Is completed.

When high heat-resistant glass is used for the transparent insulating substrate 1, a low-temperature process must be used not only during the formation of the polycrystalline silicon film 4 but also throughout the entire process up to the formation of the display electrode 4. No.

As described above, in this embodiment, the titanium thin film 23 whose resistance value hardly increases even when oxidized is formed on the source electrode 19. Accordingly, it is possible to prevent an increase in contact resistance between the source electrode 19 and the display electrode 4, and it is possible to obtain good ohmic contact between the source region 10 and the display electrode 4.

As a result, the data signal applied to the drain wiring Dn can be accurately written to the pixel 60, and the image quality of the LCD can be improved. Further, since the contact resistance between the source electrode 19 and the display electrode 4 is reduced, the diameter of the contact hole 21 can be reduced. This increases the aperture ratio of the pixel unit 50, so that the image quality (brightness) of the LCD can be further improved.

Incidentally, the thickness of the titanium thin film 23 may be arbitrarily set in accordance with the amount of over-etching at the time of forming the contact hole 21 (in short, it is sufficient that the titanium thin film 23 is not completely removed). How much the over-etching amount is set depends on the uniformity of the insulating film 20, the uniformity of the etching rate, and the like.
If the controllability of the process is good, the thickness of the titanium thin film 23 may be 100 mm or more.

Since the reflectance of the titanium thin film 23 is low, it functions as an antireflection film when patterning the drain electrode 18 and the source electrode 19, and the fine electrode 1
The shapes 8 and 19 can be accurately patterned. As a result, the aperture ratio of the pixel unit 50 increases, so that LC
The image quality (brightness) of D can be further improved.

The above embodiment may be modified as described below, and the same operation and effect can be obtained in such a case. (1) In step 6, the aluminum alloy film and the titanium thin film 23
Are not formed continuously but are formed in separate steps. In this case, the aluminum oxide film formed on the surface of the aluminum alloy film may be removed by dry-etching the surface of the aluminum alloy film before forming the titanium thin film 23. This complicates the process, but still provides the same operation and effect as the above embodiment.

(2) The titanium thin film 23 is replaced with a conductive film which exhibits conductivity even if oxidized or a non-oxidized conductive film.
Further, a multilayer structure is formed by combining a plurality of conductive films. Examples of the conductive film that exhibits conductivity even when oxidized include a thin film of a titanium compound (titanium nitride, titanium oxynitride, titanium tungsten, titanium silicide, etc.) and a high melting point metal simple substance (molybdenum, nickel, tantalum, manganese, vanadium, etc.). There are thin films and thin films of refractory metal compounds. In addition, a thin film of gold or the like is used as the conductive film that does not oxidize. If the reflectance of the conductive film is low, the conductive film functions as an antireflection film at the time of patterning the drain electrode 18 and the source electrode 19, which is more effective.

(3) The TFT 61 has an SD (Single Drain) structure or a double gate structure instead of the LDD structure. (4) The threshold voltage (Vth) of the TFT 61 is controlled by doping the channel region between the drain region 9 and the source region 10 with an impurity. In the TFT 61 using the polycrystalline silicon film 6 formed by the solid phase growth method as an active layer, the threshold voltage of the n-channel transistor tends to shift in the depletion direction, and the threshold voltage of the p-channel transistor tends to shift in the enhancement direction. . In particular,
When the hydrogenation treatment is performed, the tendency becomes more remarkable. In order to suppress the shift of the threshold voltage, the channel region may be doped with an impurity.

(5) The TFT 61 is replaced with a TFT having another structure such as an inverted planar type, a staggered type, and an inverted staggered type, instead of the planar type. (6) The TFT 61 is replaced with an amorphous silicon TFT instead of a polycrystalline silicon TFT.

(7) The source electrode 19 is formed of another conductive material other than the aluminum alloy. Examples of such a conductive material include a thin film of a high melting point metal alone, a high melting point metal compound, a metal silicide, and doped polysilicon.

(8) The TFT 61 is replaced with a pixel driving element (for example, RD (Ring Diode) or the like) having a structure in which a display electrode made of ITO and an aluminum wiring are connected .

[0092]

[0093]

[0094]

[0095]

As described above in detail, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of making ohmic contact between a semiconductor layer and an ITO film .

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a pixel according to an embodiment.

FIG. 2 is a schematic cross-sectional view for explaining a manufacturing method according to one embodiment.

FIG. 3 is a schematic cross-sectional view for explaining a manufacturing method according to one embodiment.

FIG. 4 is a schematic cross-sectional view for explaining a manufacturing method according to one embodiment.

FIG. 5 is a schematic cross-sectional view for explaining a manufacturing method according to one embodiment.

FIG. 6 is a schematic cross-sectional view for explaining a manufacturing method according to one embodiment.

FIG. 7 is a block diagram of an active matrix type LCD.

FIG. 8 is an equivalent circuit diagram of a pixel.

FIG. 9 is a schematic sectional view of a conventional pixel.

[Explanation of symbols]

6 Polycrystalline Silicon Film as Semiconductor Layer 19 Source Electrode as Layer Made of Simple Aluminum or Aluminum Alloy 21 Display Electrode as ITO Film 23 Titanium Thin Film 24 ITO Film

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-253342 (JP, A) JP-A-5-323377 (JP, A) JP-A-6-37109 (JP, A) JP-A-5-37109 235360 (JP, A) JP-A-4-336530 (JP, A) JP-A-4-326723 (JP, A)

Claims (4)

    (57) [Claims]
  1. A step of forming a layer made of aluminum alone, an aluminum alloy, or doped polysilicon connected to a semiconductor layer; a step of removing an oxide film formed on a surface of the layer by dry etching; Manufacturing of a semiconductor device comprising: a step of forming a conductive film showing conductivity even if oxidized or a film not oxidizing on the layer from which the film has been removed; and a step of forming an ITO film on the conductive film. Method.
  2. A step of forming a layer made of aluminum alone, an aluminum alloy or doped polysilicon connected to the semiconductor layer, a step of removing an oxide film formed on a surface of the layer by dry etching, A step of forming a conductive film that exhibits conductivity even when oxidized in addition to having a low reflectance on the layer from which the film has been removed, and a step of forming an ITO film on the conductive film A method for manufacturing a semiconductor device comprising:
  3. 3. A step of forming a layer made of simple substance of aluminum, an aluminum alloy or doped polysilicon connected to the semiconductor layer, a step of removing an oxide film formed on a surface of this layer by dry etching, on the layer of film is removed, or a refractory metal element or a refractory metal compound
    A method for manufacturing a semiconductor device, comprising: a step of forming a conductive film made of the same; and a step of forming an ITO film on the conductive film.
  4. 4. A step of forming a layer made of simple aluminum, aluminum alloy or doped polysilicon connected to the semiconductor layer, a step of removing an oxide film formed on the surface of this layer by dry etching, A method for manufacturing a semiconductor device, comprising: a step of forming a conductive film made of titanium alone on the layer from which the film has been removed; and a step of forming an ITO film on the conductive film.
JP23552194A 1994-09-29 1994-09-29 Method for manufacturing semiconductor device Expired - Fee Related JP3239024B2 (en)

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KR100905472B1 (en) * 2002-12-17 2009-07-02 삼성전자주식회사 Thin film transistor array panel and liquid crystal display including the panel
JP2005064142A (en) * 2003-08-08 2005-03-10 Seiko Epson Corp Thin film semiconductor device and manufacturing method thereof
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