JP3537938B2 - Method for manufacturing active matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having an active matrix circuit (active matrix display device).

[0002]

2. Description of the Related Art In recent years, active matrices for driving liquid crystal displays have been actively studied and put into practical use. As an active element, an element using a thin film transistor (TFT) for each pixel has been proposed. In such an active matrix circuit, a capacitor having a liquid crystal interposed between a pixel electrode and a counter electrode is formed, and electric charges entering and exiting the capacitor are controlled by a TFT.

In order to manufacture TFTs with good yield, it was necessary to reduce the number of manufacturing steps. In particular, as wiring design rules become finer, it has been required to reduce the number of photolithography steps, particularly the number of mask alignments. In addition, increasing the occupation ratio (opening ratio) of the pixel electrode was also an important issue.

[0004]

In the conventional active matrix circuit, the most required precision in mask alignment is a patterning process of a pixel electrode. This is because, if the mask alignment is not appropriate, the pixel electrode overlaps with the gate line and the data line, and generates a parasitic capacitance. Parasitic capacitance had a significant effect on image quality. In particular, when the distance between the pixel electrode and the gate line or the data line is narrowed in order to increase the aperture ratio, the probability of occurrence of the above-described defect increases. Conversely, if the distance between the pixel electrode and the gate line or data line is sufficiently large, the aperture ratio cannot be increased.

FIG. 2A schematically shows a cross section of a conventional active matrix display device. In this figure, the TFT
Is a planar type. Such an apparatus is manufactured as follows. That is, a thin-film semiconductor layer 32, a gate insulating film (not shown), and gate lines 33 to
35 is formed. Among them, the gate line 35 becomes a gate electrode of the TFT. In the thin film semiconductor layer, regions (source and drain) having N-type or P-type conductivity are provided. Further, a first interlayer insulator 36 is formed so as to cover them, a contact hole is provided in the first interlayer insulator 36, and a data line 37 is formed.
To form

Further, a second interlayer insulator 38 is formed to cover them, a contact hole 39 is provided in the second interlayer insulator 38, and a transparent conductive film is formed. As the second interlayer insulator,
In addition to silicon oxide and silicon nitride, an organic resin having a lower dielectric constant is used. Then, the transparent conductive film is etched by a known photolithography method, and the pixel electrode 4 is etched.
Set to 0. (Fig. 2 (A))

FIG. 2B shows a unit pixel of the active matrix display device as viewed from above. As is clear from the figure, the pixel electrode 40 is connected to the gate line 33 and the data line 3.
Since it is necessary to take a sufficient distance from the pixel 7, the ratio of the unit pixel to the area is not so high. FIG. 3 schematically shows a cross section of an active matrix display device using an inverted stagger type TFT. Such an apparatus is manufactured as follows. That is, the gate lines 42 to 4 are formed on the transparent substrate 41.
4. A gate insulating film 45 and a thin film semiconductor layer 46 are formed.
Among them, the gate line 44 becomes a gate electrode of the TFT.

Further, an etching stopper 47 is formed of a material such as silicon nitride on the thin film semiconductor layer, and a film 48 having an N-type or P-type conductivity is formed to cover the etching stopper 47. Then, this is etched up to the etching stopper 47 to be used as a source and a drain. Further, a data line 49 is formed. Further, an interlayer insulator 50 is formed to cover them, a contact hole is provided in the interlayer insulator 50, and a transparent conductive film is formed. Then, the transparent conductive film is etched by a known photolithography method to form a pixel electrode 51. (Fig. 3)

In particular, in the case of an inverted stagger type TFT, when an etching stopper is used, the unevenness of the surface becomes large. This was not preferable for a display device using liquid crystal. This is because, in order to use a liquid crystal in a display device, it is necessary to align liquid crystal molecules in a specific direction.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points. That is, a step of forming an element layer having a gate line, a data line, and a thin film semiconductor layer on a transparent substrate, the surface of which is covered with an interlayer insulator; and a contact hole for providing a pixel electrode in the element layer. Forming a transparent conductive film on the element layer, polishing and flattening the transparent conductive film and the interlayer insulator by a mechanical polishing method or a chemical mechanical polishing method, Etching the transparent conductive film along the gate line and the data line.

In practicing the present invention, it is more preferable to satisfy any of the following conditions. That is, (1) the transparent conductive film directly contacts the thin film semiconductor layer in the contact hole, and a contact portion of the thin film semiconductor layer is thinner than any of the gate line and the data line. (2) The interlayer insulator is thicker than either the gate line or the data line. (3) The gate line is provided with an insulator formed of the same film as the etching stopper formed on the thin film semiconductor layer.

The above (1) and (2) are planar types,
The method is effective for all the TFTs including the inverted stagger type, but (3) is effective only for the inverted stagger type. The reason for (3) will be described in detail in the embodiment.

[0013]

According to the present invention, the transparent conductive film is not etched by the conventional photolithography method. Instead, it is etched by a mechanical polishing method or a chemical mechanical polishing method (also referred to as a CMP method).
At this time, a portion having a gate line or a data line is more preferentially etched because it is more convex than other portions. As a result, only the portion of the transparent conductive film surrounded by the gate line and the data line is left, and becomes a pixel electrode.

The conditions (1) and (2) which are desired to be satisfied in practicing the present invention will be examined. First, the reason for the above condition (1) will be described with reference to FIG. Here, the gate line 104 and the data line 10
3. A thin film semiconductor layer 102, an interlayer insulator 105, and a transparent conductive film 106 are formed. (FIG. 6 (A))

This is polished according to the present invention. During polishing, the data line 1 of the interlayer insulator 105 is removed.
A surface 107 on top 03 emerges, which separates the transparent conductive coating 106 into two parts 108 and 109. However, since the transparent conductive film is not separated by the data line and the gate line, no pixel electrode is formed, and it is necessary to continue polishing. (FIG. 6
(B))

Further, if polishing is continued, the interlayer insulator 10
5, a surface 110 on the gate line 103 appears, whereby the transparent conductive film 108 is formed on the pixel electrode 112.
And 113. That is, in order to separate the pixel electrode according to the present invention, polishing must be continued until the surface of the interlayer insulator on the thinner one of the gate line and the data line (the gate line in FIG. 6) is exposed.

However, at this time, the interlayer insulator 1
Also, the transparent conductive film 109 is separated into 114 and 115 by the surface 111 on the thin film semiconductor layer 102 in FIG. Insulated from (FIG. 6C) In order to avoid such a problem, the height of the surface 111 needs to be lower than the height of the surface 110. This is because the thin film semiconductor layer and the pixel electrode are connected even when the polishing for separating the pixel electrode is stopped. The difference between the heights of the two portions is determined by the smaller thickness of the gate line or the data line and the thickness of the thin film semiconductor layer in the contact portion. That is, the latter is preferably thinner than the former.

For example, as shown in FIG.
A gate line 123 and a data line 124, a thin film semiconductor layer 122, an interlayer insulator 125, and a transparent conductive film 126 are formed on 21. (FIG. 6D) Then, this is polished according to the present invention. As described above, when polishing is continued until the surface 127 of the interlayer insulator on the thinner of the gate line and the data line (the gate line in FIG. 6) is exposed, the transparent conductive film 126 131. However, at this time, since the surface 129 of the portion of the interlayer insulator 125 above the thin film semiconductor layer 122 is not exposed, the pixel electrode 132 is connected to the thin film semiconductor layer. (FIG. 6
(E))

Next, the reason for the above condition (2) will be described with reference to FIG. Here, the gate line 20 is provided on the substrate 201.
2, 203, a data line 204, 205, a first interlayer insulator 206 covering the gate line, a second interlayer insulator 207 covering the data line, and a transparent conductive film 208 are formed. The gate line 203 and the data line 205 intersect. (FIG. 7A)

This is polished according to the present invention. First, the uppermost gate line 203 and data line 2
The interlayer insulator over the intersection of 05 is exposed and polished. However, at this stage, since the transparent conductive film is not separated by the data line 204 and the gate line 202, the pixel electrode is not formed, and it is necessary to continue polishing. (FIG. 7 (B))

Further, if the polishing is continued, the gate line 20
2. Surfaces 210 and 21 of interlayer insulator on data line 204
1 is exposed, whereby the transparent conductive film 208 is separated into the pixel electrodes 213 to 215. However, at this time, the interlayer insulating material at the intersection of the gate line 203 and the data line 205 is completely polished, and the upper surface 212 of the data line is exposed. Although such a state itself is not a defect, it is not preferable. (FIG. 7 (C))

In order to avoid such a problem, when the surfaces 210 and 211 of the interlayer insulator are exposed, the surface of any one of the data lines and the gate lines, which is located above, should not be exposed. . For this purpose, although the data line or the gate line is higher than the surface of the interlayer insulator on the thinner one of the gate line and the data line (the pixel electrode cannot be separated unless this surface is polished). It is necessary to reduce the height of the surface.

Therefore, when the data line is thinner than the gate line, the height is determined by the thickness of the second interlayer insulator and the thickness of the gate line. That is, the second
Need to be thicker than the gate line. Further, when the gate line is thinner than the data line, it is necessary to make the second interlayer insulator thicker than the data line. That is, the second interlayer insulator is thicker than both the gate line and the data line.

For example, as shown in FIG.
Gate lines 222 and 223 and data lines 224 and 2
25, first interlayer insulator 226, second interlayer insulator 22
7. A transparent conductive film 228 is formed. Gate line 223
And the data line 225 intersect. (FIG. 7 (D))

This is polished according to the present invention. As described above, the surface 22 of the interlayer insulator on the thinner of the gate line and the data line (both in FIG. 7).
If the polishing is continued until the layers 9 and 230 are exposed, the transparent conductive film 228 is separated into the pixel electrodes 232 to 234. The polishing may be terminated at this stage. However, at that time, the surface 231 of the data line 225 is not exposed. (FIG. 7E)

[0026]

【Example】

Embodiment 1 FIG. 1 shows a method for etching an active matrix display device according to an embodiment of the present invention, particularly, a transparent conductive film. This embodiment is an active matrix display device using a so-called polycrystalline silicon planar TFT. 1A to 1C schematically show cross sections of the process, and FIG. 1D shows a schematic view from above.

First, the glass substrate 1 is formed by a known technique.
A thin polycrystalline silicon layer 12 having a thickness of 500 °, a gate insulating film, and gate lines 13 to 15 are formed on 1. An N-type region is formed in the thin film silicon layer 12 by a well-known self-aligned doping method using the gate electrode 15 as a mask. The gate line / gate electrode uses polycrystalline silicon.
The thickness of the gate wire is 3000 mm. Then, a first interlayer insulator (silicon oxide) 16 is deposited. The thickness of the first interlayer insulator is 4000 °.

Next, a contact hole reaching the thin film silicon layer 12 is formed in the first interlayer insulator. And
The data line 17 is formed of aluminum. The thickness of the data line is 6000 °. And the thickness 8000Å
A second interlayer insulator (silicon oxide) 18 is deposited, and a contact hole 19 reaching the thin film silicon layer 12 is formed in the first and second interlayer insulators. Furthermore, indium tin oxide (ITO) having a thickness of 1000 mm by a known technique.
A coating 20 is formed. (Fig. 1 (A))

Then, the surface of the device is polished by the CMP method according to the present invention. FIG. 1B shows a state where the polishing is performed to the level indicated by the arrow 21. At this stage, the ITO film 20 is not separated into the pixel electrodes. (FIG. 1B) FIG. 1C shows a state in which polishing is completed and pixel electrodes 22 and 23 are formed. What is clear when comparing this figure with FIG. 2A of the conventional display device is that there are few surface irregularities. That is, according to the present invention, flattening is performed at the same time. (Fig. 1 (C))

FIG. 3 is a drawing showing a unit pixel of a display device in a state where etching (separation) of a pixel electrode is completed, as viewed from above.
The comparison between this figure and FIG. 2B of the conventional display device reveals that the pixel electrode 22, the gate line 13, and the data line 1
7 is sufficiently small. That is,
The aperture ratio is much higher. (Fig. 1 (D))

In this embodiment, the thin film semiconductor layer: 50
0Å, gate line: 3000Å, data line: 6000Å,
Second interlayer insulator: 8000 °. In this embodiment, the gate line and the data line are thicker than the thin silicon layer. Therefore, the above condition (1) is satisfied. The second interlayer insulator is thicker than the data line and the gate line. Therefore, the above condition (2) is satisfied.

Embodiment 2 FIG. 4 shows a method of etching an active matrix display device, particularly, a transparent conductive film according to an embodiment of the present invention. The present embodiment is an active matrix display device using a so-called amorphous silicon inverted stagger type TFT. 4 (A) and 4 (B) show a schematic cross section of the process.

First, the glass substrate 6 is formed by a known technique.
A gate line 62 to 64, a gate insulating film 65, and an intrinsic thin-film amorphous silicon layer 66 having a thickness of 300 ° are formed on 1. The gate wire is made of aluminum and has a thickness of 3000 mm. The gate insulating film is made of silicon nitride, and its thickness is 3000 °.

Then, the thin film semiconductor layer 6 on the portion above the gate electrode 64 is formed by a silicon nitride film having a thickness of 2000 °.
An etching stopper 67 is formed on 6. further,
An N-type crystalline silicon film (thickness: 2000 °) 68 is deposited. Then, this is etched to the etching stopper to separate it into a source and a drain.

Next, the data line 69 is formed of aluminum. The thickness of the data line is 3000 mm. Then, an interlayer insulator (silicon nitride) 70 having a thickness of 4000 ° is deposited, and a contact hole reaching the N-type thin-film silicon layer 68 is formed in the interlayer insulator (silicon nitride) 70. Further, an indium tin oxide (ITO) film 71 having a thickness of 1000
To form (FIG. 4A)

Then, according to the present invention, the surface of the above element is polished by the CMP method. FIG. 4B shows a state where the polishing is completed and the pixel electrodes 72 and 73 are formed. What is clear when comparing this figure with FIG. 3 of the conventional display device is that the unevenness on the surface has been significantly reduced. In the figure, a part of the N-type thin film semiconductor layer 68 and a part of the etching stopper 67 are polished,
There is no effect on the characteristics of the device. (FIG. 4 (B))

In this embodiment, the intrinsic thin film semiconductor layer: 300 °, the gate line: 3000 °, and the data line: 30 °
00 °, interlayer insulating material: 4000 °. In this embodiment, both the gate line and the data line are thicker than the thin film silicon layer 68 at the portion where the pixel electrode contacts. Therefore, the above condition (1) is satisfied. The interlayer insulator is
Thicker than both data and gate lines. Therefore,
The above condition (2) is satisfied.

Embodiment 3 FIG. 5 shows a method of etching an active matrix display device according to an embodiment of the present invention, particularly, a transparent conductive film. The present embodiment is an active matrix display device using a so-called amorphous silicon inverted stagger type TFT, and particularly relates to an example in which the present invention is applied to a method of forming an etching stopper in a self-aligned manner using a gate line as a mask. is there. FIGS. 5A and 5B schematically show the cross section of the process.

First, the glass substrate 8 is formed by a known technique.
A gate line 82 to 84, a gate insulating film 85, and an intrinsic thin-film amorphous silicon layer 86 having a thickness of 500.degree. The gate wire is made of aluminum and has a thickness of 2000 mm. The gate insulating film is made of silicon nitride, and its thickness is 3000 °.

Then, a 2000 nm thick silicon nitride film is formed on the entire surface, and a positive photoresist is applied thereon. Thereafter, when exposure is performed from the back surface of the substrate, the resist on the gate line is not exposed, and only the resist on the other portions is selectively exposed, so that only the resist on the gate line can be selectively left. When the silicon nitride film is etched using the resist formed as described above as a mask, an etching stopper is formed. However,
In this method, unlike the second embodiment, the same thing as the etching stopper is formed not only on the TFT portion but also on all the gate lines. Hereinafter, these are all referred to as etching stoppers 87 to 89.

Further, an N-type crystalline silicon film (thickness 2
000 °) 90 is deposited. Then, this is etched to the etching stopper to separate it into a source and a drain. Next, the data line 91 is formed of aluminum. The thickness of the data line is 3000 mm. And a 5000-mm thick interlayer insulator (silicon oxide)
A contact hole 92 is formed on the N-type thin film silicon layer 90. Furthermore, indium tin oxide (ITO) having a thickness of 1000 mm by a known technique.
A coating 93 is formed. (FIG. 5 (A))

Then, the surface of the device is polished by the CMP method according to the present invention. FIG. 5B shows a state where the polishing is completed and the pixel electrodes 94 and 95 are formed. (FIG. 5B) In this embodiment, the intrinsic thin-film semiconductor layer: 500 °,
Gate line: 2,000 °, data line: 3000 °, interlayer insulator: 5000 °.

In this embodiment, the gate line and the data line are apparently the same thickness. However, since an etching stopper is always formed on the gate line, the gate line and the data line are substantially formed. In this case, the substantial thickness of the gate line is the apparent thickness of the gate line and the etching stopper.

There may be other such situations. For example, when the upper surface of the gate line is anodized, the obtained anodic oxide is always formed on the gate line, so the actual thickness of the gate line is substantially equal to the apparent gate line and anodic oxide. Is the thickness. The same applies to data lines.

Apparently, the thickness 2,000 mm of the thin film semiconductor layer at the contact portion of the pixel electrode is the same as the thickness 2000 mm of the gate line, and does not satisfy the above condition (1). However, as described above, the actual gate line thickness is
The apparent thickness of the kate line plus the thickness of the etching stopper is 4000 °, and therefore both the gate line and the data line are substantially larger than the thickness 2000 ° of the thin film semiconductor layer in the contact portion. (1) is satisfied.

Similarly, apparently, the thickness of the interlayer insulator 92 should be thicker than the data line. However, since the gate line is substantially thicker than the data line, the above condition ( To satisfy 2), the interlayer insulator needs to be thicker than the substantial thickness of the gate line. As described above, the actual thickness of the gate line is 4000 mm, which is the sum of the apparent thickness of the kate line and the thickness of the etching stopper,
Therefore, the thickness of the interlayer insulator needs to be greater than 4000 °.

[0047]

The effects obtained by the present invention are as follows:
Summed up in points. (1) Reduction of the photolithography process for patterning the pixel electrode (2) Improvement of the aperture ratio (3) Flattening of the device surface Among these, (1) contributes to the improvement of the manufacturing yield and the throughput. Further, (2) and (3) have a favorable effect on the display characteristics of the display device. As described above, the present invention has great industrial value.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cross section of a manufacturing process of an active matrix display device according to a first embodiment and a state viewed from above.

FIG. 2 is a diagram showing a cross section of a conventional active matrix display device and a state viewed from above.

FIG. 3 is a diagram showing a cross section of a conventional active matrix display device.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the active matrix display device according to the second embodiment.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of the active matrix display device according to the third embodiment.

FIG. 6 is a diagram for explaining conditions of the present invention.

FIG. 7 is a diagram for explaining conditions of the present invention.

[Explanation of symbols]

11 Substrate 12 Thin-film semiconductor layer 13-15 Gate line 16 First interlayer insulator 17 Data line 18. Second interlayer insulator 19 Contact hole 20 Transparent conductive film 21 Polished level 22, 23 pixel electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 G02F 1/1343 H01L 29/786

Claims (4)

(57) [Claims] 1. A gate lines, data lines on a transparent substrate, wherein
A thin film semiconductor layer connected to a data line , and the gate
First film formed to insulate a data line from the data line
Forming a device layer having a Jo interlayer insulator, the second to form a film-like interlayer insulator, the first film-like interlayer insulator and the second film-like layers in the element layer forming a contact hole for providing a pixel electrode in the inter-layer insulator; forming a transparent conductive film on the second film-shaped interlayer insulator; forming the transparent conductive film and the second The pixel electrode is polished by a mechanical polishing method or a chemical mechanical polishing method until the second film-like interlayer insulator on the gate line and the data line is exposed. Forming an active matrix display device. 2. The method according to claim 1, wherein a gate line, a data line,
A thin film semiconductor layer connected to a data line , and the gate
First film formed to insulate a data line from the data line
Forming a device layer having a Jo interlayer insulator, the second to form a film-like interlayer insulator, the first film-like interlayer insulator and the second film-like layers in the element layer forming a contact hole for providing a pixel electrode in the inter-layer insulator; forming a transparent conductive film on the second film-shaped interlayer insulator; forming the transparent conductive film and the second The pixel electrode is polished by a mechanical polishing method or a chemical mechanical polishing method until the second film-like interlayer insulator on the gate line and the data line is exposed. Forming the transparent conductive film in direct contact with the thin film semiconductor layer in the contact hole, wherein the thickness of the thin film semiconductor layer is thinner than any of the gate line and the data line. Active matrix A method for manufacturing the shows apparatus. 3. The method according to claim 1, wherein the gate line, the data line,
A thin film semiconductor layer connected to a data line , and the gate
First film formed to insulate a data line from the data line
Forming a device layer having a Jo interlayer insulator, the second to form a film-like interlayer insulator, the first film-like interlayer insulator and the second film-like layers in the element layer forming a contact hole for providing a pixel electrode in the inter-layer insulator; forming a transparent conductive film on the second film-shaped interlayer insulator; forming the transparent conductive film and the second The pixel electrode is polished by a mechanical polishing method or a chemical mechanical polishing method until the second film-like interlayer insulator on the gate line and the data line is exposed. Wherein the thickness of the second film-shaped interlayer insulator is larger than both the gate line and the data line. 4. A gate line on a transparent substrate, data lines, wherein
A thin film semiconductor layer connected to a data line , and the gate
First film formed to insulate a data line from the data line
Forming a device layer having a Jo interlayer insulator, the second to form a film-like interlayer insulator, the first film-like interlayer insulator and the second film-like layers in the element layer forming a contact hole for providing a pixel electrode in the inter-layer insulator; forming a transparent conductive film on the second film-shaped interlayer insulator; forming the transparent conductive film and the second The pixel electrode is polished by a mechanical polishing method or a chemical mechanical polishing method until the second film-like interlayer insulator on the gate line and the data line is exposed. The transparent conductive film is in direct contact with the thin film semiconductor layer in the contact hole, the thickness of the thin film semiconductor layer is thinner than any of the gate line and the data line, and the second the thickness of the film-like interlayer insulator Method of manufacturing an active matrix display device characterized by thicker than any of the gate lines and the data lines.