JP3490216B2 - Method for manufacturing switching element substrate - Google Patents

Method for manufacturing switching element substrate

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Publication number
JP3490216B2
JP3490216B2 JP10281796A JP10281796A JP3490216B2 JP 3490216 B2 JP3490216 B2 JP 3490216B2 JP 10281796 A JP10281796 A JP 10281796A JP 10281796 A JP10281796 A JP 10281796A JP 3490216 B2 JP3490216 B2 JP 3490216B2
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JP
Japan
Prior art keywords
insulating film
formed
interlayer insulating
gate
additional capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP10281796A
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Japanese (ja)
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JPH09292626A (en
Inventor
康浩 松島
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP10281796A priority Critical patent/JP3490216B2/en
Priority claimed from US08/718,051 external-priority patent/US5917563A/en
Publication of JPH09292626A publication Critical patent/JPH09292626A/en
Application granted granted Critical
Publication of JP3490216B2 publication Critical patent/JP3490216B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching element substrate provided with a switching element such as a thin film transistor (TFT), and more particularly to a structure in a pixel portion.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a configuration of a conventional liquid crystal display device in which a peripheral drive circuit is formed on a substrate.

In FIG. 6, a gate drive circuit 32 and a source drive circuit 3 are provided on a glass substrate or a quartz substrate 31.
3 and TFT (Thin Film Transistor)
tor) array section 34 is formed. The gate drive circuit 32 is composed of a shift register 32a and a buffer 32b. Also, the source drive circuit 3
3 is composed of a shift register 33a, a buffer 33b, and an analog switch 39 for sampling the video line 38.

In the TFT array section 34, a large number of parallel gate bus lines 11 extending from the gate drive circuit 32 are provided.
6 are provided, and a large number of source bus lines 120 from the source drive circuit 33 are connected to the gate bus line 116.
Are arranged orthogonally to. Further, an additional capacitance common line 114 is arranged in parallel with the gate bus line 116.

Further, the two gate bus wirings 116 and 116, the source bus wirings 120 and 120, as described above,
The TFT 35, the pixel 36, and the additional capacitance 37 are arranged in a rectangular region surrounded by the additional capacitance common wiring 114, 114. At this time, the gate electrode of the TFT 35 is connected to the gate bus line 116, and the source electrode of the TFT 35 is connected to the source bus line 120.

A liquid crystal is sealed between the pixel electrode 36 connected to the drain of the TFT 35 and the counter electrode formed on the counter substrate to form a pixel. At this time, the additional capacitance common line 114 is connected to the electrode having the same potential as the counter electrode.

FIG. 4 is a plan view showing the structure of one pixel in the conventional liquid crystal display device, and FIG. 5 is a sectional view taken along the line BB 'in the liquid crystal display device of FIG.

In FIG. 4 and FIG. 5, the insulating substrate 110 is used.
A polycrystalline silicon thin film 111 serving as an active layer is formed on the upper surface of the thin film 40.
The gate insulating film 113 is formed to have a thickness of 80 nm to 80 nm, and the gate insulating film 113 is formed to have a thickness of 80 nm to 150 nm by sputtering or CVD.

Then, in the polycrystalline silicon thin film 111, P + is ion-implanted at a concentration of 1 × 10 15 (cm −2 ) into an additional capacitance portion (hatched portion in FIG. 4) which will later form an additional capacitance. The gate electrode 116a and the additional capacitance upper electrode 114a were formed by patterning polycrystalline silicon into a predetermined shape.

Then, in order to determine the conductivity type of the thin film transistor, from above the gate electrode 116a,
Ions were implanted into P + at a concentration of 1 × 10 15 (cm −2 ) to form a channel 112 below the gate electrode 116a.

Further, after the first interlayer insulating film 115 is formed on the entire surface of the substrate by using SiO 2 or SiNx, contact holes 118 and 119 are formed, and the source bus wiring 120 and the stacked electrode 121 are made of Al or the like. It was formed by using a resistance metal.

Then, like the first interlayer insulating film 115, a second interlayer insulating film 124 is formed on the entire surface of the substrate by using SiO 2 or SiNx, and then the contact hole 1 is formed.
23 was formed, and then the contact hole 123 was covered, and a barrier metal 126 was formed using TiW.
Further, a pixel electrode 125 made of a transparent conductive film such as ITO was formed to cover the barrier metal 126. An ohmic contact is made between the pixel electrode 125 and the stacked electrode 121 via the barrier metal 126.

In the liquid crystal display device having the above structure, the additional capacitance common wiring is formed by using the same material as the gate bus wiring so that the large additional capacitance can be obtained in the smallest possible area. It had a body structure. That is, since the gate insulating film is thin and has a large relative permittivity, it becomes a dielectric that can obtain a large additional capacitance while maintaining a high aperture ratio.

[0014]

In the above conventional liquid crystal display device, in order to obtain a large additional capacitance while obtaining a high aperture ratio, the additional capacitance common wiring is formed using the same material as the gate bus wiring. The lower gate insulating film is a dielectric. However, in the conventional liquid crystal display device, since the additional capacitance common wiring is formed of the same material as the gate bus wiring, when the gate bus wiring is formed of a material having a higher electrical resistance than the source bus wiring,
There has been a problem of signal propagation delay in the additional capacitance common wiring.

The present invention has been made to solve the above problems, and its purpose is to:
It is an object of the present invention to provide a switching element substrate that does not have a problem of signal propagation delay in the additional capacitance common wiring and can use the gate insulating film as a dielectric of the additional capacitance.

[0016]

A switching element according to the present invention
The method of manufacturing the sub-substrate is such that a polycrystalline silicon thin film and a
A gate insulating film and a gate bus line are formed, and the gate is formed.
On top of the bus wiring, the first interlayer insulating film and the source bus wiring
And the second interlayer insulating film and the pixel electrode are formed, respectively.
In the manufacturing method of the switching element substrate,
Partial electrode same process and same material as the source bus wiring
The contact provided on the first interlayer insulating film.
Forming so as to cover the holes and lower part of the additional capacitance
Forming the electrodes from polycrystalline silicon.
The above-mentioned object is achieved by the following features.

Preferably, the method includes a step of forming the first interlayer insulating film with a photosensitive organic material.

The operation will be described below.

According to the method of manufacturing a switching element substrate of the present invention, a non-single crystal silicon thin film, a gate insulating film, and a gate bus wiring are formed on a substrate, and a first interlayer insulating film is formed on the gate bus wiring. In the method of manufacturing a switching element substrate having a source bus line, a second interlayer insulating film, and a pixel electrode, the additional capacitor upper electrode is formed of the same material as the source bus line on the first interlayer insulating film. The method for manufacturing a conventional switching element substrate is characterized by including a step of forming so as to cover the provided contact hole and a step of forming the additional capacitance lower electrode with non-single-crystal silicon. It is possible to solve the problem of the signal propagation delay in the additional capacitance common wiring without adding an additional device or process. Further, since the gate insulating film is used as the dielectric of the additional capacitance, it is possible to reduce the area of the additional capacitance portion which is the light shielding film.

Preferably, by including a step of forming the first interlayer insulating film with a photosensitive organic material, the contact hole is formed in the first interlayer insulating film by an optical method which does not require etching. It becomes possible to carry out by a simple manufacturing process. As a result, the problem of damaging the gate insulating film due to etching does not occur.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a plan view showing the structure of one pixel in a liquid crystal display device using a switching element substrate according to an embodiment of the present invention, and FIG. 2 is a view of A in the liquid crystal display device of FIG. The -A 'line sectional view is shown.

The configuration of the liquid crystal display device according to this embodiment will be described below.

1 and 2, a polycrystalline silicon thin film 11 is provided on an insulating substrate 10, and a gate insulating film 13 is provided on the polycrystalline silicon thin film 11. A gate electrode 16a made of Al or polycrystalline silicon is provided on the gate insulating film 13.
A non-doped channel portion 12 is provided below the gate electrode 16a, and a region other than the channel portion 12 is a high-concentration impurity region. Further, a first interlayer insulating film 15 is provided so as to cover them, and the source bus wiring 20 and the stacked electrode 21 are respectively provided through the contact holes 18 and 19 formed in the first interlayer insulating film. It is electrically connected to the polycrystalline silicon thin film 11. Further, the additional capacitance upper electrode 14 is formed on the inner wall of the contact hole 28, and the second interlayer insulating film 24 is further provided on the upper electrode 14 and the second interlayer insulating film 2.
The pixel electrode 25 is connected to the stacked electrode 21 through a contact hole 23 provided in No. 4. The barrier metal 26 may be formed using TiW or the like in order to make ohmic contact between the stacked electrode 21 and the pixel electrode 25.

A method of manufacturing the liquid crystal display device having the above structure will be described below.

FIGS. 3A to 3G are flow charts showing a method of manufacturing the liquid crystal display device of FIG.

In FIG. 3A, first, a polycrystalline silicon thin film 11 to be an active layer is formed to a thickness of 40 nm to 80 nm on an insulating substrate 10 made of glass or quartz, and then the polycrystalline silicon thin film 11 is formed. On top of the SiO 2 or SiN by sputtering or CVD method
The gate insulating film 13 made of x was formed to a thickness of 80 nm.

Further, as shown in FIG. 3B, a gate electrode 16a made of Al or polycrystalline silicon was formed on the gate insulating film 13. Then, in order to determine the conductivity type of this thin film transistor, P + is ion-implanted from above the gate electrode 16a at a concentration of 1 × 10 15 (cm −2 ) using the gate electrode 16a as a mask, A non-doped channel portion 12 was formed below the gate electrode 16a in the active layer, and a high-concentration impurity region was formed in a region other than the channel portion 12. When the additional capacitance upper electrode is formed of the same material as the gate electrode 16a, ion implantation into the additional capacitance lower electrode region cannot be performed simultaneously with the formation of the channel portion 12. However, in the first embodiment, the resistance of the additional capacitance lower electrode can be reduced at the same time when the channel portion 12 is formed. At this time, in the active layer of the TFT, a low-concentration impurity region or a non-doped region may be provided near the channel portion 12 to reduce the leak current when the TFT is off. Thereafter, in the gate insulating film 13, contact regions 5 in which contact holes 18 and 19 will be formed later are formed.
8 and 59 were formed.

Next, as shown in FIG. 3C, a first interlayer insulating film 15 having a thickness of 2.5 μm is formed on the entire surface of the substrate by a spin coating method using a photosensitive acrylic resin. did. Here, by laminating the first interlayer insulating film 15 by 2 μm or more, the lower region of the first interlayer insulating film 15 could be planarized.

After this, as shown in FIG. 3D, exposure and development were performed to form contact holes 18 and 19 on the first interlayer insulating film 15. Further, in the present invention, the contact hole 28 that serves as the additional capacitance forming portion is formed. Since the first interlayer insulating film 15 is made of a photosensitive material, it is possible to form the contact holes 18, 19 and 28 only by exposing and developing without etching, which simplifies the manufacturing process. I was able to. Since no etching is done,
Reliability can be improved without damaging the lower gate insulating film.

Next, as shown in FIG. 3E, the source bus line 20, the stacked electrode 21, and the additional capacitance upper electrode 14 were formed using a low resistance metal such as Al.
The additional capacitance upper electrode 14 is formed so as to cover the inner wall of the contact hole 28. At this time, the lower region of the source bus line 20 is formed on the first interlayer insulating film 15.
Since it is flattened by, the source bus line 20 is disconnected due to the step of the gate bus line 16 even at the intersection of the source bus line 20 and the gate bus line 16 as shown in FIG. Things will disappear. Here, the photosensitive organic resin material used as the first interlayer insulating film 15 has a smaller relative dielectric constant than an inorganic material and can have a larger film thickness, so that the source bus wiring 20 and The capacitance at the intersection with the gate bus line 16 can be ignored, and the propagation delay of the signal generated in the bus line can be prevented. Further, since Al having a low resistance is used for the additional capacitance upper electrode 14 and the additional capacitance common wiring, the problem of signal propagation delay occurring in the additional capacitance wiring does not occur. Furthermore, since the additional capacitance is formed in the gate insulating film 13 immediately below the additional capacitance upper electrode 14, the aperture ratio is not reduced.

Next, as shown in FIG. 3F, a second interlayer insulating film 24 was formed by using a photosensitive acrylic resin similarly to the first interlayer insulating film 15. Furthermore, FIG. 3 (g)
As shown in FIG. 7, the second interlayer insulating film 24 was exposed and developed to form a contact hole 23, and a pixel electrode 25 was formed of ITO by a transparent conductive film. When the ohmic contact between the stacked electrode 21 and the pixel electrode 25 is a problem, the contact hole 2
The barrier metal 26 may be formed on the substrate 3.

As described above, in the switching element substrate and the method of manufacturing the same according to the present invention, the problem of signal propagation delay in the additional capacitance common wiring does not occur, and the gate insulating film is used as the dielectric of the additional capacitance. When applied to a liquid crystal display device, a high aperture ratio can be realized.

[0040]

[Effects of the Invention] Method of manufacturing the switching element substrate of the present invention
The method is to add the upper electrode of the additional capacitor to the same material as the source bus wiring.
Depending on the material, the contact provided on the first interlayer insulating film.
The process of forming to cover the
Forming a partial electrode from non-single crystal silicon
The conventional switching element is characterized by
Do not add new equipment or processes to the board manufacturing method.
The problem of signal propagation delay at the common electrode of the additional capacitance.
It can be resolved. Also, as a dielectric of the additional capacitance
Since a gate insulating film is used, it is an additional
It is possible to reduce the area of the volume part,
If applied, the aperture ratio can be improved, and as a result,
It is possible to realize a liquid crystal display device with excellent display quality.
It becomes Noh.

Preferably, by including a step of forming the first interlayer insulating film with a photosensitive organic material, the contact hole is formed in the first interlayer insulating film by an optical method which does not require etching. It becomes possible. As a result, the problem of damaging the gate insulating film due to etching does not occur, so that the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of one pixel in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA ′ in the liquid crystal display device of FIG.

3A to 3G are flowcharts showing a method of manufacturing the liquid crystal display device of FIG.

FIG. 4 is a plan view showing a configuration for one pixel in a conventional liquid crystal display device.

5 is a cross-sectional view taken along the line BB ′ in the liquid crystal display device of FIG.

FIG. 6 is a circuit diagram showing a configuration of a conventional liquid crystal display device in which a peripheral drive circuit is formed on a substrate.

[Explanation of symbols]

10 Insulating substrate 11 Polycrystalline silicon thin film 12 channel section 13 Gate insulating film 14 Additional capacitance upper electrode 15 First interlayer insulating film 16 gate bus wiring 16a gate electrode 18 contact holes 19 contact holes 20 Source bus wiring 21 Stacked electrodes 23 Contact holes 24 Second interlayer insulating film 25 pixel electrodes 26 Barrier metal 28 contact holes 31 substrate 32 gate drive circuit 32a shift register 32b buffer 33 Source drive circuit 33a shift register 33b buffer 34 TFT array section 35 TFT 36 pixels 37 additional capacity 38 video lines 39 analog switch 58 Contact area 59 Contact area 110 insulating substrate 111 Polycrystalline silicon thin film 112 channels 113 Gate insulating film 114 Common wiring for additional capacitance 114a Additional capacitance upper electrode 115 First interlayer insulating film 116 gate bus wiring 116a gate electrode 118 contact holes 119 contact holes 120 source bus wiring 121 stacked electrodes 123 contact holes 124 Second interlayer insulating film 125 pixel electrodes 126 barrier metal

Claims (2)

(57) [Claims]
1. A polycrystalline silicon thin film, a gate insulating film, and a gate bus wiring are formed on a substrate, and a first interlayer insulating film, a source bus wiring, and a second interlayer insulating are formed on the gate bus wiring. In a method of manufacturing a switching element substrate having a film and a pixel electrode respectively formed thereon, a contact hole formed in the first interlayer insulating film is covered with the additional capacitor upper electrode in the same step and with the same material as the source bus wiring. And a step of forming the additional capacitance lower electrode from polycrystalline silicon.
2. A method of manufacturing a switching device substrate according to claim 1, comprising the step of forming an organic material having photosensitivity said first interlayer insulating film.
JP10281796A 1996-04-24 1996-04-24 Method for manufacturing switching element substrate Expired - Lifetime JP3490216B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10281796A JP3490216B2 (en) 1996-04-24 1996-04-24 Method for manufacturing switching element substrate

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP10281796A JP3490216B2 (en) 1996-04-24 1996-04-24 Method for manufacturing switching element substrate
US08/718,051 US5917563A (en) 1995-10-16 1996-09-13 Liquid crystal display device having an insulation film made of organic material between an additional capacity and a bus line
US09/233,168 US6141066A (en) 1995-10-16 1999-01-19 Liquid crystal display device with active matrix substrate using source/drain electrode as capacitor conductor
US09/648,553 US6359665B1 (en) 1995-10-16 2000-08-28 Switching element substrate having additional capacity and manufacturing method thereof
US10/052,345 US6806932B2 (en) 1995-10-16 2002-01-23 Semiconductor device
US10/839,215 US7057691B2 (en) 1995-10-16 2004-05-06 Semiconductor device
US11/292,357 US7190418B2 (en) 1995-10-16 2005-12-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH09292626A JPH09292626A (en) 1997-11-11
JP3490216B2 true JP3490216B2 (en) 2004-01-26

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973787B2 (en) 1997-12-31 2007-09-12 三星電子株式会社Samsung Electronics Co.,Ltd. Liquid crystal display device and manufacturing method thereof
TW478014B (en) 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
JP4700156B2 (en) * 1999-09-27 2011-06-15 株式会社半導体エネルギー研究所 Semiconductor device
JP4132508B2 (en) 1999-12-13 2008-08-13 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US7456911B2 (en) * 2000-08-14 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TW525216B (en) 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
JP4506133B2 (en) * 2002-10-31 2010-07-21 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
JP4095518B2 (en) 2002-10-31 2008-06-04 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
KR100683713B1 (en) * 2004-11-25 2007-02-15 삼성에스디아이 주식회사 A organic thin film transistor and a flat panel display device having the same
KR20070002933A (en) * 2005-06-30 2007-01-05 엘지.필립스 엘시디 주식회사 Poly thin film transistor substrate and method of fabricating the same
WO2007111044A1 (en) * 2006-03-24 2007-10-04 Sharp Kabushiki Kaisha Liquid crystal display
JP4994491B2 (en) * 2010-11-10 2012-08-08 株式会社半導体エネルギー研究所 projector
JP5298156B2 (en) * 2011-04-20 2013-09-25 株式会社半導体エネルギー研究所 Front type projector and semiconductor device
JP5786600B2 (en) * 2011-09-28 2015-09-30 セイコーエプソン株式会社 Electro-optical device, manufacturing method thereof, and electronic device
JP5613717B2 (en) * 2012-04-25 2014-10-29 株式会社半導体エネルギー研究所 Semiconductor device, module and electronic device
JP5685613B2 (en) * 2013-02-27 2015-03-18 株式会社半導体エネルギー研究所 Display device

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