JPH07114281B2 - Driver-Built-in active matrix substrate - Google Patents
Driver-Built-in active matrix substrateInfo
- Publication number
- JPH07114281B2 JPH07114281B2 JP61096301A JP9630186A JPH07114281B2 JP H07114281 B2 JPH07114281 B2 JP H07114281B2 JP 61096301 A JP61096301 A JP 61096301A JP 9630186 A JP9630186 A JP 9630186A JP H07114281 B2 JPH07114281 B2 JP H07114281B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- built
- active matrix
- drive circuit
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 28
- 239000011159 matrix material Substances 0.000 title claims description 14
- 239000010409 thin film Substances 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008832 photodamage Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、透明絶縁基板上に薄膜トランジスタを形成し
たドライバー内蔵アクティブマトリックス基板の構造に
関する。The present invention relates to a structure of an active matrix substrate with a built-in driver in which a thin film transistor is formed on a transparent insulating substrate.
近年、絶縁基板上に堆積した半導体薄膜を能動領域とし
て用いたMOS型薄膜トランジスターは、液晶表示装置の
画素の光スイッチとしてばかりでなく、周辺の駆動回路
も構成できるほどに性能があがっている。しかし、絶縁
基板を用いたデバイスでは、絶縁基板表面に生じた電荷
をいかに外部に放散して、薄膜トランジスターの絶縁破
壊を防止するかが課題である。特に液晶表示装置のよう
に、パネル表示部分の面積が大きいデバイスでは製造工
程中での基板表面でのチャージアップをいかに防止する
かが重要である。In recent years, a MOS type thin film transistor using a semiconductor thin film deposited on an insulating substrate as an active region has improved in performance not only as an optical switch of a pixel of a liquid crystal display device but also as a peripheral drive circuit. However, in a device using an insulating substrate, how to dissipate the charge generated on the surface of the insulating substrate to the outside to prevent the dielectric breakdown of the thin film transistor is a problem. Particularly in a device such as a liquid crystal display device having a large panel display area, it is important to prevent charge-up on the substrate surface during the manufacturing process.
第2図は、透明絶縁基板上にマトリックス状に配置され
た薄膜トランジスターと周辺駆動回路から構成された液
晶表示用ドライバー内蔵アクティブマトリックス基板の
模式図である。1(G1〜Gm)は、タイミング線となるゲ
ート線、2(S1〜Sn)は、データ線となるソース線であ
り、3の薄膜トランジスターと4の画素電極は、ゲート
線,ソース線の交点に配置されている。5は、タイミン
グ線駆動回路、6はデータ線駆動回路であり、この図で
は両側駆動の場合を示している。FIG. 2 is a schematic diagram of an active matrix substrate with a built-in driver for liquid crystal display, which is composed of thin film transistors arranged in a matrix on a transparent insulating substrate and a peripheral driving circuit. 1 (G 1 to G m ) is a gate line that is a timing line, 2 (S 1 to S n ) is a source line that is a data line, and 3 thin film transistors and 4 pixel electrodes are gate lines, It is located at the intersection of the source lines. Reference numeral 5 is a timing line drive circuit, and 6 is a data line drive circuit. In this figure, the case of double-sided drive is shown.
第3図は、前記模式図で構成された従来の液晶表示用ド
ライバー内蔵アクティブマトリックス基板の外周近傍の
平面図(a)と断面図(b)である。透明絶縁基板7上
に化学反応を媒介として結晶や非晶質を被着させるCVD
法により、多結晶シリコン薄膜8を堆積させる。次に、
多結晶シリコン薄膜のパターン形成を行なった後、ゲー
ト絶縁膜9を形成し、その上に金属や多結晶シリコン薄
膜を用いたゲート電極10及びゲート線1を駆動回路内を
含めて同時形成する。次に、ゲート電極10とレジストを
マスクに用いて、P型不純物イオンとN型不純物イオン
を選択的にイオン打込みをしてP型とN型の薄膜トラン
ジスターのソース・ドレイン領域を形成する。次に、層
間絶縁膜11をCVD法により積層し、コンタクトホール12
を開口した後、透明導電膜を被着して、画素電極4を形
成し金属を被着して、ソース線2及び、周辺のタイミン
グ線駆動回路5とデータ線駆動回路6内の配線とする。FIG. 3 is a plan view (a) and a cross-sectional view (b) in the vicinity of the outer periphery of the conventional active matrix substrate with a built-in driver for liquid crystal display constructed as the schematic diagram. CVD for depositing crystals or amorphous materials on transparent insulating substrate 7 through chemical reaction
The polycrystalline silicon thin film 8 is deposited by the method. next,
After patterning the polycrystalline silicon thin film, a gate insulating film 9 is formed, and a gate electrode 10 and a gate line 1 using a metal or a polycrystalline silicon thin film are simultaneously formed on the gate insulating film 9 including in the drive circuit. Next, using the gate electrode 10 and the resist as a mask, P-type impurity ions and N-type impurity ions are selectively ion-implanted to form source / drain regions of P-type and N-type thin film transistors. Next, the interlayer insulating film 11 is laminated by the CVD method, and the contact hole 12
After opening, a transparent conductive film is deposited, a pixel electrode 4 is formed, and a metal is deposited to form the source line 2 and wirings in the peripheral timing line driving circuit 5 and data line driving circuit 6. .
しかし、前述の従来技術では、イオン打込みの工程で透
明絶縁基板上にチャージアップされた電荷の逃げ路がな
いため、薄膜トランジスターの絶縁破壊を生じやすい。
そのため、イオン打込み時には、基板表面近傍で打込み
イオンを熱電子により中性化する打込み方式を採用する
のであるが、完全な中性化は難しく、外観上不明な程度
の軽いダメージが発生する。このようなダメージに対し
て、画素を駆動する薄膜トランジスターは、レーザー等
を用いて、切断することによってその画素のみを犠牲に
するだけすむ。ところが、周辺にある駆動回路部分の薄
膜トランジスターは、1つでも不良があると動作不良を
おこすという問題点を生ずる。そこで本発明は、このよ
うな問題点を解決するもので、その目的とするところ
は、薄膜トランジスターの絶縁破壊耐量を増加した周辺
駆動回路を提供するところにある。However, in the above-mentioned conventional technique, since there is no escape route for the charges charged up on the transparent insulating substrate in the step of ion implantation, dielectric breakdown of the thin film transistor is likely to occur.
Therefore, at the time of ion implantation, an implantation method in which implanted ions are neutralized by thermoelectrons in the vicinity of the surface of the substrate is adopted, but complete neutralization is difficult and light damage of unknown extent occurs. With respect to such damage, the thin film transistor for driving the pixel only needs to sacrifice only the pixel by cutting with a laser or the like. However, if there is even one defective thin film transistor in the peripheral driving circuit portion, there is a problem that malfunction occurs. Therefore, the present invention solves such a problem, and an object of the present invention is to provide a peripheral drive circuit in which the dielectric breakdown resistance of a thin film transistor is increased.
本発明のドライバー内蔵アクティブマトリックス基板
は、周辺駆動回路を導電膜の配線で囲うと共に、基板周
辺にも導電膜領域をもうけ、両者を短絡することを特徴
とする。The active matrix substrate with a built-in driver according to the present invention is characterized in that the peripheral driving circuit is surrounded by conductive film wiring, and a conductive film region is provided around the substrate to short-circuit both.
本発明の上記の構造によれば、駆動回路は、導電膜の配
線でシールドされたことになり、大面積を占める表示部
分からのチャージアップした電荷は基板周辺を接地する
ことで外部に放散できるため駆動回路内の薄膜トランジ
スターのダメージをなくすことが可能である。According to the above structure of the present invention, the drive circuit is shielded by the wiring of the conductive film, and the charge up from the display portion occupying a large area can be dissipated to the outside by grounding the periphery of the substrate. Therefore, damage to the thin film transistor in the driver circuit can be eliminated.
第1図は、本発明の実施例であり、液晶表示用ドライバ
ー内蔵アクティブマトリックス基板の外周近傍の平面図
である。第3図の従来例と同様な工程で形成されている
が、第3図に比して第1図では駆動回路をゲート線と同
一の材料からなるシールド配線13で囲うため、駆動回路
内の薄膜トランジスターは、完全にシールドされる。さ
らにシールド配線13は透明絶縁基板周辺に設られた導電
膜14に接続されているため、イオン打ち込み等によりチ
ャージアップした電荷は基板周辺を接地することで外部
に放散でき、絶縁破壊を十分防止することができる。ま
た、シールド配線13は、本実施例のように、ゲート線と
同一材料で同時に形成されてもよいが、同一材料にする
必要はなく、異種の導線膜を用いても何らさしつかえな
い。さらに、シールド配線13は駆動回路内の薄膜トラン
ジスターのゲート配線層と同一層で形成してもよい。FIG. 1 is an embodiment of the present invention and is a plan view of the vicinity of the outer periphery of an active matrix substrate with a built-in driver for liquid crystal display. Although it is formed by the same process as the conventional example of FIG. 3, compared with FIG. 3, the drive circuit is surrounded by the shield wiring 13 made of the same material as the gate line in FIG. The thin film transistor is completely shielded. Further, since the shield wiring 13 is connected to the conductive film 14 provided in the periphery of the transparent insulating substrate, the charge charged up by ion implantation or the like can be dissipated to the outside by grounding the periphery of the substrate, thereby sufficiently preventing dielectric breakdown. be able to. Further, the shield wiring 13 may be formed of the same material as the gate line at the same time as in the present embodiment, but it is not necessary to use the same material and a different kind of conductor film may be used. Further, the shield wiring 13 may be formed in the same layer as the gate wiring layer of the thin film transistor in the drive circuit.
配線幅は、十ミクロンメートルもとれば十分であり、占
有面積も小さく、工程が増えるわけではないので好都合
である。The wiring width is sufficient if it is 10 μm, the occupied area is small, and the number of steps does not increase, which is advantageous.
以上述べたように本発明によれば、周辺の駆動回路は導
電膜の配線でシールドされたことになり、イオン打込み
等で発生するチャージアップされた表面電荷による駆動
回路内の薄膜トランジスターの絶縁破壊を防止するとい
う効果を有する。また酸素プラズマ等のクリーニング工
程でも、ダメージ防止に役立つものである。As described above, according to the present invention, the peripheral drive circuit is shielded by the wiring of the conductive film, and the dielectric breakdown of the thin film transistor in the drive circuit due to the charged surface charge generated by ion implantation or the like. Has the effect of preventing Also, it is useful for preventing damage even in a cleaning process using oxygen plasma or the like.
第1図は、本発明の液晶表示用ドライバー内蔵アクティ
ブマトリックス基板の外周近傍の平面図である。第2図
は、液晶表示用ドライバー内蔵アクティブマトリックス
基板の模式図である。第3図は、従来の液晶表示用ドラ
イバー内蔵アクティブマトリックス基板の外周近傍の平
面図(a)と断面図(b)である。 1……ゲート線(タイミング線) 2……ソース線(データ線) 3……薄膜トランジスター 4……画素電極 5……タイミング線駆動回路 6……データ線駆動回路 7……透明絶縁基板 8……多結晶シリコン薄膜 9……ゲート絶縁膜 10……ゲート電極 11……層間絶縁膜 12……コンタクトホール 13……シールド配線 14……導電膜FIG. 1 is a plan view of the vicinity of the outer periphery of an active matrix substrate with a built-in driver for liquid crystal display of the present invention. FIG. 2 is a schematic diagram of an active matrix substrate with a built-in driver for liquid crystal display. FIG. 3 is a plan view (a) and a sectional view (b) in the vicinity of the outer periphery of a conventional active matrix substrate with a built-in driver for liquid crystal display. 1 ... Gate line (timing line) 2 ... Source line (data line) 3 ... Thin film transistor 4 ... Pixel electrode 5 ... Timing line drive circuit 6 ... Data line drive circuit 7 ... Transparent insulating substrate 8 ... … Polycrystalline silicon thin film 9 …… Gate insulating film 10 …… Gate electrode 11 …… Interlayer insulating film 12 …… Contact hole 13 …… Shield wiring 14 …… Conductive film
Claims (3)
て配置されてなり、該データ線及びタイミング線との交
点近傍には薄膜トランジスターが配置されてなり、該薄
膜トランジスターは画素電極に接続されてなり、該デー
タ線及びタイミング線の端部には該データ線または該タ
イミング線を駆動してなる駆動回路が形成されてなるド
ライバー内蔵アクティブマトリックス基板において、 該駆動回路周辺部には、該駆動回路を取り囲みかつ該駆
動回路とは電気的に絶縁されたシールド配線が形成さ
れ、該基板の周辺部には導電膜が形成され、該シールド
配線と該導電膜とは電気的に接続されてなることを特徴
とするドライバー内蔵アクティブマトリックス基板。1. A plurality of data lines and timing lines are arranged so as to intersect with each other, and a thin film transistor is arranged in the vicinity of an intersection with the data line and the timing line. The thin film transistor is connected to a pixel electrode. In an active matrix substrate with a built-in driver in which a drive circuit for driving the data line or the timing line is formed at the ends of the data line and the timing line, the drive circuit is provided around the drive circuit. A shield wiring that surrounds the circuit and is electrically insulated from the drive circuit is formed, a conductive film is formed in the peripheral portion of the substrate, and the shield wiring and the conductive film are electrically connected to each other. An active matrix substrate with a built-in driver.
ランジスターのゲート配線層と同一層であることを特徴
とする特許請求の範囲第1項記載のドライバー内蔵アク
ティブマトリックス基板。2. The active matrix substrate with a built-in driver according to claim 1, wherein the shield wiring is the same layer as a gate wiring layer of a thin film transistor in the drive circuit.
のゲート配線層と同一層であることを特徴とする特許請
求の範囲第1項記載のドライバー内蔵アクティブマトリ
ックス基板。3. The active matrix substrate with a built-in driver according to claim 1, wherein the shield wiring is the same layer as the gate wiring layer of the thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61096301A JPH07114281B2 (en) | 1986-04-25 | 1986-04-25 | Driver-Built-in active matrix substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61096301A JPH07114281B2 (en) | 1986-04-25 | 1986-04-25 | Driver-Built-in active matrix substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62252964A JPS62252964A (en) | 1987-11-04 |
JPH07114281B2 true JPH07114281B2 (en) | 1995-12-06 |
Family
ID=14161207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61096301A Expired - Lifetime JPH07114281B2 (en) | 1986-04-25 | 1986-04-25 | Driver-Built-in active matrix substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07114281B2 (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2816982B2 (en) * | 1989-03-16 | 1998-10-27 | 松下電子工業株式会社 | Liquid crystal display |
US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
US6778231B1 (en) | 1991-06-14 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device |
JP2677167B2 (en) * | 1993-07-08 | 1997-11-17 | 日本電気株式会社 | Method for manufacturing liquid crystal display device with built-in drive circuit |
JP4057127B2 (en) * | 1998-02-19 | 2008-03-05 | セイコーエプソン株式会社 | Active matrix substrate, method of manufacturing active matrix substrate, and liquid crystal device |
JP2004163493A (en) * | 2002-11-11 | 2004-06-10 | Sanyo Electric Co Ltd | Display device |
KR100600865B1 (en) | 2003-11-19 | 2006-07-14 | 삼성에스디아이 주식회사 | Electro luminescence display contained EMI shielding means |
US8355015B2 (en) | 2004-05-21 | 2013-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device and electronic device including a diode electrically connected to a signal line |
KR100726090B1 (en) | 2004-12-30 | 2007-06-08 | 엘지.필립스 엘시디 주식회사 | TFT array substrate and the fabrication method thereof |
JP5130916B2 (en) * | 2008-01-08 | 2013-01-30 | 三菱電機株式会社 | Scanning line drive circuit for active matrix |
JP5256938B2 (en) * | 2008-08-27 | 2013-08-07 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
CN103033728B (en) * | 2011-10-08 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Time dependent dielectric breakdown test circuit and method of testing |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0814667B2 (en) * | 1984-05-28 | 1996-02-14 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
-
1986
- 1986-04-25 JP JP61096301A patent/JPH07114281B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS62252964A (en) | 1987-11-04 |
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