JPH0814667B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0814667B2 JPH0814667B2 JP59107694A JP10769484A JPH0814667B2 JP H0814667 B2 JPH0814667 B2 JP H0814667B2 JP 59107694 A JP59107694 A JP 59107694A JP 10769484 A JP10769484 A JP 10769484A JP H0814667 B2 JPH0814667 B2 JP H0814667B2
- Authority
- JP
- Japan
- Prior art keywords
- gate line
- gate
- line
- insulating substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 42
- 239000010409 thin film Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 13
- 239000010408 film Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- -1 carbon halide Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、絶縁基板上に半導体薄膜を能動領域として
用いたMOS型薄膜トランジスターを複数個用いた薄膜半
導体装置において、工程上生ずる絶縁基板表面での電荷
の蓄積や、静電気によるソース・ゲート間の絶縁破壊の
防止方法と薄膜トランジスターの分離に関する。Description: TECHNICAL FIELD The present invention relates to a thin film semiconductor device using a plurality of MOS thin film transistors in which a semiconductor thin film is used as an active region on an insulating substrate, and a charge generated on the surface of the insulating substrate during the process. It relates to a method of preventing the accumulation of electric charges and dielectric breakdown between the source and the gate due to static electricity, and separation of thin film transistors.
近年、絶縁基板上に堆積した半導体薄膜を能動領域と
して用いたMOS型薄膜トランジスターは、液晶表示装
置，論理回路，イメージセンサ等への応用として使われ
ている。これらの応用分野においては、絶縁基板の大面
積化を行なうと、絶縁基板表面に生じた電荷をいかに外
部に放散して、ソース・ゲート間の絶縁破壊を防止する
かが課題となる。特に、薄膜トランジスターのソース・
ドレイン領域をイオン注入によつて形成する場合には、
絶縁基板表面でチヤージアツプによる瞬間過剰電流によ
り、ソース・ゲート間の絶縁破壊はもちろんのこととし
て、ゲート線の破損による断線さえも起こすことがあ
る。In recent years, MOS type thin film transistors using a semiconductor thin film deposited on an insulating substrate as an active region have been used for applications in liquid crystal display devices, logic circuits, image sensors and the like. In these fields of application, when the area of the insulating substrate is increased, the problem is how to dissipate the charges generated on the surface of the insulating substrate to the outside to prevent the dielectric breakdown between the source and the gate. Especially, the source of thin film transistor
When the drain region is formed by ion implantation,
Instantaneous excess current on the surface of the insulating substrate due to charge jumps may cause not only dielectric breakdown between the source and the gate but also disconnection due to breakage of the gate line.
第１図は、従来の透明絶縁基板にマトリツクス状に配
置された薄膜トランジスターから構成された液晶表示パ
ネル基板の模式図である。１（G1〜Gm）はゲート線、２
（S1〜Sn）はソース線であり、３の薄膜トランジスター
と４の画素電極は、ゲート・ソース線の交点に配置され
ている。FIG. 1 is a schematic view of a conventional liquid crystal display panel substrate composed of thin film transistors arranged in a matrix on a transparent insulating substrate. 1 (G 1 to Gm) is a gate line, 2
(S 1 to Sn) are source lines, and the thin film transistor 3 and the pixel electrode 4 are arranged at the intersections of the gate and source lines.
第２図は、前記模式図で構成された液晶表示マトリツ
クス基板の外周近傍の平面図（ａ）と、断面図（ｂ）で
ある。透明絶縁基板５上に、気相から化学反応を媒介と
して結晶や非晶質を被着させるCVD法により、多結晶シ
リコン薄膜６を堆積させる。次に、多結晶シリコン薄膜
のパターン形成を行なつた後、CVD法により、ゲート絶
縁膜７を積層し、その上に金属や多結晶シリコン薄膜を
用いたゲート電極８を形成する。ゲート電極は、１本の
ゲート線に接続されており、個々のゲート線は周辺にて
短絡されている。ゲート線の周辺での短絡の目的は、ゲ
ート電極８をマスクにしたイオン打込みで、ソース・ド
レイン部を形成する際に絶縁基板表面に蓄積された電荷
をゲート線により基板周辺９に放散させ、基板周辺より
イオン注入装置に短絡させることにより、突発的な過剰
電流による、ソース・ゲート間の絶縁破壊とゲート線の
破損を防止するためである。次に、層間絶縁膜10をCVD
法により積層し、ソースコンタクトホール11及びドレイ
ンコンタクトホール12を形成した後、透明導電膜を被着
して、ソース線２及び画素電極４を形成する。ソース線
２はゲート配線と、短絡用のコンタクトホール13を用い
て短絡しておけば、後工程中に入いる静電気による絶縁
破壊等の防止に役だつものである。ゲート線１及びソー
ス線２の分離は、最終工程で外周部をダイシングして切
断することによつて行なわれる。FIG. 2 is a plan view (a) and a sectional view (b) in the vicinity of the outer periphery of the liquid crystal display matrix substrate constructed in the schematic diagram. A polycrystalline silicon thin film 6 is deposited on the transparent insulating substrate 5 by a CVD method in which a crystal or an amorphous substance is deposited from a gas phase through a chemical reaction. Next, after patterning the polycrystalline silicon thin film, a gate insulating film 7 is laminated by a CVD method, and a gate electrode 8 using a metal or a polycrystalline silicon thin film is formed thereon. The gate electrode is connected to one gate line, and each gate line is short-circuited in the periphery. The purpose of short-circuiting around the gate line is to perform ion implantation using the gate electrode 8 as a mask so that the charges accumulated on the surface of the insulating substrate when forming the source / drain portions are diffused to the substrate periphery 9 by the gate line. This is to prevent the dielectric breakdown between the source and the gate and the damage to the gate line due to a sudden excess current by short-circuiting from the periphery of the substrate to the ion implantation device. Next, the interlayer insulating film 10 is CVD
After stacking by the method to form the source contact hole 11 and the drain contact hole 12, a transparent conductive film is deposited to form the source line 2 and the pixel electrode 4. If the source line 2 is short-circuited with the gate line using the short-circuiting contact hole 13, the source line 2 is useful for preventing dielectric breakdown or the like due to static electricity entering in a later process. The gate line 1 and the source line 2 are separated by dicing and cutting the outer peripheral portion in the final step.
第２図は、ゲート線１及びソース線２が、透明絶縁基
板５の周辺に直接短絡できる構造であるため、静電気等
による絶縁破壊の防止が可能であるが、第３図のよう
に、同一基板上でゲート線１がゲート線駆動回路14、ま
たソース線２がソース線駆動回路15とコンタクトホール
を介した配線により連結されている構造のマトリツクス
基板の場合には、ゲート線が外周部と短絡できないため
に、特にイオン打込みによつて透明絶縁基板上にチヤー
ジアツプされた電荷の逃げ路がなく、突発的な過剰電流
によつて、外周部の薄膜トランジスターの絶縁破壊や、
ゲート線の破壊を生ずることがある。FIG. 2 shows a structure in which the gate line 1 and the source line 2 can be short-circuited directly to the periphery of the transparent insulating substrate 5, so that dielectric breakdown due to static electricity or the like can be prevented, but as shown in FIG. In the case of a matrix substrate having a structure in which the gate line 1 is connected to the gate line drive circuit 14 and the source line 2 is connected to the source line drive circuit 15 by wiring via contact holes on the substrate, the gate lines are connected to the outer peripheral portion. Since it is not possible to short-circuit, there is no escape route for the charge charged on the transparent insulating substrate by ion implantation, and due to a sudden excess current, dielectric breakdown of the thin film transistor in the outer peripheral portion,
This may cause damage to the gate lines.
本発明は、かかる欠点を除去したもので、その目的
は、大面積の絶縁基板上に複雑に構成された複数個の薄
膜トランジスターを用いた薄膜半導体装置において、静
電気やイオン打込み等による薄膜トランジスターのソー
ス・ゲート間の絶縁破壊やゲート線の破壊を防止するこ
とである。The present invention eliminates such drawbacks, and an object thereof is to provide a thin film semiconductor device using a plurality of thin film transistors that are complicatedly configured on an insulating substrate having a large area, and to provide a thin film transistor by static electricity or ion implantation. This is to prevent insulation breakdown between the source and gate and breakdown of the gate line.
前記の防止は、大面積の絶縁基板上に構成された複数
個の薄膜トランジスターのゲート電極をゲート配線によ
り共通に短絡して、絶縁基板周辺に落とし、後に層間絶
縁膜にコンタクトホールと同時に形成したホールを用い
て、ゲート配線のエツチングをして素子分離をすること
によつて達成される。In order to prevent the above, the gate electrodes of a plurality of thin film transistors formed on a large-area insulating substrate are commonly short-circuited by the gate wiring, dropped to the periphery of the insulating substrate, and later formed simultaneously with the contact holes in the interlayer insulating film. This is achieved by etching the gate wiring using the holes to isolate the elements.
本発明の半導体装置の製造方法は、絶縁基板上に複数
のソース線と複数のゲート線とが交差して配置されてな
り、該ソース線及び該ゲート線に接続して薄膜トランジ
スターが形成されてなり、該薄膜トランジスターに画素
電極が接続されてなり、前記絶縁基板上に該ソース線に
接続してなるソース線駆動回路、該ゲート線に接続して
なるゲート線駆動回路、及び前記絶縁基板周辺に短絡用
配線を形成してなる半導体装置の製造方法において、 前記絶縁基板上にゲート線と前記短絡用配線を形成す
る工程と、 前記薄膜トランジスターと前記ソース線及び前記画素
電極とを接続するためのコンタクトホール、前記短絡用
配線にゲート線分離用ホールを形成する工程と、 該ゲート線分離用ホールを用いてエッチングにより前
記ゲート線と前記短絡用配線との分離を行う工程と、 を少なくとも有することを特徴とする。A method of manufacturing a semiconductor device according to the present invention is configured such that a plurality of source lines and a plurality of gate lines are arranged so as to intersect each other on an insulating substrate, and a thin film transistor is formed by connecting the source lines and the gate lines. And a pixel electrode connected to the thin film transistor, a source line drive circuit connected to the source line on the insulating substrate, a gate line drive circuit connected to the gate line, and the insulating substrate periphery. In a method of manufacturing a semiconductor device having a short-circuit line formed on a substrate, a step of forming a gate line and the short-circuit line on the insulating substrate; and connecting the thin film transistor, the source line, and the pixel electrode. And a step of forming a gate line separating hole in the contact hole and the short circuit wiring, and the gate line and the short circuit by etching using the gate line separating hole. And having a step for separation of the wires, at least.
また、本発明の第２の半導体装置の製造方法は、前記
ゲート線と前記短絡用配線が同一層で形成されてなるこ
とを特徴とする。A second method for manufacturing a semiconductor device of the present invention is characterized in that the gate line and the short-circuit line are formed in the same layer.
また、本発明の第３の半導体装置の製造方法は、前記
絶縁基板がガラス基板であることを特徴とする。Further, a third method for manufacturing a semiconductor device of the present invention is characterized in that the insulating substrate is a glass substrate.
以下、実施例に基づいて本発明を詳しく説明する。 Hereinafter, the present invention will be described in detail based on examples.
第４図は、本発明の実施例である。第３図の従来例に
比べて、ゲート線は、共通短絡線16により、ゲート線と
同じ材料を用いて配線され、透明絶縁基板周辺に接続さ
れているため、第２図の構造と全く類似しており、イオ
ン打込みによる絶縁破壊やゲート線の破壊を防止するこ
とができる。第３図と異なる点は、層間絶縁膜にコンタ
クトホールを開口する際、ゲート線分離用ホール17を同
時に開口することにある。次に、透明導電膜を積層し
て、ソース線及び画素電極を形成してから、ゲート線分
離用ホール17を用いて、ゲート配線のエツチングを行な
い、ゲート線の分離を行なう。ゲート線のエツチング
は、ゲート配線材料として高濃度不純物が添加された多
結晶シリコンを用いる場合には、ハロゲン化炭素を用い
れば容易にエツチングできる。FIG. 4 shows an embodiment of the present invention. Compared with the conventional example of FIG. 3, the gate line is wired by the common short-circuit line 16 using the same material as the gate line and is connected to the periphery of the transparent insulating substrate, so that it is completely similar to the structure of FIG. Therefore, it is possible to prevent dielectric breakdown and gate line breakdown due to ion implantation. The difference from FIG. 3 is that when the contact hole is opened in the interlayer insulating film, the gate line separating hole 17 is simultaneously opened. Next, a transparent conductive film is laminated to form a source line and a pixel electrode, and then the gate line is separated by using the gate line separation hole 17 to etch the gate wiring. Etching of the gate line can be easily performed by using carbon halide when polycrystalline silicon added with a high concentration impurity is used as the gate wiring material.
本実施例は、液晶表示アクティブマトリックスパネル
を例にとって詳述しているが、複数個の薄膜トランジス
ターが絶縁基板上に形成された論理回路においても、ゲ
ート電極を共通に連結しておき、後から同様な分離する
工程を取れば、素子分離が可能であり、三次元集積回路
にも応用できるものである。This embodiment has been described in detail by taking a liquid crystal display active matrix panel as an example. However, even in a logic circuit in which a plurality of thin film transistors are formed on an insulating substrate, the gate electrodes are connected in common and later If a similar step is taken, the element can be separated and can be applied to a three-dimensional integrated circuit.
本発明の製造方法を用いることによって、薄膜トラン
ジスターのソース・ゲート間の絶縁破壊やゲート線の破
壊を防止することができる。また、ゲート配線又は素子
分離のためのエッチング工程が増えるのみで半導体装置
を容易に製造することができる。By using the manufacturing method of the present invention, it is possible to prevent the dielectric breakdown between the source and the gate of the thin film transistor and the breakdown of the gate line. Further, the semiconductor device can be easily manufactured only by increasing the number of etching steps for gate wiring or element isolation.
第１図は、従来の薄膜トランジスターがマトリツクス状
に配置された液晶表示パネル基板の模式図であり、第２
図は、前記基板の外周近傍の平面図（ａ）と断面図
（ｂ）である。第３図は、前記基板の外周部に、駆動回
路を配置した構造をもつパネル基板の従来例であり、第
４図は、本発明によるパネル基板の平面図である。 １……ゲート線（G1〜Gm） ２……ソース線（S1〜Sn） ３……薄膜トランジスター ４……画素電極 ５……透明絶縁基板 ６……多結晶シリコン薄膜 ７……ゲート絶縁膜 ８……ゲート電極 ９……基板周辺 10……層間絶縁膜 11……ソースコンタクトホール 12……ドレインコンタクトホール 13……短絡用コンタクトホール 14……ゲート線駆動回路 15……ソース線駆動回路 16……共通短絡線 17……ゲート線分離用ホールFIG. 1 is a schematic view of a liquid crystal display panel substrate in which conventional thin film transistors are arranged in a matrix.
The figure is a plan view (a) and a cross-sectional view (b) in the vicinity of the outer periphery of the substrate. FIG. 3 is a conventional example of a panel substrate having a structure in which a drive circuit is arranged on the outer peripheral portion of the substrate, and FIG. 4 is a plan view of the panel substrate according to the present invention. 1 …… Gate line (G 1 to Gm) 2 …… Source line (S 1 to Sn) 3 …… Thin film transistor 4 …… Pixel electrode 5 …… Transparent insulating substrate 6 …… Polycrystalline silicon thin film 7 …… Gate insulation Film 8 …… Gate electrode 9 …… Substrate periphery 10 …… Interlayer insulating film 11 …… Source contact hole 12 …… Drain contact hole 13 …… Short circuit contact hole 14 …… Gate line drive circuit 15 …… Source line drive circuit 16: Common short-circuit line 17: Gate line separation hole
Claims (3)
ト線とが交差して配置されてなり、該ソース線及び該ゲ
ート線に接続して薄膜トランジスターが形成されてな
り、該薄膜トランジスターに画素電極が接続されてな
り、前記絶縁基板上に該ソース線に接続してなるソース
線駆動回路、該ゲート線に接続してなるゲート線駆動回
路、及び前記絶縁基板周辺に短絡用配線を形成してなる
半導体装置の製造方法において、 前記絶縁基板上にゲート線と前記短絡用配線を形成する
工程と、 前記薄膜トランジスターと前記ソース線及び前記画素電
極とを接続するためのコンタクトホール、前記短絡用配
線にゲート線分離用ホールを形成する工程と、 該ゲート線分離用ホールを用いてエッチングにより前記
ゲート線と前記短絡用配線との分離を行う工程と、 を少なくとも有することを特徴とする半導体装置の製造
方法。1. A plurality of source lines and a plurality of gate lines are arranged on an insulating substrate so as to intersect with each other, and a thin film transistor is formed by connecting to the source line and the gate line. A pixel electrode connected to the source electrode, a source line drive circuit connected to the source line on the insulating substrate, a gate line drive circuit connected to the gate line, and a short-circuit wiring around the insulating substrate. In the method of manufacturing a semiconductor device formed, a step of forming a gate line and the short-circuit line on the insulating substrate, a contact hole for connecting the thin film transistor, the source line and the pixel electrode, A step of forming a gate line separating hole in the short circuit wiring, and the gate line separating hole is separated by etching using the gate line separating hole. The method of manufacturing a semiconductor device characterized by having a degree, at least.
形成されてなることを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the gate line and the short-circuit line are formed in the same layer.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating substrate is a glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59107694A JPH0814667B2 (en) | 1984-05-28 | 1984-05-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59107694A JPH0814667B2 (en) | 1984-05-28 | 1984-05-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60251665A JPS60251665A (en) | 1985-12-12 |
| JPH0814667B2 true JPH0814667B2 (en) | 1996-02-14 |
Family
ID=14465579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59107694A Expired - Lifetime JPH0814667B2 (en) | 1984-05-28 | 1984-05-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0814667B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07112069B2 (en) * | 1985-09-18 | 1995-11-29 | 株式会社東芝 | Display device |
| JPH07114281B2 (en) * | 1986-04-25 | 1995-12-06 | セイコーエプソン株式会社 | Driver-Built-in active matrix substrate |
| JPH0824187B2 (en) * | 1986-08-11 | 1996-03-06 | ソニー株式会社 | Preventing electrostatic damage to semiconductor devices |
| JP2586127B2 (en) * | 1989-01-04 | 1997-02-26 | 日本電気株式会社 | Electronic circuit board and method of manufacturing the same |
| GB9225906D0 (en) * | 1992-12-11 | 1993-02-03 | Philips Electronics Uk Ltd | Electronic device manufacture using ion implantation |
| GB9416899D0 (en) * | 1994-08-20 | 1994-10-12 | Philips Electronics Uk Ltd | Manufacture of electronic devices comprising thin-film circuitry |
| US7183147B2 (en) | 2004-03-25 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
| JP6209434B2 (en) * | 2013-12-06 | 2017-10-04 | 株式会社ジャパンディスプレイ | Wiring board and display device |
-
1984
- 1984-05-28 JP JP59107694A patent/JPH0814667B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60251665A (en) | 1985-12-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |