CN109300841B - The manufacturing method of array substrate - Google Patents
The manufacturing method of array substrate Download PDFInfo
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- CN109300841B CN109300841B CN201811366363.1A CN201811366363A CN109300841B CN 109300841 B CN109300841 B CN 109300841B CN 201811366363 A CN201811366363 A CN 201811366363A CN 109300841 B CN109300841 B CN 109300841B
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 238000003860 storage Methods 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 238000001259 photo etching Methods 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 239000011521 glass Substances 0.000 claims abstract description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 10
- 229910052738 indium Inorganic materials 0.000 claims abstract description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011787 zinc oxide Substances 0.000 claims abstract description 9
- 238000001459 lithography Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000002834 transmittance Methods 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
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- 210000002858 crystal cell Anatomy 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical group 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention provides a kind of manufacturing method of array substrate, comprising: is sequentially depositing metal layer and layer of ito on the glass substrate, and carries out first time photoetching, to form the first layer structure for including grid and storage capacitor electrode；It is sequentially depositing gate insulating layer, indium gallium zinc oxide IGZO semiconductor layer and source-drain electrode metal layer in first layer structure, and carries out second of photoetching, to form the second layer structure for including silicon island figure, source electrode and drain electrode；Passivation layer and planarization layer are sequentially formed in second layer structure, so that IGZO semiconductor layer is formed conductor IGZO during forming passivation layer, and carry out third time photoetching to form conductive via；Transparent conductive film is deposited on planarization layer, and carries out fourth lithography to form pixel electrode, and connected pixel electrode and conductive via.The present invention provides a kind of manufacturing method of array substrate, it is only necessary to which the production of the array substrate with high transmittance pixel can be realized in four optical cover process sequence.
Description
Technical field
The present invention relates to field of liquid crystal display more particularly to a kind of manufacturing methods of array substrate.
Background technique
The transmitance of liquid crystal display panel plays particularly important effect to the whole display performance of liquid crystal display panel, thoroughly
Cross that rate is higher, liquid crystal display panel can reality two degrees it is higher, the brightness of backlight can do it is lower, to reduce product
Cost, therefore the transmitance for how promoting liquid crystal display panel is a very important research topic.
Fig. 1 is the route design diagram for the array substrate that the prior art provides, and Fig. 2 is that array substrate shown in FIG. 1 exists
The cross-sectional view in the direction A-A ', referring to fig. 1 and fig. 2, the manufacturing method for the array substrate that the prior art provides include six pieces of light
Cover process sequence, comprising: step 1: deposited metal layer over the glass substrate 100, carries out first time photoetching, form 101 He of grid
Storage capacitor electrode 102；Second step is sequentially depositing gate insulating layer 103 and indium gallium zinc oxide IGZO semiconductor layer 104, into
Second of photoetching of row, has formed silicon island figure；Third step, deposition-etch barrier layer 105, and carry out third time photoetching；4th step,
Sedimentary origin drain metal layer, and fourth lithography is carried out, to form source electrode 106 and drain electrode 107；5th step, deposit passivation layer 108
With planarization layer 109, and carry out the 5th photoetching, to form conductive via；6th step deposits transparent conductive film, and carries out
6th photoetching is connected to figure with form pixel electrode 110 and conductive via and pixel electrode.
Six pieces of optical cover process techniques that the prior art provides, although the saturating of pixel electrode and storage capacitor electrode may be implemented
Brightization and high transmittance, but its complex process, cost of manufacture are high.
Summary of the invention
The present invention provides a kind of manufacturing method of array substrate, it is only necessary to which four optical cover process sequence, which can be realized, has height thoroughly
Cross the production of the array substrate of rate pixel.
The present invention provides a kind of manufacturing method of array substrate, comprising: is sequentially depositing metal layer and oxygen on the glass substrate
Change indium tin ITO layer, and carry out first time photoetching, to form include grid and storage capacitor electrode the on the glass substrate
One layer of structure；
Gate insulating layer, indium gallium zinc oxide IGZO semiconductor layer and source-drain electrode are sequentially depositing in the first layer structure
Metal layer, and second of photoetching is carried out, to form the second layer structure for including silicon island figure, source electrode and drain electrode；
Passivation layer and planarization layer are sequentially formed in the second layer structure, and during forming the passivation layer
So that the IGZO semiconductor layer is formed conductor IGZO, and carry out third time photoetching, to form conductive via；
Transparent conductive film is deposited on the planarization layer, and carries out fourth lithography, to form pixel electrode, and even
Lead to the pixel electrode and the conductive via.
The manufacturing method of array substrate provided by the invention will form grid using half-tone mask technique in the prior art
Pole insulating film, etching barrier layer and source electrode, drain electrode three optical cover process, be reduced to an optical cover process, reduce process, pole
Big has saved manufacturing cost.Further, storage capacitor electrode replaces metal in the prior art using transparent conductive film
Layer can effectively improve the aperture opening ratio of pixel, and then improve the transmitance of pixel entirety.In addition, during using passivation layer deposition
Be filled with hydrogen, can be convenient by IGZO semiconductor layer conductor.
The manufacturing method of array substrate as described above, the storage capacitor electrode includes the metal layer and the ITO
Layer, the linewidth of the ITO pattern are greater than the width of the metal layer, and at least partly storage capacitance is formed in the ITO layer
Between the pixel electrode.
The manufacturing method of array substrate as described above, the storage capacitance are also formed in the conductor IGZO and described
Between pixel electrode.
The manufacturing method of array substrate as described above, before the sedimentary origin drain metal layer, further includes: deposition-etch
Barrier layer, the etching barrier layer is for stopping the IGZO semiconductor layer to be etched when etching the source-drain electrode metal.
The manufacturing method of array substrate as described above, the first time photoetching and second of photoetching pass through half color
Mask process is adjusted to carry out.
The manufacturing method of array substrate as described above, it is described to make the IGZO half during forming the passivation layer
Conductor layer forms conductor IGZO and specifically includes: leading to hydrogen during depositing the passivation layer, so that the IGZO is partly led
Body layer conductorization forms conductor IGZO.
The manufacturing method of array substrate as described above, the formation IGZO semiconductor layer specifically include: being splashed using magnetic control
The mode of penetrating forms the IGZO semiconductor layer.
The manufacturing method of array substrate as described above, the deposit passivation layer specifically include: the source electrode, drain electrode with
And deposited silicon nitride layer on the IGZO semiconductor layer not covered by the source electrode and drain electrode.
The manufacturing method of array substrate as described above, the formation conductive via specifically include: above the drain electrode
The passivation layer and the planarization layer on form the conductive via.
The manufacturing method of array substrate as described above, the pixel electrode are tin indium oxide ito thin film.
The manufacturing method of array substrate provided in an embodiment of the present invention will in the prior art using half-tone mask technique
Three optical cover process for forming gate insulating film, etching barrier layer and source electrode, drain electrode, are reduced to an optical cover process, reduce
Process has greatly saved manufacturing cost.Further, storage capacitor electrode is replaced in the prior art using transparent conductive film
Metal layer, the aperture opening ratio of pixel can be effectively improved, and then improve the transmitance of pixel entirety.In addition, utilizing passivation layer deposition
Be filled with hydrogen in the process, can be convenient by IGZO semiconductor layer conductor.
Detailed description of the invention
In order to illustrate more clearly of the present invention or the technical solution of the prior art, embodiment or the prior art will be retouched below
Attached drawing needed in stating is briefly described, it should be apparent that, the accompanying drawings in the following description is of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the route design diagram for the array substrate that the prior art provides；
Fig. 2 is cross-sectional view of the array substrate shown in FIG. 1 in the direction A-A '；
Fig. 3 is the route design diagram of array substrate provided in an embodiment of the present invention；
Fig. 4 is cross-sectional view of the array substrate shown in Fig. 3 in the direction A-A '；
Fig. 5 is the flow chart of the manufacturing method of array substrate provided in an embodiment of the present invention.
Appended drawing reference:
100- glass substrate
101- grid
102- storage capacitor electrode
1021- metal layer
1022-ITO layers
103- gate insulating layer
104-IGZO semiconductor layer
105- etching barrier layer
106- source electrode
107- drain electrode
108- passivation layer
109- planarization layer
110- pixel electrode
111- conductor IGZO
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the attached drawing in the present invention, to this
Technical solution in invention is clearly and completely described, it is clear that and described embodiments are some of the embodiments of the present invention,
Instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative labor
Every other embodiment obtained under the premise of dynamic, shall fall within the protection scope of the present invention.
It should be noted that traditional liquid crystal display panel is by one sheet of film transistor (TFT) array substrate (Thin Film
Transistor Array Substrate, abbreviation TFT Array Substrate) and a piece of color membrane substrates (Color
Filter Substrate, abbreviation CF Substrate) it is bonded, pixel is formed in array substrate and color membrane substrates respectively
Electrode and public electrode, and liquid crystal is poured between array substrate and color membrane substrates, its working principle is that by pixel electrode
Apply driving voltage between public electrode, is controlled in liquid crystal layer using the electric field formed between pixel electrode and public click
Liquid crystal molecule rotation, by the light refraction of backlight module come out generate picture.
Further, thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) liquid crystal display is mainly by backlight
Source, liquid crystal display panel and driving circuit composition.In entire liquid crystal display die set, the light of a polarised light is made of two polaroids
System, in conjunction with liquid crystal optical anisotropy and electrical anisotropy and thin film transistor (TFT) TFT to driving liquid crystal telecommunications
Number on-off action, modulating action is played to the light by backlight incidence into liquid crystal cell.
The basic composition of thin film transistor (TFT) TFT is located at half including double layer of metal, dielectric layers, one layer of active layer and one layer
Ohmic contact layer between conductor and metal layer.The electrode that double layer of metal is constituted be scanning signal metal electrode sum number respectively it is believed that
Number metal electrode, dielectric layers respectively refer to be located at the insulating layer (also referred to as gate insulating layer) below active layer and are located at active layer
The doped layer of the insulating layer (also referred to as passivation layer, PVX) of top, active layer and Ohmic contact effect leads in thin film transistor (TFT) together
It is often island-like shape, therefore also referred to as active island or silicon island.
Pixel region is provided with grid, source electrode, drain electrode, pixel electrode and storage capacitor electrode, the grid and the scanning
Line electrical connection, the source electrode are electrically connected with the data line, and the drain electrode is electrically connected with the pixel electrode.Generally, in battle array
In the manufacturing process of column substrate, scan line, grid and storage capacitor electrode are formed simultaneously, and data line and source electrode, drain shape simultaneously
At.
Mask (Mask), also referred to as light shield (Photo Mask), are figure mother matrixs used in photoetching process, are by not
The shading film (crome metal) of light transmission forms mask graph on the transparent substrate, passes through photoetching process (Photolithography)
It transfers the graphic on the film of glass substrate.(Exposure) process of exposure is exactly ultraviolet light (Ultraviolet) by covering
Template irradiation light photoresist (Photo Resist), makes the figure on mask be transferred to the process on photoresist.
In array engineering, photoresist plays the role of mask, i.e., the photoetching offset plate figure formed by exposure protects it
Following film is not etched in etching technics, finally removes photoresist again, and the figure on mask is transferred to film
Upper, this process is known as photoetching.It in each photoetching process, is all coated with, exposure, development, carves by film deposition, photoresist
Erosion and these main technological steps of photoresist lift off.
Below with reference to the accompanying drawings and in conjunction with specific embodiments the present invention is described.
Fig. 3 is the route design diagram of array substrate provided in an embodiment of the present invention, and Fig. 4 is array base shown in Fig. 3
Plate is in the cross-sectional view in the direction A-A ', and Fig. 5 is the flow chart of the manufacturing method of array substrate provided in an embodiment of the present invention, with reference to figure
3, shown in Fig. 4 and Fig. 5, the present invention provides a kind of manufacturing method of array substrate, comprising:
S101, it is sequentially depositing metal layer 1021 and layer of ito 1022 over the glass substrate 100, and carries out first
Secondary photoetching, to form the first layer structure including grid 101 and storage capacitor electrode 102 over the glass substrate 100.
Wherein, first time photoetching is carried out by half-tone mask technique.It is understood that time of lithographic process steps
Number, had not only influenced the production capacity of panel, but also affect the manufacturing cost of panel, therefore the fewer the number of photoetching process the better.Wherein, half
Tone mask technique (Half-tone Mask, abbreviation HTM) is not exclusively to be exposed photoresist using the semi-permeable membrane on mask
Technique.The different region of setting transmitance, then can be formed simultaneously grid 101 and storage capacitance after exposing on setting mask
Electrode 102.
Specifically, metal layer 1021 is used to form grid 101 and storage capacitor electrode 102, and layer of ito 1022 is set
It sets above metal layer 1021, is used to form storage capacitor electrode 102.Since storage capacitor electrode 102 includes metal layer and ITO
Layer, the linewidth of ITO pattern are greater than the width of metal layer, and storage capacitance is at least formed at ITO layer 1022 and pixel electrode 110
Between.In addition, storage capacitance is also formed between conductor IGZO111 and pixel electrode 110.
Since the leakage current of liquid crystal cell and TFT can cause the decline of pixel electrode voltage, and then influence liquid crystal display panel
The display characteristics such as contrast.In order to compensate for the pixel electrode voltage of decline, storage capacitance can be set in array substrate.It deposits
Storage holds, the voltage retention of a common raising liquid crystal cell in parallel with liquid crystal capacitance, the load capacity of TFT for liquid crystal capacitance with deposit
The sum of storage appearance.
Storage capacitor electrode is traditionally arranged to be metal layer storage electrode, and storage capacitance depends mainly on the size of storage electricity
Hold the width of electrode, increase the width of storage capacitor electrode, although being conducive to improve voltage retention, but also increases simultaneously
The load capacity of TFT, and metal shading-area is increased, it can reduce the aperture opening ratio of pixel.And in the present embodiment, use ITO
1022 and conductor IGZO111 of layer is as storage capacitor electrode, since ITO layer 1022 and conductor IGZO111 are transparent lead
Problem of Shading is not present in conductive film, and this improves the aperture opening ratios of pixel, and then improve the transmitance of pixel entirety.
Preferably, storage capacitor electrode 102 is indium gallium zinc oxide IGZO.IGZO thin-film material is almost for visible light
Transparent, therefore, on the aperture opening ratio of pixel without influence.In the manufacturing process of array substrate, when passivation layer PAS is formed, fill
Enter hydrogen, make IGZO by semiconductor variable at conductor with can be convenient, to improve the electric conductivity of storage capacitor electrode 102.
Gate metal layer requires good conductive characteristic and is easy to etch as much as possible, optionally, gate metal layer
For Mo.
S102, gate insulating layer 103, indium gallium zinc oxide IGZO semiconductor layer 104 are sequentially depositing in first layer structure
With source-drain electrode metal layer, and carry out second of photoetching, with formed include silicon island figure, source electrode 106 and drain 107 second layer knot
Structure.
Wherein, IGZO is that a kind of amorphous oxides containing indium, gallium and zinc is mixed wherein using zinc oxide material as matrix
Conductor oxidate IGZO can be formed by entering indium and gallium both transiting group metal elements, and carrier mobility is amorphous silicon
20-30 times, TFT can be greatly improved to the charge-discharge velocity of pixel electrode 500, the response speed of pixel is improved, realize faster
Refresh rate, while response also substantially increases the line scanning rate of pixel faster.
Compared with the prior art, with the electronics of higher concentration in IGZO film, so in the manufacturing process of TFT,
Can directly be contacted with source-drain electrode metal layer, without in the prior art equally increase by one layer of heavy doping contact layer.
On the basis of the above embodiments, before the sedimentary origin drain metal layer, further includes: deposition-etch barrier layer
105 (Etching-Stop-Layer, abbreviation ESL), etching barrier layer 105 is for stopping IGZO semiconductor layer 104 in etching source
It is etched when drain metal.
It is also very sensitive in meeting for back surface to carrier due to the very thin thickness of IGZO semiconductor layer 104, so, it carves
When losing the effect on barrier layer 105 in addition to being blocked in etching source-drain electrode metal, etching liquid is thinned to IGZO semiconductor layer 104, also
One effect is the back surface for being passivated IGZO semiconductor layer 104, reduces the carrier probability compound in back surface.Usually etching
Barrier layer 105 selects SiOXFilm or Al2O3Film.
Wherein, it forms IGZO semiconductor layer to specifically include: IGZO semiconductor layer is formed using magnetron sputtering mode.Magnetic control splashes
Penetrating mode is for depositing ITO and metallic film in other techniques, and the deposition of IGZO semiconductor layer can also use
Magnetron sputtering technique can be mutually compatible with existing panel fabrication process well without increasing additional process equipment.
Magnetron sputtering is to increase a magnetic field near the target back side on the basis of second level d.c. sputtering, sputtered
Cheng Zhong, electronics are spinned movement by the effect of electric and magnetic fields, substantially increase the stroke of electronics in this way, increase the production of ionization
Volume has the feature good, reproducible and high rate of film build at film uniformity.
In the present embodiment, second of photoetching is carried out by half-tone mask technique.Transmitance is set on setting mask
Different regions can be formed simultaneously gate insulating layer 103, indium gallium zinc oxide IGZO semiconductor layer 104 and source and drain after then exposing
Pole metal layer.
Specifically, gate insulating layer 103 requires biggish dielectric constant, with guarantee grid voltage to TFT have compared with
Strong ability of regulation and control guarantees the switching speed of device.It it is also desirable to have biggish forbidden bandwidth, to guarantee not influencing the saturating of light
It crosses, guarantees there is biggish band rank between gate insulating layer 103 and the conduction band bottom of IGZO semiconductor layer 104, got over to increase electronics
The difficulty that potential barrier reaches gate metal layer is crossed, the generation of grid current and leakage current is reduced.
S103, passivation layer 108 and planarization layer 109 are sequentially formed in second layer structure, and forming passivation layer 108
So that IGZO semiconductor layer is formed conductor IGZO111 in the process, and carry out third time photoetching, to form conductive via.
It is described sequentially form passivation layer 108, conductor IGZO111 is specifically included: during deposit passivation layer 108 lead to
Hydrogen, so that 104 conductorization of IGZO semiconductor layer forms conductor IGZO111.In the manufacturing process of array substrate, passivation layer
When 108 formation, it is filled with hydrogen, makes IGZO by semiconductor variable at conductor with can be convenient.
The deposit passivation layer 108 specifically includes: not being covered in source electrode 106, drain electrode 107 and by source electrode 106 and drain electrode 107
Deposited silicon nitride layer on the IGZO semiconductor layer 104 of lid.
Wherein, the effect of passivation layer 108 is insulating layer, also referred to as PAS layers, generally SiO2/SiNx film layer；Planarization layer
109 also referred to as JAS layers, generally acrylic material.
The conductive via that formed specifically includes: the passivation layer 108 and the planarization above the drain electrode 107
The conductive via (not shown) is formed on layer 109.Conductive via, also referred to as drain electrode pixel contact hole, in passivation layer
108 and planarization layer 109 on formed, for making drain electrode 107 contact connection with pixel electrode 110.
S104, transparent conductive film is deposited on planarization layer 109, and carry out fourth lithography, to form pixel electrode
110, and connected pixel electrode 110 and conductive via.
Pixel electrode 110 is connected with conductive via, and conductive via is formed in 108 peace of passivation layer of 107 top of drain electrode
On smooth layer 109, and then it can realize that pixel electrode 110 is connected to drain electrode 107.
Wherein, pixel electrode 110 is tin indium oxide ito thin film.Tin indium oxide (Indium Tin Oxide, abbreviation ITO)
It is a kind of N-type semiconductor material, the electric conductivity with semiconductor.The characteristic of ito thin film includes higher conductive capability, relatively strong
Light reproducibility and light transmission rate, stronger chemical stability, thermal stability, good etching homogeneity and suitable surface shape
Shape.
The manufacturing method of array substrate as described above, can make to form array substrate, refering to what is shown in Fig. 3, array substrate
Including forming scan line and data line on the glass substrate, pixel electricity is formed in the pixel region that scan line and data line limit
Pole and thin film transistor (TFT), thin film transistor (TFT) include the grid being connected with scan line, the source electrode and pixel electrode that are connected with data line
The semiconductor layer of the thin film transistor (TFT) formed between connected drain electrode and source electrode and drain electrode.Be also formed in pixel region with
Pixel electrode constitutes the storage electrode of storage capacitance together, wherein storage electrode is metal oxide IGZO and ITO, and film is brilliant
The semiconductor layer of body pipe is IGZO, pixel electrode ITO.
Wherein, glass substrate 100 is the most basic material of Thin Film Transistor-LCD, and quality directly influences
The qualification rate of entire engineering, glass substrate 100 require higher light transmission rate, stronger heat resistance, certain acid resistance
And alkali resistance, enough planarizations etc..
The manufacturing method of array substrate provided in an embodiment of the present invention will in the prior art using half-tone mask technique
Three optical cover process for forming gate insulating film, etching barrier layer and source electrode, drain electrode, are reduced to an optical cover process, reduce
Process has greatly saved manufacturing cost.Further, storage capacitor electrode is replaced in the prior art using transparent conductive film
Metal layer, the aperture opening ratio of pixel can be effectively improved, and then improve the transmitance of pixel entirety.In addition, utilizing passivation layer deposition
Be filled with hydrogen in the process, can be convenient by IGZO semiconductor layer conductor.
In the description of the present invention, it is to be understood that, used term " center ", " length ", " width ", " thickness
Degree ", " top ", " bottom end ", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outside" " axis
To ", the indicating positions such as " circumferential direction " or positional relationship be to be based on the orientation or positional relationship shown in the drawings, be merely for convenience of describing
The present invention and simplified description, rather than the position of indication or suggestion meaning or original part must have a particular orientation, with specific
Construction and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is at least two, such as two
It is a, three etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
It shall be understood in a broad sense, such as may be a fixed connection, may be a detachable connection, or be integrally formed；It can be mechanical connection,
It is also possible to be electrically connected or can communicate with each other；It can be directly connected, can also indirectly connected through an intermediary, it can be with
Make the connection inside two elements or the interaction relationship of two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature "upper" or "lower"
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature includes the first spy above the second feature " above ", " above " and " above "
Sign is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " include that fisrt feature is directly below and diagonally below the second feature, or is merely representative of
First feature horizontal height is less than second feature.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (9)
1. a kind of manufacturing method of array substrate characterized by comprising
It is sequentially depositing metal layer and layer of ito on the glass substrate, and carries out first time photoetching, so that the metal layer
Grid and storage capacitor electrode are formed, the layer of ito is located at the metal layer for being used to form the storage capacitor electrode
Top；
It is sequentially depositing gate insulating layer, indium gallium zinc oxide IGZO semiconductor layer and source-drain electrode metal layer, and carries out second of light
It carves, while forming active island, to make the source-drain electrode metal layer form source electrode and drain electrode, the IGZO semiconductor layer includes
Positioned at the first part in the array switch region where source electrode and drain electrode and positioned at the second part of pixel region, the IGZO half
The first part of conductor layer forms the active island；
Passivation layer and planarization layer are sequentially formed, and makes second positioned at the pixel region during forming the passivation layer
The partial IGZO semiconductor layer forms conductor IGZO, then carries out third time photoetching, in the passivation layer and planarization
Conductive via is formed on layer；
Transparent conductive film is deposited on the planarization layer, and carries out fourth lithography, so that the transparent conductive film shape
Pixel electrode, and it is connected to the pixel electrode and the conductive via, the conductive via is for being connected to the pixel electrode
With the drain electrode；
Wherein, the conductor IGZO is used for and the pixel electrode forms part storage capacitance.
2. the manufacturing method of array substrate according to claim 1, which is characterized in that the storage capacitor electrode includes institute
Metal layer and the ITO layer are stated, the linewidth of the pattern of the ITO layer is greater than the width of the metal layer, at least partly deposits
Storage appearance is formed between the ITO layer and the pixel electrode.
3. the manufacturing method of array substrate according to claim 1, which is characterized in that the sedimentary origin drain metal layer it
Before, further includes: deposition-etch barrier layer, the etching barrier layer is for stopping the IGZO semiconductor layer etching the source and drain
It is etched when the metal of pole.
4. the manufacturing method of array substrate according to claim 3, which is characterized in that the first time photoetching and described
Secondary photoetching passes through half-tone mask technique and carries out.
5. the manufacturing method of array substrate according to claim 1, which is characterized in that described to form the passivation layer
Make the IGZO semiconductor layer of the second part positioned at the pixel region form conductor IGZO in the process to specifically include: in shape
Lead to hydrogen during at the passivation layer, so that the IGZO semiconductor layer conductor forms the conductor IGZO.
6. the manufacturing method of array substrate according to claim 5, which is characterized in that the deposition indium gallium zinc oxide
IGZO semiconductor layer specifically includes: forming the IGZO semiconductor layer using magnetron sputtering mode.
7. the manufacturing method of array substrate according to claim 1, which is characterized in that the formation passivation layer specifically wraps
It includes: deposited silicon nitride layer on the IGZO semiconductor layer not covered in the source electrode, drain electrode and by the source electrode and drain electrode.
8. the manufacturing method of array substrate according to claim 1, which is characterized in that the formation conductive via specifically wraps
It includes: forming the conductive via on the passivation layer and the planarization layer above the drain electrode.
9. the manufacturing method of array substrate according to claim 1, which is characterized in that the pixel electrode is tin indium oxide
Ito thin film.
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| CN1702530A (en) * | 2004-05-27 | 2005-11-30 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN105914183A (en) * | 2016-06-22 | 2016-08-31 | 深圳市华星光电技术有限公司 | TFT (Thin Film Transistor) substrate manufacturing method |
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| CN1702530A (en) * | 2004-05-27 | 2005-11-30 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN105914183A (en) * | 2016-06-22 | 2016-08-31 | 深圳市华星光电技术有限公司 | TFT (Thin Film Transistor) substrate manufacturing method |
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