CN109828404A - A kind of array substrate and preparation method thereof, display panel - Google Patents
A kind of array substrate and preparation method thereof, display panel Download PDFInfo
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- CN109828404A CN109828404A CN201910101240.3A CN201910101240A CN109828404A CN 109828404 A CN109828404 A CN 109828404A CN 201910101240 A CN201910101240 A CN 201910101240A CN 109828404 A CN109828404 A CN 109828404A
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Abstract
The invention discloses a kind of array substrates and preparation method thereof, display panel.The array substrate includes the first substrate and the grid line, data line and the thin film transistor (TFT) that are arranged in first substrate, the grid line and the data line, which intersect, limits multiple pixel regions, the thin film transistor (TFT) is corresponding with the pixel region, and array substrate further includes the first layer of photonic crystals being arranged in first substrate for projecting the light for being irradiated to the grid line, the data line and the thin film transistor (TFT) region towards the pixel region.The array substrate of this structure, the light for being irradiated to lighttight grid line, data line and thin film transistor (TFT) projects under the action of the first layer of photonic crystals towards pixel region, and then array substrate is penetrated from pixel region, to reduce the light losing for being irradiated to grid line, data line and thin film transistor (TFT) region, the utilization rate for improving light improves the light transmittance of array substrate.
Description
Technical field
The present invention relates to field of display technology, and in particular to a kind of array substrate and preparation method thereof, display panel.
Background technique
There have been development at full speed in FPD mode of the liquid crystal display device as current mainstream, nearly more than ten years,
Have many advantages, such as light, thin, low energy consumption, is widely used in the modernization such as TV, computer, mobile phone, digital camera information and sets
Standby, especially in large-sized liquid crystal display, development is quite mature.In liquid crystal display device, the light that backlight issues,
Entered by lower polarizing film, after each layer, is emitted again from upper polarizer, the brightness for the light being emitted at this time is only equivalent to incident light
7%~8% or lower.One reason for this is that in array substrate lighttight metal layer (including grid line, data line,
Gate electrode and source-drain electrode etc.) stop a part of light to penetrate, so that the light transmittance of array substrate is about below 60%.Such as
What improves the light transmittance of liquid crystal display panel, is the larger problem that liquid crystal display industry faces always.
In the prior art, there are mainly three types of the methods for promoting liquid crystal display panel light transmittance: first, improve the bright of backlight
Degree to improve light transmission capacity and the brightness of liquid crystal display panel, and then improves the display quality of liquid crystal display panel, but this method
It will increase the power consumption of display device；Second, the aperture opening ratio of array substrate is improved to promote the light transmittance of display panel, currently, this
Kind method has almost accomplished that the limit, the promotion effect of light transmittance are limited；Third improves the light transmission of display panel material therefor
Rate, to improve the integral light-transmitting rate of display panel, but such method is limited to the development of a variety of materials, based on current material,
The light transmittance for adopting this method raising display panel is difficult to realize.
Summary of the invention
The purpose of the embodiment of the present invention is that a kind of array substrate and preparation method thereof, display panel are provided, to solve to show
The low problem of panel light transmission rate.
In order to solve the above-mentioned technical problem, the embodiment of the present invention provides a kind of array substrate, including the first substrate and setting
Grid line, data line and thin film transistor (TFT) in first substrate, the grid line and the data line intersect and limit
Multiple pixel regions, the thin film transistor (TFT) is corresponding with the pixel region, and array substrate further includes being arranged in first base
For making to be irradiated to the light of the grid line, the data line and the thin film transistor (TFT) region towards the pixel on bottom
The first layer of photonic crystals that region is projected.
Optionally, first layer of photonic crystals has incident side and light emission side, and the light emission side has multiple grooves.
Optionally, multiple grooves are evenly arranged, and the depth of the groove is less than or equal to 120nm, two neighboring institute
Stating the spacing between groove is 350nm~600nm.
Optionally, the material of first layer of photonic crystals include the gallium nitride of p-type doping, n-type doping gallium nitride and
At least one of indium tin oxide.
Optionally, the orthographic projection of the grid line, data line and thin film transistor (TFT) in first substrate is respectively positioned on described
First layer of photonic crystals is within the scope of the orthographic projection in first substrate.
Optionally, first layer of photonic crystals is arranged between first substrate and the thin film transistor (TFT).
Optionally, the thin film transistor (TFT) is bottom gate thin film transistor, and the thin film transistor (TFT) includes being located at described the
Gate electrode in one substrate, the active layer on the gate electrode and source electrode and electric leakage on the active layer
Pole, first layer of photonic crystals is between the gate electrode and first substrate.
Optionally, the array substrate further includes being arranged between first layer of photonic crystals and the thin film transistor (TFT)
Flatness layer.
Optionally, the array substrate further includes the pixel electrode being arranged on the thin film transistor (TFT), is arranged described
Interlayer insulating film on pixel electrode and the public electrode being arranged on the interlayer insulating film, the array substrate further include
The public electrode lead for being arranged with the grid line same layer and being electrically connected with the public electrode further includes being arranged in the common electrical
Between pole lead and first substrate and for making the light for being irradiated to public electrode lead region described in
The second layer of photonic crystals that pixel region projects.
Optionally, orthographic projection of the public electrode lead in first substrate is located at second layer of photonic crystals
Within the scope of the orthographic projection in first substrate.
In order to solve the above-mentioned technical problem, the embodiment of the present invention also provides a kind of preparation method of array substrate, comprising:
Form the first layer of photonic crystals, grid line, data line and thin film transistor (TFT) in the first substrate, the grid line and described
Data line, which intersects, limits multiple pixel regions, and the thin film transistor (TFT) is corresponding with the pixel region, first light
Sub- crystal layer is used to make to be irradiated to the light of the grid line, the data line and the thin film transistor (TFT) region described in
Pixel region projects.
Optionally, described that the first layer of photonic crystals, grid line, data line and thin film transistor (TFT), packet are formed in the first substrate
It includes:
The first layer of photonic crystals is formed in the first substrate, the light emission side of first layer of photonic crystals has multiple recessed
Slot；
Grid line, data line and thin film transistor (TFT) are formed on first layer of photonic crystals.
It is optionally, described that the first layer of photonic crystals is formed in the first substrate, comprising:
Photon crystal film is formed in the first substrate；
A layer photoresist is coated on the photon crystal film；
Ladder exposure is carried out to photoresist using intermediate tone mask or gray level mask and is developed, in the first layer of photonic crystals
Non-recessed position forms unexposed area, retains photoresist, forms part exposure region in the groove location of the first layer of photonic crystals
Domain retains a part of photoresist, forms complete exposure area, unglazed photoresist in other positions；
The photon crystal film of complete exposure area is performed etching；
Ashing processing is carried out to photoresist, removes the photoresist of partial exposure area, unexposed area retains a part of light
Photoresist；
The photon crystal film of partial exposure area is performed etching, the pattern of the first layer of photonic crystals is formed.
It is optionally, described that grid line, data line and thin film transistor (TFT) are formed on first layer of photonic crystals, comprising:
Flatness layer is formed on first layer of photonic crystals；
Grid line, data line and thin film transistor (TFT) are formed on the flat laye.
In order to solve the above-mentioned technical problem, the embodiment of the present invention also provides a kind of display panel, including above-described battle array
Column substrate, further includes the color membrane substrates with array substrate pairing setting, and the color membrane substrates exist including the second substrate, setting
The color film towards the array substrate side of second substrate and the black matrix that is arranged between the adjacent color film, institute
It states black matrix and is located at positive throwing of first layer of photonic crystals in first substrate in the orthographic projection in first substrate
Within the scope of shadow.
The array substrate of the embodiment of the present invention is provided with and grid line, data line and thin film transistor (TFT) institute in the first substrate
In corresponding first layer of photonic crystals in region, the first layer of photonic crystals is for making to be irradiated to grid line, data line and thin film transistor (TFT)
The light of region is projected towards pixel region, thus, it is irradiated to the light of lighttight grid line, data line and thin film transistor (TFT)
Line projects under the action of the first layer of photonic crystals towards pixel region, and therefore, this some light can be penetrated from pixel region
Array substrate, which reduces the light losings for being irradiated to grid line, data line and thin film transistor (TFT) region, improve light
Utilization rate, improve the light transmittance of array substrate.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the overlooking structure diagram of first embodiment of the invention array substrate；
Fig. 2 is the cross section structure schematic diagram of first embodiment of the invention array substrate；
Fig. 3 is the cross section structure schematic diagram of the first layer of photonic crystals；
Fig. 4 a is the structural schematic diagram after etching for the first time during forming the first layer of photonic crystals；
Fig. 4 b is the structural schematic diagram during forming the first layer of photonic crystals after photoresist ashing；
Fig. 4 c is the structural schematic diagram after the first layer of photonic crystals of formation of first embodiment of the invention array substrate；
Fig. 5 is the structural schematic diagram of first embodiment of the invention array substrate formed after gate electrode；
Fig. 6 is the structural schematic diagram of first embodiment of the invention array substrate formed after active layer；
Fig. 7 is the structural schematic diagram after the formation source/drain electrode of first embodiment of the invention array substrate；
Fig. 8 is the structural schematic diagram of first embodiment of the invention array substrate formed after pixel electrode；
Fig. 9 is the structural schematic diagram of first embodiment of the invention array substrate formed after interlayer insulating film；
Figure 10 is the structural schematic diagram of second embodiment of the invention display panel.
Description of symbols:
100-array substrates；101-grid lines；103-pixel regions；
121-gate electrodes；122-active layers；123-source electrodes；
124-drain electrodes；200-color membrane substrates；300-liquid crystal layers；
400-sealants；11-the first substrate；12-thin film transistor (TFT)s；
13-flatness layers；14-pixel electrodes；15-interlayer insulating films；
16-public electrodes；17-public electrode leads；18-gate insulation layers；
19-first alignment layers；21-the second substrate；22-color films；
23-black matrix；24-second orientation layers；41-the first layer of photonic crystals；
42-the second layer of photonic crystals；411-incident sides；412-light emission sides；
413-grooves；102-data lines.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Technology contents of the invention will be discussed in detail by specific embodiment below.
First embodiment:
Fig. 1 is the overlooking structure diagram of first embodiment of the invention array substrate, and Fig. 2 is first embodiment of the invention battle array
The cross section structure schematic diagram of column substrate.As depicted in figs. 1 and 2, array substrate 100 includes the first substrate 11 and is arranged in the first base
Grid line 101 and data line 102 on bottom 11.Grid line 101 and data line 102 be mutually perpendicular to intersect limit it is multiple arranged in arrays
Pixel region 103.Array substrate 100 further includes setting in the first substrate 11, and one-to-one thin with pixel region 103
Film transistor 12.Array substrate 100 further includes the first layer of photonic crystals 41 being arranged in the first substrate 11, the first photonic crystal
The region of layer 41 is corresponding with the region of grid line 101, data line 102 and thin film transistor (TFT) 12, the first photonic crystal
Layer 41 is for making to be irradiated to the light of 12 region of grid line 101, data line 102 and thin film transistor (TFT) towards pixel region 103
It projects.
It is understood that the light for being irradiated to pixel region 103 can be directed through the injection of pixel region 103, irradiation
To 12 region of grid line 101, data line 102 and thin film transistor (TFT) light since grid line 101, data line 102 cannot be penetrated
It projects and loses with thin film transistor (TFT) 12.The array substrate of the embodiment of the present invention, is provided with and grid line in the first substrate 11
101, the first layer of photonic crystals 41 corresponding with 12 region of thin film transistor (TFT) of data line 102, the first layer of photonic crystals 41 are used
It is projected in the light for making to be irradiated to 12 region of grid line 101, data line 102 and thin film transistor (TFT) towards pixel region 103, from
And it is irradiated to work of the light in the first layer of photonic crystals 41 of lighttight grid line 101, data line 102 and thin film transistor (TFT) 12
It is projected with lower towards pixel region 103, thus, this some light can penetrate array substrate from pixel region 103, thus subtract
Lack the light losing for being irradiated to 12 region of grid line 101, data line 102 and thin film transistor (TFT), improve the utilization rate of light,
Improve the light transmittance of array substrate.
Fig. 3 is the cross section structure schematic diagram of the first layer of photonic crystals.As shown in figure 3, the first layer of photonic crystals 41 include into
Light side 411 and light emission side 412 have multiple grooves 413 in light emission side 412.First layer of photonic crystals 41 of this structure, it is incident
After light is from the first layer of photonic crystals 41 of entrance of incident side 411, diffraction, the biography of light occur in the first layer of photonic crystals 41
Direction is broadcast to be changed, so that the corresponding emergent ray of incident ray is projected towards pixel region 103, in turn,
Emergent ray can penetrate array substrate from pixel region 103.
As shown in figure 3, in the present embodiment, multiple grooves 413 are evenly arranged in light emission side 412, the depth of groove 413
H is less than or equal to 120nm, and the spacing d between two neighboring groove 413 is 350nm~600nm.The groove 413 of this structure,
It is easy production, meets the production application of the first layer of photonic crystals 41.In one embodiment, the width w and phase of groove 413
The ratio of spacing d between adjacent two grooves 413 is 0.6~0.8.The groove of this structure can make light in the first light
Better diffracting effect is obtained in sub- crystal layer, is guaranteed that emergent ray can be projected towards pixel region, is further improved
The utilization rate of light.
The material of first layer of photonic crystals 41 may include the gallium nitride of the gallium nitride (p-GaN) of p-type doping, n-type doping
(n-GaN) and at least one of indium tin oxide.
It is easily understood that multiple grooves can be multiple strip grooves extended in the same direction, or setting
Multiple keyhole-shaped recess in matrix arrangement in light emission side, cut as long as the first layer of photonic crystals as shown in Figure 3 can be formed
Face belongs to scope of the claimed of the embodiment of the present invention.
In order to enable the light being irradiated on grid line 101, data line 102 and thin film transistor (TFT) 12 can be in the first photon
It is projected under the action of crystal layer 41 towards pixel region 103, in the present embodiment, grid line 101, data line 102 and film crystal
Pipe 12 is respectively positioned on the first layer of photonic crystals 41 within the scope of the orthographic projection in the first substrate 11 in the orthographic projection in the first substrate 11.
To be irradiated to the light of 12 region of grid line 101, data line 102 and thin film transistor (TFT) in the first layer of photonic crystals 41
It under effect, is projected towards pixel region 103, and penetrates array substrate from pixel region 103, thus, further reduce light
Line loss is lost, and the light transmittance of array substrate is further improved.
As shown in Fig. 2, thin film transistor (TFT) 12 includes gate electrode 121, active layer 124, source electrode 122 and drain electrode 123.It is logical
Often, grid line 101 is located on the same floor with gate electrode 121, and data line 102 is located on the same floor with source/drain electrode, in order to enable being irradiated to
The light of 102 region of 12 region of thin film transistor (TFT), 101 region of grid line and data line can be towards pixel region
103 project, and the first layer of photonic crystals 41 can be set in the side towards incident ray of thin film transistor (TFT).To be irradiated to
The light of 102 region of 12 region of thin film transistor (TFT), 101 region of grid line and data line can be irradiated to first first
On layer of photonic crystals 41, and projected under the action of the first layer of photonic crystals 41 towards pixel region 103.
In general, the side away from thin film transistor (TFT) of array substrate is incident side, therefore, in the present embodiment, the first light
Sub- crystal layer 41 is arranged between the first substrate 11 and thin film transistor (TFT) 12.In the present embodiment, as shown in Fig. 2, film crystal
Pipe 12 is bottom gate thin film transistor, and gate electrode 121 is arranged in the first substrate 11, is provided with gate insulation layer on gate electrode 121
18, active layer 124 is arranged on gate insulation layer 18, and source electrode 122 and drain electrode 123 are located on the same floor and are arranged in active layer
On 124.Grid line (being not shown in Fig. 2) and 121 same layer of gate electrode are arranged, data line (being not shown in Fig. 2) and source/drain electrode same layer
Setting.Light injects array substrate 100 from the side away from thin film transistor (TFT) 12 of the first substrate 11.First layer of photonic crystals 41
The side towards incident ray of thin film transistor (TFT) is set, that is to say, that the first layer of photonic crystals 41 is located at thin film transistor (TFT)
12 and first between substrate 11, i.e., the first layer of photonic crystals 41 is located between gate electrode 121 and the first substrate 11.
In other embodiments, thin film transistor (TFT) can be top gate type thin film transistor, be provided in the first substrate active
Layer, gate insulation layer is set on active layer, gate electrode is set on gate insulation layer, interlayer insulating film, layer insulation are set on gate electrode
Source electrode and drain electrode is set on layer, source electrode and drain electrode passes through via hole respectively and is electrically connected with active layer, the first photonic crystal
Layer can be set between active layer and the first substrate.
As shown in Fig. 2, array substrate further includes flat between the first layer of photonic crystals 41 and thin film transistor (TFT) 12
Layer 13.In the present embodiment, flatness layer 13 is between the first layer of photonic crystals 41 and gate electrode 121.Due to the width of groove 413
Degree is nanoscale, and therefore, when forming flatness layer 13, flatness layer 13 will not be filled in the groove 413 of the first layer of photonic crystals 41
It is interior, so that flatness layer 13 will not influence the function of the first layer of photonic crystals 41.Flatness layer 13 is towards the side of thin film transistor (TFT) 12
With flat surface, thus, the metal layer for being used to form thin film transistor (TFT) 12 can be made on flat surfaces, avoided
Influence of first layer of photonic crystals 41 to later period metal layer processing procedure.
In addition, in order to avoid the light that is projected by the first layer of photonic crystals 41 is in the first layer of photonic crystals 41 and flatness layer 13
Interface generate total reflection, in the present embodiment, the refractive index of flatness layer 13 is greater than the refractive index of the first layer of photonic crystals 41.
To, when the light projected by the first layer of photonic crystals 41 injects flatness layer 13, light enters optically denser medium by optically thinner medium,
The light projected by the first layer of photonic crystals 41 can be projected by flatness layer 13 towards pixel region, avoided total reflection and made
At light losing, further improve the utilization rate of light.
The array substrate of the embodiment of the present invention is Senior super dimension field switch technology (Advanced Super Dimension
Switch, ADS) display pattern, as shown in Fig. 2, array substrate can also include setting on the source/drain electrodes and and source electrode
122 or the pixel electrode 14 being electrically connected of drain electrode 123, the interlayer insulating film 15 that is arranged on pixel electrode 14 and it is arranged in layer
Between public electrode 16 on insulating layer 15.The material of pixel electrode 14 and public electrode 16 can be indium tin oxide (ITO).Picture
Plain electrode 14 is plate electrode, and public electrode 16 is gap electrode.Array substrate further includes public electrode lead 17, public electrode
Lead 17 and gate electrode same layer are arranged, and public electrode 16 is electrically connected by via hole with public electrode lead 17.
In order to enable the light for being irradiated to 17 region of public electrode lead is also projected towards pixel region, such as Fig. 2 institute
Show, array substrate further includes the second layer of photonic crystals 42, the region of the second layer of photonic crystals 42 and public electrode lead 17
Region it is corresponding, thus, be irradiated to the light of 17 region of public electrode lead in the second layer of photonic crystals 42
It is projected under effect towards pixel region 103, and penetrates array substrate, reduced and be irradiated to 17 region of public electrode lead
Light losing further improves the utilization rate of light, improves the light transmittance of array substrate.
In the present embodiment, the second layer of photonic crystals 42 can be identical with the structure of the first layer of photonic crystals 41 and material,
Second layer of photonic crystals 42 is located on the same floor with the first layer of photonic crystals 41, and by being formed with a patterning processes.
In the present embodiment, orthographic projection of the public electrode lead 17 in the first substrate 11 is located at the second layer of photonic crystals 42
Within the scope of the orthographic projection in the first substrate 11.To be irradiated to the light of 17 region of public electrode lead in the second light
It under the action of sub- crystal layer 42, is projected towards pixel region 103, and penetrates array substrate from pixel region 103, thus, into
One step reduces light losing, further improves the light transmittance of array substrate.
Below by the technical solution of preparation process the present invention will be described in detail the embodiment of array substrate.It is described in embodiment
" patterning processes " include coating photoresist, mask exposure, development, etching, the processing such as stripping photoresist, be the system of existing maturation
Standby technique.The already known processes such as sputtering, vapor deposition, chemical vapor deposition can be used in deposition, and known coating processes can be used in coating, carve
Known method can be used in erosion, does not do specific restriction herein.
First time patterning processes form the first layer of photonic crystals 41 and the second layer of photonic crystals 42 in the first substrate 11.
Include: to form photon crystal film in the first substrate 11, forms the first layer of photonic crystals 41 and the second light by patterning processes
The pattern of sub- crystal layer 42, as illustrated in fig. 4 c, Fig. 4 c are the first photonic crystal of formation of first embodiment of the invention array substrate
Structural schematic diagram after layer.Wherein, the first substrate 11 can be using the transparent substrates such as substrate of glass or quartz substrate, the first photon
41 region of crystal layer is corresponding with grid line, data line and thin film transistor (TFT) region, the second layer of photonic crystals 42 with it is public
Contact conductor region is corresponding.The material of photon crystal film can be the gallium nitride (p-GaN) of p-type doping, n-type doping
Gallium nitride (n-GaN) or indium tin oxide etc..
Fig. 4 a is the structural schematic diagram after etching for the first time during forming the first layer of photonic crystals, and Fig. 4 b is to form first
Structural schematic diagram during layer of photonic crystals after photoresist ashing.In the present embodiment, the first layer of photonic crystals 41 and second
The structure of layer of photonic crystals 42 as shown in figure 3, form the patterning processes of the first layer of photonic crystals 41 and the second layer of photonic crystals 42,
It specifically includes: coating a layer photoresist on photon crystal film；Photoresist is carried out using intermediate tone mask or gray level mask
Ladder exposes and develops, and forms unexposed area in the non-recessed position of the first layer of photonic crystals 41 and the second layer of photonic crystals 42
Domain retains whole photoresists, forms Partial exposure in the groove location of the first layer of photonic crystals 41 and the second layer of photonic crystals 42
Region retains a part of photoresist, forms complete exposure area in other positions, photoresist is removed, and exposes photonic crystal
Film；The photon crystal film of complete exposure area is performed etching, as shown in fig. 4 a；Ashing processing is carried out to photoresist, is gone
Except the photoresist of the photoresist of partial exposure area, i.e. groove location is removed, unexposed area i.e. the first layer of photonic crystals 41
Retain a part of photoresist with the non-recessed position of the second layer of photonic crystals 42, as shown in Figure 4 b；To the light of partial exposure area
Sub- crystal film performs etching, and forms the pattern of the first layer of photonic crystals 41 and the second layer of photonic crystals 42, as illustrated in fig. 4 c.
Second of patterning processes forms flatness layer 13 and gate electrode 121.It include: to be formed with the first layer of photonic crystals 41
The first substrate 11 on sequentially form flatness layer 13 and grid metal film, form gate electrode 121, grid line and public affairs using patterning processes
The pattern of common electrode lead 17, as shown in figure 5, Fig. 5 is the knot of first embodiment of the invention array substrate formed after gate electrode
Structure schematic diagram.Wherein, the orthographic projection of gate electrode 121 and grid line in the first substrate 11 is respectively positioned on the first layer of photonic crystals 41
Within the scope of orthographic projection in one substrate 11, orthographic projection of the public electrode lead 17 in the first substrate 11 is located at the second photonic crystal
Layer 42 is within the scope of the orthographic projection in the first substrate 11.Grid metal film can using platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo,
One of metals such as chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W are a variety of, and the material of flatness layer 13 includes transparent organic, can be with
Flatness layer is formed by the way of coating.
Third time patterning processes form gate insulation layer 18 and active layer 124.It include: to be formed with the first of gate electrode 121
It is sequentially depositing gate insulation layer 18 and active film in substrate 11, the pattern of active layer 124 is formed using patterning processes, such as Fig. 6 institute
Show, Fig. 6 is the structural schematic diagram of first embodiment of the invention array substrate formed after active layer.Wherein, active film can be with
It is amorphous silicon, polysilicon or microcrystalline silicon materials, is also possible to metal oxide materials, metal oxide materials can be indium gallium zinc
Oxide (Indium Gallium Zinc Oxide, IGZO) or indium tin zinc oxide (Indium Tin Zinc Oxide,
ITZO).Gate insulation layer 18 can be using the composite layer of silicon nitride SiNx, silicon oxide sio x or SiNx/SiOx.
4th patterning processes form source electrode 122 and drain electrode 123.It include: to be formed with the first of active layer 124
Source/drain metallic film is deposited in substrate 11, forms source electrode 122, drain electrode 123 and data line (in figure not using patterning processes
Show) pattern.As shown in fig. 7, Fig. 7 shows for the structure after the formation source/drain electrode of first embodiment of the invention array substrate
It is intended to.Wherein, the orthographic projection of source electrode 122, drain electrode 123 and data line in the first substrate 11 is respectively positioned on the first photonic crystal
Layer 41 is within the scope of the orthographic projection in the first substrate 11.Source/drain metallic film can use platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum
One of metals such as Mo, chromium Cr, aluminium Al, tantalum Ta, titanium Ti, tungsten W are a variety of.
5th patterning processes form pixel electrode 14.It include: to form the first of active electrode 122 and drain electrode 123
Ito thin film is deposited in substrate 11, forms the pattern of pixel electrode 14 using patterning processes, as shown in figure 8, Fig. 8 is the present invention the
The structural schematic diagram of one embodiment array substrate formed after pixel electrode.
6th patterning processes form interlayer insulating film 15.It include: in the first substrate 11 for being formed with pixel electrode 14
Insulation film is deposited, the pattern of interlayer insulating film 15 is formed using patterning processes, is provided on interlayer insulating film 15 for exposing
The via hole of public electrode lead 17, as shown in figure 9, Fig. 9 is the formation interlayer insulating film of first embodiment of the invention array substrate
Structural schematic diagram afterwards.
7th patterning processes form public electrode 16.It include: to deposit ito thin film on interlayer insulating film 15, using structure
Figure technique forms the pattern of public electrode 16, and public electrode 16 is electrically connected by via hole with public electrode lead 17, such as Fig. 2 institute
Show.Public electrode 16 is in gap electrode.
The array substrate of the embodiment of the present invention, when light injects array away from thin film transistor (TFT) side from the first substrate 11
When substrate, the light for being irradiated to grid line, data line and thin film transistor (TFT) region is irradiated to the first layer of photonic crystals 41 first
On, the first layer of photonic crystals 41 can be with oriented light-guiding, thus it is possible to vary the direction of propagation of light thereon is irradiated to, so that being irradiated to
Light thereon is projected towards pixel region 103, and in turn, this some light can penetrate array substrate from pixel region 103, this
Sample just reduces the light losing of grid line, data line and thin film transistor (TFT) region, improves the utilization rate of light, improves
The light transmittance of array substrate.
Second embodiment:
Figure 10 is the structural schematic diagram of second embodiment of the invention display panel.Inventive concept based on above embodiments,
Second embodiment of the invention provides a kind of display panel, as shown in Figure 10.Display panel includes the array in above embodiments
Substrate 100 further includes color membrane substrates 200 and liquid crystal layer 300.Color membrane substrates 200 are arranged oppositely with array substrate 100, color film base
Plate 200 and array substrate 100 are connected by sealant 400.The setting of liquid crystal layer 300 is located at array substrate 100 and color membrane substrates 200
Between, and be located at sealant 400 and enclose in the region set.
Color membrane substrates 200 include the second substrate 21, color film 22 and black matrix 23.The court of the second substrate 21 is arranged in color film 22
To the side of array substrate 100, black matrix 23 is between adjacent color film 22.Positive throwing of the black matrix 23 in the first substrate 11
Shadow is located at the first layer of photonic crystals 41 within the scope of the orthographic projection in the first substrate 11.To as shown in Figure 10, when light is from battle array
When display panel is injected in the side away from color membrane substrates of column substrate, vertical irradiation is first to the light in 23 region of black matrix
It is first irradiated on the first layer of photonic crystals 41, the first layer of photonic crystals 41 can change the propagation of vertical irradiation to light thereon
Direction, so that the light of vertical irradiation to 23 region of black matrix is projected towards color 22 region of film, in turn, this part light
Line can penetrate display panel from color 22 region of film, in this way, just reducing the light for being irradiated to 23 region of black matrix
Loss, improves the utilization rate of light, improves the light transmittance of display panel, improve the brightness of display panel.Therefore, of the invention
The display panel of embodiment can improve aobvious in the case where not increasing backlight power consumption and brightness and other costs of material
The light transmittance for showing panel promotes the brightness of display panel.
It can also be seen that display panel further includes first alignment layer 19 and second orientation layer 24 from Fig. 4.First alignment layer
19 are located at the side towards liquid crystal layer 300 of public electrode 16, second orientation layer 24 be located at color film 22 towards liquid crystal layer 300
Side.
Display panel can be with are as follows: mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator
Etc. any products or components having a display function.
In the description of the embodiment of the present invention, it is to be understood that term " on ", "lower", "front", "rear", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "top", "bottom", "inner", "outside" is that orientation based on the figure or position are closed
System, is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must have
Specific orientation is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.
In the description of the embodiment of the present invention, it should be noted that unless otherwise clearly defined and limited, term " peace
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (12)
1. a kind of array substrate, which is characterized in that including the first substrate and the grid line, the data line that are arranged in first substrate
And thin film transistor (TFT), the grid line and the data line intersect and limit multiple pixel regions, the thin film transistor (TFT) with
The pixel region is corresponding, and array substrate further includes being arranged in first substrate for making to be irradiated to the grid line, described
The first layer of photonic crystals that data line and the light of the thin film transistor (TFT) region are projected towards the pixel region.
2. array substrate according to claim 1, which is characterized in that first layer of photonic crystals has incident side and goes out
Light side, the light emission side have multiple grooves.
3. array substrate according to claim 2, which is characterized in that multiple grooves are evenly arranged, the groove
Depth is less than or equal to 120nm, and the spacing between the two neighboring groove is 350nm~600nm.
4. array substrate according to claim 1, which is characterized in that the material of first layer of photonic crystals includes p-type
At least one of the gallium nitride of doping, the gallium nitride of n-type doping and indium tin oxide.
5. array substrate according to claim 1, which is characterized in that the grid line, data line and thin film transistor (TFT) are in institute
It states the orthographic projection in the first substrate and is respectively positioned on first layer of photonic crystals within the scope of the orthographic projection in first substrate.
6. array substrate described according to claim 1~any one of 5, which is characterized in that first layer of photonic crystals
It is arranged between first substrate and the thin film transistor (TFT).
7. array substrate according to claim 6, which is characterized in that the thin film transistor (TFT) is bottom gate thin film crystal
Pipe, the thin film transistor (TFT) include the gate electrode in first substrate, the active layer on the gate electrode and
Source electrode and drain electrode on the active layer, first layer of photonic crystals are located at the gate electrode and first base
Between bottom.
8. array substrate according to claim 6, which is characterized in that the array substrate further includes being arranged described first
Flatness layer between layer of photonic crystals and the thin film transistor (TFT).
9. array substrate according to claim 6, which is characterized in that the array substrate further includes being arranged in the film
Pixel electrode on transistor, the interlayer insulating film being arranged on the pixel electrode and it is arranged on the interlayer insulating film
Public electrode, the array substrate further includes being arranged with the grid line same layer and the common electrical that is electrically connected with the public electrode
Pole lead further includes being arranged between the public electrode lead and first substrate and for making to be irradiated to the common electrical
The second layer of photonic crystals that the light of pole lead region is projected towards the pixel region.
10. array substrate according to claim 9, which is characterized in that the public electrode lead is in first substrate
On orthographic projection be located at second layer of photonic crystals within the scope of the orthographic projection in first substrate.
11. a kind of preparation method of array substrate characterized by comprising
Photon crystal film is formed in the first substrate；
A layer photoresist is coated on the photon crystal film；
Ladder exposure is carried out to photoresist using intermediate tone mask or gray level mask and is developed, in the non-recessed of the first layer of photonic crystals
Groove location forms unexposed area, retains photoresist, forms partial exposure area in the groove location of the first layer of photonic crystals, protects
A part of photoresist is stayed, forms complete exposure area, unglazed photoresist in other positions；
The photon crystal film of complete exposure area is performed etching；
Ashing processing is carried out to photoresist, removes the photoresist of partial exposure area, unexposed area retains a part of photoresist；
The photon crystal film of partial exposure area is performed etching, the pattern of the first layer of photonic crystals is formed；
Grid line, data line and thin film transistor (TFT), the grid line and the data line phase are formed on first layer of photonic crystals
Mutually intersect and limit multiple pixel regions, the thin film transistor (TFT) is corresponding with the pixel region, first layer of photonic crystals
For making to be irradiated to the light of the grid line, the data line and the thin film transistor (TFT) region towards the pixel region
It projects.
12. a kind of display panel, which is characterized in that including array substrate described in any one of claim 1~10, also wrap
The color membrane substrates with array substrate pairing setting are included, the color membrane substrates include the second substrate, are arranged in second base
The color film towards the array substrate side and the black matrix that is arranged between the adjacent color film, the black matrix at bottom exist
Orthographic projection in first substrate is located at first layer of photonic crystals within the scope of the orthographic projection in first substrate.
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| CN112882299A (en) * | 2021-03-10 | 2021-06-01 | 武汉京东方光电科技有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN109828404B (en) | 2022-03-18 |
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