CN112882299A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN112882299A CN112882299A CN202110261553.2A CN202110261553A CN112882299A CN 112882299 A CN112882299 A CN 112882299A CN 202110261553 A CN202110261553 A CN 202110261553A CN 112882299 A CN112882299 A CN 112882299A
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- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 29
- 239000005543 nano-size silicon particle Substances 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002105 nanoparticle Substances 0.000 claims 1
- 238000005265 energy consumption Methods 0.000 abstract description 3
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 71
- 239000002159 nanocrystal Substances 0.000 description 16
- 239000013078 crystal Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000002077 nanosphere Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133524—Light-guides, e.g. fibre-optic bundles, louvered or jalousie light-guides
Abstract
The application discloses array substrate and manufacturing method, display panel and display device thereof, wherein, array substrate includes: the thin-film transistor layer comprises an opening area and a non-opening area; the first light guide layer is arranged on the light incidence side of the thin film transistor layer and comprises a hollowed-out area and a light guide pattern, the hollowed-out area is arranged corresponding to the opening area, the light guide pattern is arranged corresponding to the non-opening area, and the light guide pattern is used for guiding at least part of backlight light rays which penetrate into the light guide pattern into the opening area. The light guide pattern can lead at least one part of backlight light in the backlight light which is originally shielded or reflected by the non-opening area into the opening area, and under the condition of not changing the backlight brightness, more backlight light can enter the opening area, so that the display brightness can be improved under the condition of the same backlight brightness, and the light guide pattern is favorable for reducing energy consumption and is green and environment-friendly.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
Thin Film Transistor Liquid Crystal displays (TFT-LCDs) are widely used in products such as televisions, displays, notebook computers, smart phones, and the like, and are important Display devices in human life. The TFT-LCD has the advantages of mature manufacturing process, high definition, low price and the like.
For TFT-LCD, the display brightness mainly depends on the transmittance and the backlight brightness, and under the same display brightness, the higher the transmittance is, the lower the required backlight brightness is, and the power consumption of the whole display module is relatively lower, whereas, the lower the transmittance is, the higher the required backlight brightness is, and the power consumption of the whole display module is also relatively higher. Therefore, how to increase the display brightness under the same backlight brightness condition is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The present application is directed to an array substrate, a method for manufacturing the same, a display panel and a display device, which are used to improve display brightness under the same backlight brightness.
In a first aspect, the present invention provides an array substrate, including:
a thin-film transistor layer comprising an open region and a non-open region;
the first light guide layer is arranged on the light incident side of the thin film transistor layer and comprises a hollow area and a light guide pattern, the hollow area is arranged corresponding to the opening area, the light guide pattern is arranged corresponding to the non-opening area, and the light guide pattern is used for guiding at least part of backlight light which is emitted into the light guide pattern into the opening area.
As an implementation manner, the light guide pattern is a nano-crystalline grain light guide pattern, and a plurality of nano-crystalline grains are distributed in the nano-crystalline grain light guide pattern.
As an implementation manner, the nanocrystal particle is at least any one of a nanosphere crystal, a nanosphere crystal and a nanocopolymer crystal.
In a practical mode, the grain size of the nanometer crystal grains is 1 nm-200 nm.
As an implementation manner, the material of the nanocrystal particle is any one of nano silicon, nano silicon nitride, nano silicon oxynitride and nano silicon oxide.
As an implementation manner, a second light guide layer is disposed between the thin film transistor layer and the first light guide layer, and the second light guide layer is a planarized light transmissive layer.
As an implementation manner, the material of the second optical guide layer is at least any one of silicon nitride, silicon oxynitride, and silicon oxide.
In a second aspect, the present invention provides a method for preparing an array substrate as described above, including:
providing a substrate;
forming a first light guide layer on the substrate, the first light guide layer including a hollow area and a light guide pattern;
and forming a thin film transistor layer on the first light guide layer, wherein the thin film transistor layer comprises an opening area and a non-opening area, the hollow-out area is arranged corresponding to the opening area, the light guide pattern is arranged corresponding to the non-opening area, and the light guide pattern is used for guiding at least part of backlight light emitted into the light guide pattern into the opening area.
In a third aspect, the present invention provides a display panel, including the array substrate.
In a fourth aspect, the present invention provides a display device, including the display panel.
In the above-mentioned scheme, owing to set up the first light guide layer that has the light guide pattern, the light guide pattern can be with penetrating into at least partial light guide opening district in a poor light of light guide pattern, that is to say, the light guide pattern can be with originally by the leading-in opening district of at least some light guide opening district in a poor light that non-opening district sheltered from or the reflection, under the condition that does not change luminance in a poor light, make more light in a poor light can enter into the opening district, consequently can be under the condition of equal luminance in a poor light, improve display brightness, be favorable to reducing the energy consumption, green. In addition, since the hollow-out area of the first light guide layer is arranged corresponding to the opening area, and the light guide pattern is arranged corresponding to the non-opening area, however, the opening area corresponds to the sub-pixel area of the color film substrate, and the non-opening area corresponds to the black matrix area of the color film substrate, then the light guide pattern and the black matrix area can be prepared by using the existing equipment and adopting the same Mask (Mask), so that the extra Mask cost is not required to be increased under the condition of increasing the display brightness, and the existing equipment is not required to be modified.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an array substrate according to an embodiment of the present invention for improving display brightness;
fig. 3-7 are schematic structural diagrams illustrating a manufacturing process of an array substrate according to an embodiment of the invention;
fig. 8 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to at least fig. 1, an array substrate according to an embodiment of the present invention includes:
a thin-film transistor layer 4, the thin-film transistor layer 4 including an open area A and a non-open area B;
thin-film transistor layer 4 is a composite layered structure, for example, but not limited to, the thin-film transistors of thin-film transistor layer 4 may be of a back-channel blocking type, a back-channel etching type, or a top-gate type. In this example, the thin film transistor structure in the thin film transistor layer 4 is of a back channel etching type, and may include a gate electrode layer 41, a gate insulating layer 42, an active layer 43, a source/drain electrode layer 44, and a passivation layer 45, which are sequentially stacked, and a pixel electrode 10 may be formed on the passivation layer 45, as shown in fig. 7.
The opening area A is corresponding to the position of each sub-pixel, the non-opening area B is corresponding to the position of the black matrix, and the grid line, the source drain line and the like of the thin film transistor are also positioned in the non-opening area B.
Referring to fig. 5, the first light guide layer 2 is disposed on the light incident side of the thin film transistor layer 4, the first light guide layer 2 includes a hollow-out region C and a light guide pattern 6, the hollow-out region C is disposed corresponding to the opening region a, so that the backlight light can directly enter the opening region a through the hollow-out region C, the light guide pattern 6 is disposed corresponding to the non-opening region B, and the light guide pattern 6 is configured to guide at least a part of the backlight light incident on the light guide pattern 6 into the opening region a.
The corresponding arrangement referred to herein may refer to an opposite arrangement, and the sizes of the two components/structures of the opposite arrangement may be the same or different, for example, the structure of the hollow area C may be similar to that of the opening area a, and the area may be greater than or equal to that of the opening area a, so as to ensure that the opening ratio is sufficient.
In the above solution, referring to fig. 2, since the array substrate 301 is provided with the first light guide layer 2 having the light guide pattern 6, the light guide pattern 6 can guide at least a part of the backlight light entering the light guide pattern 6 into the opening region a, that is, the light guide pattern 6 can guide at least a part of the backlight light originally blocked or reflected by the non-opening region B into the opening region a, so that under the condition of not changing the backlight brightness, more backlight light (the upward arrow in fig. 2 represents the backlight light) can enter the opening region a, and further backlight is provided for the sub-pixel region 2311 of the color filter substrate 302, so that under the condition of the same backlight brightness, the display brightness can be improved, which is beneficial for reducing energy consumption, and is green and environment-friendly. In addition, since the hollow area C of the first light guide layer 2 of the array substrate 301 is disposed corresponding to the opening area a, and the light guide pattern 6 is disposed corresponding to the non-opening area B, however, the opening area a corresponds to the sub-pixel area 2311 of the color film substrate 302, and the non-opening area B corresponds to the black matrix area 2312 of the color film substrate, referring to fig. 9, the light guide pattern 6 and the black matrix area 2312 may be prepared by using the existing equipment and using the same Mask (Mask), and therefore, an additional Mask cost is not required to be added when the display luminance is increased, and the existing equipment is not required to be modified.
As an implementation manner, the light guide pattern 6 is a nano-crystalline grain light guide pattern, and a plurality of nano-crystalline grains 5 are distributed in the nano-crystalline grain light guide pattern. The plurality of nano crystal grains 5 are distributed in the nano crystal grain light guide pattern, and the nano crystal grains 5 can reflect the backlight light rays which are emitted into the nano crystal grain light guide pattern for multiple times, so that part of the backlight light rays which are emitted into the nano crystal grain light guide pattern are guided into the opening area A, the backlight light ray throughput of the opening area A is improved, and the display brightness can be improved under the condition that the backlight light source brightness is not changed.
According to the rayleigh scattering law, the intensity of the scattered light in different directions is proportional to 1+ cos2 θ, and if the percentage of the non-opening area B is 50% of the array substrate and the extinction ratio of the first light guiding layer 2 is 1-k, the increase Δ T of the transmittance is:
wherein θ is an angle between the light (scattered light) guided from the light guide pattern 6 to the opening area a and the backlight light (incident light) incident on the light guide pattern 6; taking theta in the scattered light as pi/4-pi/2 as effective light; k is a constant, and is determined by the material, shape and particle size of the nanocrystal particles 5 arranged in the nanocrystal light guide pattern, and the transmittance can be improved by 3% to 5% by using the following material, shape and particle size, for example.
As an implementation manner, the nanocrystal particle 5 is at least any one of a nanosphere crystal, and a nanocrystallite crystal.
In a practical mode, the grain size of the nanocrystal particle 5 is 1nm to 200 nm.
As an implementation manner, the material of the nano crystal grain 5 is any one of nano silicon (Si), nano silicon nitride (SiNx), nano silicon oxynitride (Si (on) x), and nano silicon oxide (SiOx).
As an implementation manner, a second light guide layer 3 is disposed between the thin film transistor layer 4 and the first light guide layer 2, and the second light guide layer 3 is a planarized light-transmissive layer.
Through set up the flattening euphotic layer between thin-film transistor layer 4 and first light guide layer 2, on the one hand, it can regard as the planarization layer that forms thin-film transistor layer 4, owing to do benefit to the structure that makes this array substrate more stable, on the other hand can improve the homogeneity of leading-in to the light of opening area A by leaded light pattern 6.
As an implementation manner, the material of the second optical guiding layer 3 is at least any one of silicon nitride, silicon oxynitride and silicon oxide.
In a second aspect, as shown in fig. 3 to 8, the present invention provides a method for preparing an array substrate as above, including:
s21: providing a substrate 1;
s22: forming a first light guide layer 2 on the substrate 1, the first light guide layer 2 including a hollow area C and a light guide pattern 6;
s23: forming a thin film transistor layer 4 on the first light guide layer 2, wherein the thin film transistor layer 4 includes an opening area a and a non-opening area B, the hollow-out area C is disposed corresponding to the opening area a, the light guide pattern 6 is disposed corresponding to the non-opening area B, and the light guide pattern 6 is used for guiding at least part of backlight light emitted into the light guide pattern 6 into the opening area a.
The following description is given to the preparation method of the array substrate provided by the invention in one implementation manner, which is not the only limitation of the preparation method, and one or some process steps may be replaced or omitted according to actual needs.
As shown in fig. 3, a substrate 1 is provided, the substrate 1 being, for example, but not limited to, a glass substrate;
as shown in fig. 4, a photoresist 7 is coated on the substrate 1 and patterned to form a groove 8 for depositing a light guide pattern 6;
as shown in fig. 5, a light guide pattern 6 is formed in the groove 8 by evaporation, a plurality of nano crystal grains 5 are distributed in the light guide pattern 6, the grain size of the nano crystal grains 5 is 1nm to 200nm, the nano crystal grains are made of any one of nano silicon (Si), nano silicon nitride (SiNx), nano silicon oxynitride (Si (on) x) and nano silicon oxide (SiOx), and the shape of the nano crystal grains 5 is at least any one of nano spherulites, nano ellipsoids and nano polyhedrons; removing the photoresist 7 forms the first light guide layer 2 having the hollow area C and the light guide pattern 6.
As shown in fig. 6, a second light guiding layer 3 is deposited on the first light guiding layer 2, and the material of the second light guiding layer 3 is at least any one of silicon nitride, silicon oxynitride and silicon oxide, and may be a single-layer, double-layer or multi-layer structure, such as a SiNx/SiOx composite film, which may serve to provide better blocking and planarization effects and also facilitate stress relief between the layers.
A thin film transistor layer 4 is formed on the second light guide layer 3, the thin film transistor layer 4 includes a substrate (not shown in the figure), a gate electrode layer 41, a gate insulating layer 42, an active layer 43, a source drain layer 44, and a passivation layer 45, which are sequentially stacked, and a pixel electrode 10 is formed on the passivation layer 45.
Of course, in other examples, the second light guide layer 3 may not be provided, but the substrate in the thin-film transistor layer 4 may be made thicker.
In a third aspect, the present invention provides a display panel, including the array substrate.
Specifically, as shown in fig. 9, the liquid crystal display device includes the array substrate 301, the liquid crystal layer 22, and the color filter substrate 302 sequentially disposed, wherein the color filter substrate includes the color filter layer 231 and the encapsulation layer 232, the sub-pixel area 2311 of the color filter layer 231 corresponds to the opening area a of the array substrate 301, and the black matrix area 2312 of the color filter substrate 302 corresponds to the non-opening area B of the array substrate 301.
In a fourth aspect, the present invention provides a display device, including the display panel.
The display device in this embodiment may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator.
It will be understood that any orientation or positional relationship indicated above with respect to the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc., is based on the orientation or positional relationship shown in the drawings and is for convenience in describing and simplifying the invention, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be considered limiting of the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. An array substrate, comprising:
a thin-film transistor layer comprising an open region and a non-open region;
the first light guide layer is arranged on the light incident side of the thin film transistor layer and comprises a hollow area and a light guide pattern, the hollow area is arranged corresponding to the opening area, the light guide pattern is arranged corresponding to the non-opening area, and the light guide pattern is used for guiding at least part of backlight light which is emitted into the light guide pattern into the opening area.
2. The array substrate of claim 1, wherein the light guide pattern is a nano-grain light guide pattern, and a plurality of nano-grains are disposed in the nano-grain light guide pattern.
3. The array substrate of claim 2, wherein the nano-crystalline grains are at least any one of nano-spherulites, nano-ellipsoids, and nano-polyhedrons.
4. The array substrate of claim 2 or 3, wherein the nano-crystalline particles have a particle size of 1nm to 200 nm.
5. The array substrate of claim 2 or 3, wherein the material of the nano-crystalline grains is any one of nano-silicon, nano-silicon nitride, nano-silicon oxynitride and nano-silicon oxide.
6. The array substrate of any of claims 1-3, wherein a second light guide layer is disposed between the thin-film-transistor layer and the first light guide layer, the second light guide layer being a planarized light transparent layer.
7. The array substrate of claim 6, wherein the second light guide layer is made of at least one of silicon nitride, silicon oxynitride, and silicon oxide.
8. A method for preparing the array substrate according to any one of claims 1 to 7, comprising:
providing a substrate;
forming a first light guide layer on the substrate, the first light guide layer including a hollow area and a light guide pattern;
and forming a thin film transistor layer on the first light guide layer, wherein the thin film transistor layer comprises an opening area and a non-opening area, the hollow-out area is arranged corresponding to the opening area, the light guide pattern is arranged corresponding to the non-opening area, and the light guide pattern is used for guiding at least part of backlight light emitted into the light guide pattern into the opening area.
9. A display panel comprising the array substrate according to any one of claims 1 to 7.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110261553.2A CN112882299A (en) | 2021-03-10 | 2021-03-10 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN202110261553.2A CN112882299A (en) | 2021-03-10 | 2021-03-10 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN112882299A true CN112882299A (en) | 2021-06-01 |
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| CN103525316A (en) * | 2013-09-29 | 2014-01-22 | 合肥京东方光电科技有限公司 | Seal agent and display device |
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| CN110568661A (en) * | 2019-08-14 | 2019-12-13 | 深圳市华星光电技术有限公司 | Diffusion sheet structure |
| CN111613735A (en) * | 2020-06-03 | 2020-09-01 | 京东方科技集团股份有限公司 | Light emitting device, manufacturing method thereof, display device or lighting device |
| WO2020258766A1 (en) * | 2019-06-28 | 2020-12-30 | 深圳市隆利科技股份有限公司 | Backlight module and electronic device |
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2021
- 2021-03-10 CN CN202110261553.2A patent/CN112882299A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103525316A (en) * | 2013-09-29 | 2014-01-22 | 合肥京东方光电科技有限公司 | Seal agent and display device |
| CN107255885A (en) * | 2017-08-16 | 2017-10-17 | 京东方科技集团股份有限公司 | Display panel and its manufacture method |
| CN109828404A (en) * | 2019-01-31 | 2019-05-31 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel |
| WO2020258766A1 (en) * | 2019-06-28 | 2020-12-30 | 深圳市隆利科技股份有限公司 | Backlight module and electronic device |
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Application publication date: 20210601 |