JP3463007B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates <br/> the liquid crystal display equipment.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device using a thin film transistor (TFT) as a switching element for driving a liquid crystal has been actively developed.

As an example of the above liquid crystal display device, a schematic plan view of a driver integrated liquid crystal display device is shown in FIG. A gate driver 2, a source driver 3 and a TFT array section 4 are arranged on a glass substrate 1 or a quartz substrate 1. The gate driver 2 is composed of a shift register 2a and a buffer 2b. The source driver 3 is composed of a shift register 3a and a buffer 33b, and an analog switch 9 for sampling the video line 8.

In the TFT array section 4, a large number of parallel gate bus lines 1 extending from the gate driver 2 are provided.
0 is set. A large number of parallel source bus lines 11 extending from the source driver 3 are arranged orthogonal to the gate bus lines 10. Further, an additional capacitance common line 12 is arranged in parallel with the gate bus line 10. And two gate bus lines 10 and 2
TFTs 5, pixels 6 and additional capacitors 7 are provided in a rectangular area surrounded by the source bus line 11 of the book. The gate electrode of the TFT 5 is the gate bus line 10
, The source electrode is connected to the source bus line 11, and the drain electrode is connected to the pixel 6 and the additional capacitor 7. Liquid crystal is sealed between a pixel electrode (not shown) that constitutes the pixel 6 and a counter electrode (not shown) on the counter substrate. Further, the additional capacitance common line 12 is connected to an electrode having the same potential as the counter electrode.

In the liquid crystal display device having the above structure,
In recent years, a pixel having a small pixel pitch has been developed, and a pixel pitch of 30 μm or less, and in some cases 20 μm or less has been developed. In particular, in the case of a portable projector, it is necessary to downsize the device, and a high-definition liquid crystal display with a diagonal of 1 inch or less is used.

FIG. 8 is a layout diagram of one pixel 6 in the liquid crystal display device shown in FIG. In addition, FIG.
FIG. 9 is a sectional view taken along the line AA in FIG. 8. Hereinafter, the procedure for forming the pixels 6 in the conventional liquid crystal display device will be described with reference to FIGS. 8 and 9.

First, a polycrystalline silicon thin film 16 serving as an active layer is formed with a thickness of 40 nm to 80 nm on an insulating substrate 1 such as a glass substrate or a quartz substrate. Next, the gate insulating film 17 is formed to a thickness of 80 nm to 150 nm by using sputtering or CVD (chemical vapor deposition) method. Then, the polycrystalline silicon thin film 16, phosphorus ions are implanted at a concentration of 1 × 10 ¹⁵ cm ^-2 in the additional capacitance portion 16a forming the additional capacitor after. This is because when the ion implantation is performed after the gate electrode 18 and the additional capacitance common wiring 12 are formed, ions are not implanted below the electrodes and the wiring because of the electrodes and the wiring.

Next, the gate electrode 18, the gate bus line 10 and the additional capacitance common wiring 12 are formed by patterning into a predetermined shape using metal or low resistance polycrystalline silicon. Next, in order to determine the conductivity type of this thin film transistor, phosphorus ions are implanted from above the gate electrode 18 at a concentration of 1 × 10 ¹⁵ cm ⁻² , and a channel 20 is formed below the gate electrode 18. Next, a first interlayer insulating film 21 is formed on the entire surface using a silicon oxide film or a silicon nitride film, and then contact holes 22 and 23 are formed. Next, the source bus line 11 and the drain electrode 24 are formed by using a low resistance metal such as Al.

Next, the second interlayer insulating film 2 is made of acrylic resin or the like.
After forming 5 on the entire surface, a contact hole 26 is formed, and then a pixel electrode 27 is formed using a transparent conductive film such as ITO (indium tin oxide).

[0010]

However, the structure of the pixel 6 in the conventional liquid crystal display device has the following problems. That is, what actually turns on / off the liquid crystal and functions as a substantial opening is that from the display area to the gate bus line 10, the source bus line 11 and the TFT.
5 is a portion excluding 5 and the additional capacitance common wiring 12,
If the pixel pitch is as small as 30 μm or less,
The opening is also particularly small.

When the aperture ratio of the display area is small,
There is a problem that the display of the liquid crystal display device becomes dark, which is not preferable.

[0012] Accordingly, an object of the present invention is to provide a liquid crystal display equipment with an improved aperture ratio of the display area.

[0013]

In order to achieve the above object, a liquid crystal display device according to the first invention comprises a gate bus line,
Source bus lines, additional capacity, a first substrate on Symbol gate bus lines and the source bus lines and transistors arranged in the vicinity of an intersection of the, and pixel electrodes connected to the transistors are formed, facing to the pixel electrode And a second substrate on which a counter electrode is formed, and a liquid crystal material is sandwiched between the first substrate and the second substrate,
Below the gate bus line or source bus line
The groove formed in the insulating film formed in the area and the groove described above are covered.
Provided with a additional capacitor upper electrode formed I, the
The drain end of the transistor is on the insulating film above the inner wall of the groove.
Along the inner wall of the groove.
Between the extension of the drain and the upper electrode of the additional capacitance
It constitutes the additional capacitance, and
Is the above-mentioned gate bus line or source bus line
An additional volume that overlaps and doubles as a lower light-shielding film
Common wiring is formed, and the drain extension and
A second additional capacitance is formed with the additional capacitance common line.
That that you are characterized by.

According to the above Symbol configuration, the inner wall of the groove formed in the lower region of the gate bus line or a source bus line, the additional made between the drain of the extending portion and the additional capacitor upper electrode of the transistor A capacity is formed. Thus, the additional capacitance of the desired capacitance is efficiently formed in a small area by overlapping the bus line. Therefore, reduction in the aperture ratio due to the additional capacity Ru is suppressed.

Further , a second additional capacitance is formed between the extending portion of the drain and the additional capacitance common line, and the additional capacitance is also formed under the transistor. In this way, in addition to the above-mentioned additional capacitance, a desired additional capacitance can be obtained in a small area, and a decrease in aperture ratio due to the additional capacitance can be suppressed. Further, the light from below the transistor is blocked by the additional capacitance common wiring functioning as a lower light shielding film. In this way, leakage current is prevented.

The liquid crystal display device according to the first invention is
It is desirable to electrically connect the additional capacitance common wiring to the additional capacitance upper electrode.

According to the above structure, since the additional capacitance common wiring is electrically connected to the additional capacitance upper electrode, it is not necessary to form a new wiring for applying a voltage to the additional capacitance upper electrode. . Therefore, reduction in the aperture ratio due to the wiring for the additional capacitor upper electrode Ru is avoided.

[0018] In addition, the liquid crystal display device of the second aspect of the present invention, the gate
Bus line, source bus line, additional capacitance, above gate
It is placed near the intersection of the bus line and the source bus line.
Transistor, a pixel connected to the above transistor
It faces the first substrate on which the electrode is formed and the pixel electrode.
A second substrate having a counter electrode formed thereon, the first substrate
A liquid crystal surface in which a liquid crystal material is sandwiched between the second substrate and the second substrate.
In the device shown, the additional capacitance is the groove provided in the insulating film.
Is formed on the inner wall of the
A topper is formed, and it is below the etch stopper.
Equipped with additional capacitance common wiring formed in common with other additional capacitances
In addition, the common wiring of the additional capacitance and the etch stopper are used.
Forms a second additional capacitance Te, the additional capacitor common line, formed by the source bus line and overlaps the lower region of the channel portion of the transistor, that it has to serve as a lower light shielding film It has a feature .

According to the above structure, the groove forming the additional capacitance
An etch stopper is formed on the bottom of the. According to
To form a groove on the insulating film by etching.
If the groove depth is set to a specified value, there will be
A trench-type additional capacitance is obtained. In addition,
The bottom of the groove is flat due to the presence of a stopper.
It Therefore, the above addition that exhibits a reliable capacity value.
Capacity is obtained.

Further, the inner wall portion and the lower portion of the groove have additional capacity.
Quantity is formed. In this way, you can efficiently request in a small area
The additional capacity of the capacity is obtained, and the aperture ratio due to the additional capacity is obtained.
Can be suppressed.

Further , the lower light-shielding film formed so as to overlap the source bus line and functioning as the additional capacitance common wiring blocks light from below the transistor. Thus, leakage current Ru is prevented.

[0022]

DETAILED DESCRIPTION OF THE INVENTION hereinafter be described in detail by way of embodiments thereof illustrated in the accompanying drawings. First Embodiment FIG. 1 is a layout diagram of one pixel in the liquid crystal display device of the present embodiment. 2 shows a cross section taken along the line BB in FIG. Further, FIG. 3 shows C in FIG.
-C shows a cross section taken along the arrow. Hereinafter, the configuration and the forming procedure of the liquid crystal display device according to the present embodiment will be described with reference to FIGS. The basic configuration of the liquid crystal display device of this embodiment is the same as that shown in FIG.

On the insulating substrate 31, a lower light-shielding film (shaded area) which blocks light from below and serves as a common wiring for additional capacitance
32 by using impurity-doped polysilicon
It is formed with a film thickness of 00 nm so as to overlap the formation region of the source bus line. Incidentally, metal silicide may be used as the lower light-shielding film 32.

Next, an insulating film 33 made of SiO ₂ or the like is formed to a thickness of 1 μm.
It is formed with a film thickness of. Next, a polycrystalline silicon thin film 34, which will be the active layer of the TFT, is formed in a thickness of 40 nm to 80 nm so as to overlap the lower light shielding film 32. This polycrystalline silicon thin film 34 is extended to form an additional capacitance electrode 34a. The additional capacitance electrode 34a is made into a low resistance film by introducing phosphorus ions. Next, the gate insulating film 35 is formed with a film thickness of 80 nm to 150 nm by using sputtering or CVD method.

Next, a contact hole 37 for connecting the additional capacitance upper electrode 36 and the lower light-shielding film 32, which will be formed on the gate insulating film 35 later, is formed by etching the insulating film 33 and the gate insulating film 35. The lower light-shielding film 32 is exposed through the contact hole 37.

Next, the gate bus line (gate electrode) 38
Is patterned into a predetermined shape using metal or low-resistance polycrystalline silicon, and is formed at a predetermined interval so as to be orthogonal to the lower light-shielding film 32 and the polycrystalline silicon thin film 34. Further, the additional capacitance upper electrode 36 is formed of the same material as the gate bus line (gate electrode) 38 so that one end thereof covers the contact hole 37 and overlaps with the lower light shielding film 32. Then, the additional capacitor upper electrode 3
6 and the lower light shielding film 32 are electrically connected.

Thus, in addition to the first additional capacitance composed of the additional capacitance electrode 34a, the additional capacitance upper electrode 36, and the gate insulating film 35, the additional capacitance common wiring formed of the lower light-shielding film 32 and the additional capacitance electrode 34a are formed. A second additional capacitance formed by the insulating film 33 is formed. Therefore, by providing the additional capacitance in two layers in the overlapping portion of the additional capacitance common wiring 32 and the additional capacitance upper electrode 36, it is possible to obtain the desired additional capacitance in a small area and suppress the decrease in the aperture ratio. Can be done.

The voltage is supplied to the additional capacitance upper electrode 36 from the additional capacitance common wiring 32. Therefore, it is not necessary to form a wiring for supplying a voltage to the additional capacitance upper electrode 36, and it is possible to avoid a decrease in aperture ratio due to the wiring for the additional capacitance upper electrode 36.

Next, in order to determine the conductivity type of this thin film transistor, phosphorus ions are introduced from above the gate electrode 38 to form the gate electrode 3 in the polycrystalline silicon thin film 34.
A channel 39 is formed in the lower part of 8. Here, in order to make the TFT have an LDD structure, phosphorus ions are introduced into the polycrystalline silicon thin film 34 in the vicinity of the channel 39 at a concentration of 1 × 10 ¹³ cm ^-2 , and the polycrystalline silicon thin film 34 in the region outside the phosphorus ions is introduced. Phosphorus ions are introduced at a concentration of 1 × 10 ¹⁵ cm ^-2 . Thus, by forming the LDD structure TFT on the lower light-shielding film 32, the LDD structure T is caused by the light from below.
Leakage current generated in FT is prevented. Therefore, it is possible to improve the display quality by improving the off-characteristics of the LDD structure transistor.

Next, a contact hole 41 is formed after a first interlayer insulating film 40 is formed on the entire surface by a silicon oxide film. Next, the source bus line 42 is formed by using a low resistance metal such as Al so as to overlap the additional capacitance common wiring 32. Then, a second interlayer insulating film 43 having a role of a flattening film is formed of acrylic resin on the entire surface of the substrate.

Next, contact holes 44 are formed in the gate insulating film 35, the first interlayer insulating film 40 and the second interlayer insulating film 43, and then a transparent conductive film such as ITO is used,
A pixel electrode (dotted line portion in FIG. 1) 45 is formed so as to overlap the gate bus line 38 and the additional capacitance common wiring (lower light shielding film) 32. In that case, since the adjacent pixel electrodes 45, 45 are separated above the gate bus line 38 and the lower light-shielding film 32, the pixel electrode 45, the gate bus line 38, and the lower light-shielding film 32 are separated.
There is no gap between Therefore, there is no place where light leaks around the pixel electrode 45, and it is not necessary to form a new light shielding film on the counter substrate (not shown) facing the pixel electrode 45, which simplifies the manufacturing process of the counter substrate. It can be converted.

As described above, in the liquid crystal display device according to the present embodiment, the LDD structure TFT is provided below the intersection of the gate bus line 38 and the source bus line 42.
To form. Furthermore, below the source bus line 42,
Lower light-shielding film 32, TF functioning as additional capacitance common wiring
The T active layer 34, the additional capacitance electrode 34a, and the additional capacitance upper electrode 36 are formed to overlap each other. Therefore, unlike the conventional liquid crystal display device shown in FIGS. 8 and 9, the additional capacitance common line 32 and the additional capacitance do not exist in the display region surrounded by the gate bus lines 38 and the source bus lines 42. That is, according to the present embodiment, it is possible to suppress the decrease in the aperture ratio due to the additional capacitance common line 32 and the additional capacitance as much as possible.

Further, from the above, the pixel electrode 4
5 can overlap the lower light-shielding film 32 and the gate bus line 38 to be formed on substantially the entire surface of the display region, and a light-shielding film for shielding the periphery of the pixel electrode 45 is newly provided on the counter substrate. No need to form.

Below the source bus line 42, a first additional capacitance formed between the additional capacitance electrode 34a and the additional capacitance upper electrode 36, and the additional capacitance electrode 34a.
And a second additional capacitor formed between the additional capacitor common wiring (lower light shielding film) 32. Therefore, the additional capacitance having a desired capacitance can be efficiently formed in a small area. At that time, the additional capacitance upper electrode 36 is electrically connected to the additional capacitance common line 32. Therefore, it is possible to avoid a decrease in the aperture ratio due to the wiring for the additional capacitance upper electrode 36.

Further, since the LDD structure TFT is formed on the lower light-shielding film 32, the L light is applied by the light from below.
Leakage current generated in the DD structure TFT can be prevented. Therefore, it is possible to improve the display quality by improving the off characteristics of the LDD structure transistor.

<Second Embodiment> FIG. 4 is a layout diagram of one pixel in the liquid crystal display device of the present embodiment. Further, FIG. 5 shows a cross section taken along the line DD in FIG. Further, FIG. 6 shows E in FIG.
-E shows a cross section taken along the arrow. Hereinafter, the configuration and the forming procedure of the liquid crystal display device according to the present embodiment will be described with reference to FIGS.

On the insulating substrate 51, a lower light-shielding film (hatched portion) which blocks light from below and serves as a common wiring for additional capacitance
52 by means of polysilicon doped with impurities
It is formed with a film thickness of 00 nm so as to overlap the source bus line formation region. Next, a dielectric film 53 having a high relative dielectric constant such as Ta ₂ O ₅ is formed with a film thickness of 100 nm. In the present embodiment, since this dielectric film 53 is also used as the insulating film for the additional capacitance, it is preferable to use an insulating film having a higher relative dielectric constant (preferably "8" or more) than that of SiO _2. preferable.

Next, an insulating film 54 made of SiO ₂ or the like is formed to a thickness of 3 μm.
Then, wet etching and dry etching are performed to form a capacitance forming groove 55 on the lower light-shielding film 52 at a location where an additional capacitance will be formed later. As the insulating film 54, it is preferable to use SiO ₂ which has a high etching rate. In the etching process of SiO ₂ , the Ta ₂ O ₅ film 53 functions as an etch stopper. The bottom of the capacitance forming groove 55 becomes flat due to the presence of this etch stopper, and a highly reliable trench type capacitance can be formed. On the other hand, if the etch stopper is not provided, the bottom of the capacitance forming groove 55 does not become flat, and the film thickness of various thin films to be formed later in the capacitance forming groove 55 is constant at the bottom. It may not be. Further, the presence of the etch stopper does not cause overetching, and the depth of the capacitance forming groove 55 becomes constant, so that the designed additional capacitance value can be obtained.

By forming at least a part of the capacitance forming groove 55 below the source bus line 56, it is possible to prevent the aperture ratio from decreasing due to the presence of the additional capacitance. The capacitance forming groove 55 is formed into a tapered shape by, for example, wet etching the upper opening to prevent disconnection of the polycrystalline silicon thin film 57 and the source bus line 56 which will be formed on the upper portion later. it can.

Next, a polycrystalline silicon thin film 57 to be an active layer of the TFT is formed on the lower light-shielding film 52 with a film thickness of 40 nm to 80 nm.
Are formed by overlapping. The polycrystalline silicon thin film 57 is extended to the inside of the capacitance forming groove 55 to form the additional capacitance electrode 57a. The additional capacitance electrode 5
A low resistance film is formed by introducing phosphorus ions into 7a. As described above, the capacitance between the additional capacitance electrode 57a and the lower light-shielding film 52 which is the additional capacitance common wiring becomes the additional capacitance. Next, sputtering or CVD
Then, the gate insulating film 58 is formed with a film thickness of 80 nm to 150 nm.

Next, a contact hole 60 for connecting the additional capacitance upper electrode 59 and the additional capacitance common wiring (lower light shielding film) 52 which will be formed on the gate insulating film 58 later.
Are formed by etching the insulating film 54 and the gate insulating film 58, and the additional capacitance common line 52 is exposed through the contact hole 60. In this etching step, it is necessary to remove the dielectric (Ta ₂ O ₅ ) film 53 after etching the insulating film (SiO ₂ ) 54.

Next, the gate bus line (gate electrode) 61
Is patterned into a predetermined shape using metal or low-resistance polycrystalline silicon, and is formed at a predetermined interval so as to be orthogonal to the lower light-shielding film 52 and the polycrystalline silicon thin film 57. Further, the additional capacitance upper electrode 59 is formed of the same material as the gate bus line (gate electrode) 61 so as to cover the capacitance forming groove 55 and the contact hole 60. Then, the additional capacitance upper electrode 59 and the additional capacitance common wiring (lower light shielding film) 52 are electrically connected. In this way, a double-layered additional capacitance is formed at the overlapping portion of the additional capacitance electrode 57a, the additional capacitance upper electrode 59, and the additional capacitance common wiring 52. As described above, by forming the additional capacitance by arranging the additional capacitance electrodes 57a in parallel above and below, it is possible to form a desired capacitance in a small area, and it is possible to suppress a decrease in the aperture ratio.

At this time, since the additional capacitance upper electrode 59 is electrically connected to the additional capacitance common wiring (lower light shielding film) 52, the reduction of the aperture ratio due to the wiring for the additional capacitance upper electrode 59 is avoided. be able to.

Next, in order to determine the conductivity type of this thin film transistor, phosphorus ions are introduced from above the gate electrode 61, and the gate electrode 6 in the polycrystalline silicon thin film 57 is formed.
A channel 62 is formed in the lower part of 1. Here, in order to make the TFT have an LDD structure, phosphorus ions are introduced into the polycrystalline silicon thin film 57 in the vicinity of the channel 62 at a concentration of 1 × 10 ¹³ cm ⁻² , and the polycrystalline silicon thin film 57 in the region outside thereof is introduced. Phosphorus ions are introduced at a concentration of 1 × 10 ¹⁵ cm ^-2 . Thus, by forming the LDD structure TFT on the lower light-shielding film 52, the LDD structure T is caused by the light from below.
It is possible to prevent the leak current generated in the FT and improve the display quality.

Next, a contact hole 64 is formed after the first interlayer insulating film 63 is formed on the entire surface with a silicon oxide film. Next, the source bus line 56 is formed by using a low resistance metal such as Al so as to overlap the additional capacitance common wiring 52. Then, a second interlayer insulating film 65 having a function of a flattening film is formed of acrylic resin on the entire surface of the substrate.

Next, contact holes 66 are formed in the gate insulating film 58, the first interlayer insulating film 63 and the second interlayer insulating film 65. Next, using a transparent conductive film such as ITO, a pixel electrode (dotted line portion in FIG. 4) 67 is formed so that the edge overlaps the gate bus line 61 and the additional capacitance common wiring (lower light shielding film) 52. In that case,
Adjacent pixel electrodes 67, 67 are connected to the gate bus line 61.
Further, since it is separated above the lower light shielding film 52, there is no gap between the pixel electrode 67 and the gate bus line 61. Therefore, there is no place where light leaks around the pixel electrode 67, and a counter substrate (not shown) facing the pixel electrode 67.
It is not necessary to form a sharp light-shielding film on the top, and the manufacturing process of the counter substrate can be simplified.

As described above, in the liquid crystal display device according to the present embodiment, the TFT having the LDD structure is provided below the intersection of the gate bus line 61 and the source bus line 56.
To form. Furthermore, below the source bus line 56,
Lower light-shielding film 52, TF functioning as additional capacitance common wiring
The T active layer 57, the additional capacitance electrode 57a and the additional capacitance upper electrode 59 are formed so as to substantially overlap each other. Therefore, unlike the conventional liquid crystal display device shown in FIGS. 8 and 9, the additional capacitance common line 52 and the additional capacitance do not exist in the display region surrounded by the gate bus line 61 and the source bus line 56. That is, according to the present embodiment, it is possible to suppress the decrease in the aperture ratio due to the additional capacitance common wiring 52 and the additional capacitance as much as possible.

Further, from the above, as in the first embodiment, the pixel electrode 67 can be formed on the lower surface of the lower light-shielding film 52 and the gate bus line 61 over substantially the entire display area. Therefore, it is not necessary to newly form a light-shielding film for shielding the periphery of the pixel electrode 67 on the counter substrate.

Further, an additional capacitance is formed by overlapping the inner wall portion and the lower portion of the capacitance forming groove 55. Therefore, a desired additional capacitance can be efficiently formed in a small area. At that time, the additional capacitance upper electrode 59 is electrically connected to the additional capacitance common wiring 52. Therefore, it is possible to avoid a decrease in the aperture ratio due to the wiring for the additional capacitor upper electrode 59. Further, since the capacitance forming groove 55 is formed below the source bus line 56, the aperture ratio does not decrease due to the additional capacitance formed on the inner wall portion and the lower portion of the capacitance forming groove 55. Even if the capacitance forming groove 55 is formed so as to protrude from the source bus line 52, only the protruding portion reduces the aperture ratio.

Further, since the LDD structure TFT is formed on the lower light-shielding film 52, the L light is applied by the light from below.
Leakage current generated in the DD structure TFT can be prevented. Therefore, the off-characteristics of the LDD structure transistor can be improved and the display quality can be improved.

Below the insulating film 54 in which the capacitance forming groove 55 is formed, a dielectric film 53 made of an insulating film having a slower etching rate and a higher relative dielectric constant than the insulating film 54.
Is formed. Therefore, when the insulating film 54 is etched to form the capacitance forming groove 55, the dielectric film 53 functions as an etch stopper to flatten the bottom of the capacitance forming groove 55. That is, according to the present embodiment, it is possible to form a highly reliable trench-type capacitor having no variation in capacitance value.

[0052]

As apparent from above, according to the present invention, a liquid crystal display device of the first invention, which has a biasing pressure capacity, a groove is formed in the insulating film formed in the lower region of the gate bus line or a source bus line Then, an additional capacitance upper electrode is formed so as to cover the groove, the end of the drain of the transistor is extended along the inner wall of the groove, and the extension of the drain and the upper portion of the additional capacitance at least on the inner wall of the groove are formed. Since the additional capacitance is formed with the electrodes, the additional capacitance exhibiting a desired capacitance can be efficiently formed in a small area so as to overlap the bus line. Therefore, it is possible to suppress a decrease in the aperture ratio due to the additional capacitance.

Further , the additional capacitance common wiring is formed in the lower region of the insulating film so as to overlap the gate bus line or the source bus line, and the additional capacitance common wiring is formed between the extension portion of the drain and the additional capacitance common wiring. Since the additional capacitance of 2 is formed, in addition to the additional capacitance described above, an additional capacitance exhibiting a desired capacitance in a small area can be obtained, and a reduction in the aperture ratio due to the additional capacitance can be suppressed. further,
If the additional capacitance common wiring also serves as the lower light-shielding film, the light from below the transistor can be blocked. In this way, leakage current generated in the transistor due to light can be prevented.

The liquid crystal display device of the first invention is
If the additional capacitance common wiring is electrically connected to the additional capacitance upper electrode, it is not necessary to form a new wiring for applying a voltage to the additional capacitance upper electrode. Therefore,
Ru can avoid a decrease in aperture ratio due to the wiring for the additional capacitor upper electrode.

[0055] Also, the liquid crystal display device of the second invention, which has an additional capacity, the additional capacitance is formed in the inner wall portion of the groove provided in the insulating film, etching stopper at the bottom of the groove Since the groove is formed, the depth of the groove is set to a predetermined value when the groove is formed by etching, and it is possible to obtain a trench-type additional capacitance having no variation in capacitance value. Furthermore, since the bottom of the groove is flattened by the presence of the etch stopper, it is possible to obtain an additional capacitance having a highly reliable capacitance value.

Further , since the additional capacitance lower electrode is provided below the etch stopper and the second additional capacitance is formed by using the additional capacitance lower electrode and the etch stopper, the additional capacitance lower electrode is added to the inner wall portion and the lower portion of the groove. Capacitance can be formed. Thus, it is possible to obtain additional capacity efficiently desired capacity in a small area, Ru can suppress a decrease in aperture ratio due to the additional capacitance.

[0057] Further, the additional capacitor lower electrode and the other additional capacitor lower electrode common to form the additional capacitor common line
Therefore , the process for forming the individual additional capacitance lower electrodes is unnecessary, and the process for forming the additional capacitance lower electrodes can be simplified.

Further , the additional capacitance common wiring is formed in the lower region of the channel portion so as to overlap the source bus line, and also serves as a lower light shielding film .
Thus, light from below the transistor can be blocked. Thus, Ru prevents leakage current generated in the transistor by light.

[Brief description of drawings]

FIG. 1 is a layout diagram of one pixel in a liquid crystal display device of the present invention.

FIG. 2 is a sectional view taken along the line BB in FIG.

3 is a cross-sectional view taken along the line CC in FIG.

FIG. 4 is a pixel 1 in a liquid crystal display device different from that in FIG.
It is a layout diagram for each piece.

5 is a cross-sectional view taken along the line DD in FIG.

6 is a cross-sectional view taken along the line EE in FIG.

FIG. 7 is a schematic plan view of a driver-integrated liquid crystal display device.

FIG. 8 is a layout diagram of one pixel in FIG.

9 is a cross-sectional view taken along the line AA in FIG.

[Explanation of symbols]

31, 51 ... Insulating substrate, 32, 52 ... Lower light-shielding film (common wiring for additional capacitance), 33, 54 ... Insulating film,
34, 57 ... Polycrystalline silicon thin film, 34a, 57a ... Additional capacitance electrode, 35, 58 ... Gate insulating film, 36, 5
9 ... Additional capacitance upper electrode, 37, 41, 44, 60, 64, 6
6 ... Contact hole, 38, 61 ... Gate bus line
(Gate electrode), 39, 62 ... Channel,
40, 63 ... First interlayer insulating film, 42, 56 ... Source bus line, 43, 65 ... Second interlayer insulating film, 45, 67
... Pixel electrode, 53 ... Dielectric film, 55 ...
Groove for capacity formation.

Continuation of the front page (56) Reference JP 10-10548 (JP, A) JP 3-80225 (JP, A) JP 7-146491 (JP, A) JP 9-26601 (JP , A) JP 9-160074 (JP, A) JP 2000-98409 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1368 G09F 9/30 338 G09F 9/30 349

Claims (3)

(57) [Claims] 1. A gate bus line, a source bus line,
Additional capacitance, above gate bus line and source bus line
Transistor located near the intersection of
A first substrate on which a pixel electrode connected to the
A second substrate on which a counter electrode facing the pixel electrode is formed;
And a liquid crystal material between the first substrate and the second substrate.
In the sandwiched liquid crystal display device, below the gate bus line or source bus line
A groove formed in the insulating film formed in the region and an additional capacitance upper electrode formed so as to cover the groove.
In addition, the drain end of the transistor has a groove on the insulating film.
Extending along the inner wall of the drain and extending of the drain at least on the inner wall of the groove.
The above-mentioned additional capacitance between the section and the upper electrode of the additional capacitance.
In the lower region of the insulating film, an additional capacitance common line that overlaps with the gate bus line or the source bus line and also serves as a lower light-shielding film is formed. Second with the wiring
A liquid crystal display device characterized by forming an additional capacitance of. 2. The liquid crystal display device according to claim 1 , wherein the additional capacitance common line is electrically connected to the additional capacitance upper electrode. 3. A gate bus line, a source bus line,
Additional capacitance, above gate bus line and source bus line
Transistor located near the intersection of
A first substrate on which a pixel electrode connected to the
A second substrate on which a counter electrode facing the pixel electrode is formed;
And a liquid crystal material between the first substrate and the second substrate.
In the sandwiched liquid crystal display device, the additional capacitance is formed on the inner wall portion of the groove provided in the insulating film.
An etch stopper is formed at the bottom of the groove, and the etch stopper is formed under the etch stopper in common with other additional capacitors.
Comprise made the additional capacitor common line, by using the above-described additional capacitor common line and etch stopper, the
2 additional capacitance is formed, and the additional capacitance common line is formed in the lower region of the channel portion of the transistor so as to overlap the source bus line and also serves as a lower light-shielding film. Liquid crystal display device.