JP2003262881A - Liquid crystal device, method for manufacturing the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal device wherein an alignment defect is reduced to the utmost, as the liquid crystal device of an active matrix driving system driven by a TFT. <P>SOLUTION: The liquid crystal device (100) is provided with a liquid crystal layer (50) interposed between a pair of substrates, and a pixel electrode (11) provided on a TFT array substrate (10) in a matrix shape. A step part consisting of a step portion swelled by a light shielding film (11a) and a scanning line (3a), and a hollow portion formed in a first interlayer insulating film (12'), is formed on the surface of a third interlayer insulating film of the TFT array substrate (10), and pixel electrodes (9a) adjacent to each other are formed on the respective step parts. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technical field of an active matrix driving type liquid crystal device driven by a thin film transistor (hereinafter referred to as TFT), a method of manufacturing the same, and an electronic device using the same.

[0002]

2. Description of the Related Art Conventionally, in this type of liquid crystal device, a pair of alignment films, each of which is rubbed in a predetermined direction, is provided on a pixel electrode and a counter electrode between a pair of substrates. Liquid crystals are sandwiched between the films in a predetermined alignment state. Then, during operation, an electric field is applied to the liquid crystal from both electrodes, the alignment state of the liquid crystal is changed, and display is performed within the screen display area of the liquid crystal device.

Therefore, in this type of liquid crystal device, an area in which wirings such as data lines, scanning lines, and capacitance lines are formed,
The unevenness due to the difference in the total layer thickness on the TFT array substrate from the area where these data lines and the like are not formed (particularly the opening area through which the incident light for image display passes) is assumed to be the surface that directly contacts the liquid crystal (alignment). If it is left even in the film, alignment failure (disclination) occurs in the liquid crystal depending on the degree of the unevenness, which leads to deterioration of the image of each pixel. More specifically, when the rubbing treatment is applied to the alignment film formed on the concave and convex surface in which each opening region is depressed, the alignment regulating force varies on the alignment film surface depending on the concave and convex. In the uneven portion, the liquid crystal alignment defect occurs and the contrast changes. That is, when the liquid crystal alignment defect occurs, for example, in the normally white mode in which white display is performed when the liquid crystal voltage is not applied, a white spot phenomenon occurs at the alignment defect portion, and the contrast and the definition also decrease. Resulting in. In order to avoid such a situation, in order to keep the distance between the alignment films (the thickness of the liquid crystal layer) at a predetermined value and to perform the rubbing process on the alignment film uniformly and appropriately over the entire surface of the substrate, the screen display It is important to flatten the pixel portion located in the area.

On the other hand, in this type of liquid crystal device, in order to prevent flicker and crosstalk from occurring even if the duty ratio when supplying an image signal to each pixel electrode is small, a predetermined capacitance is applied to each pixel electrode. The storage capacity for providing

In this type of liquid crystal device, there is also a demand for increasing the pixel aperture ratio to make the screen brighter. Therefore, in order to increase the storage capacity, the liquid crystal device is provided on the opposite substrate as a boundary between adjacent pixels. The storage capacitor as described above may be formed under the data line made of non-transparent Al (aluminum) or the like at a position corresponding to the light shielding layer to be formed or in a region along the data line. More specifically, for example, in the region under the data line, a semiconductor layer extending from the semiconductor layer forming the TFT in the pixel portion to under the data line is formed as a first storage capacitor electrode, and a gate insulating film is formed. An insulating film made of the same film is formed on the first storage capacitor electrode, and a capacitor line made of low resistance polysilicon or the like in the same layer as the scanning line and arranged along the scanning line is extended on the insulating film. The second storage capacitor electrode is provided so as to face the first storage capacitor electrode via the insulating film. Alternatively, in a region along the scanning line, the semiconductor layer extending below the capacitance line from the semiconductor layer forming the TFT in the pixel portion is formed as the first storage capacitance electrode and is made of the same film as the gate insulating film. An insulating film is formed on the first storage capacitor electrode (in this case, the portion of the capacitance line facing the first storage capacitor electrode via the insulating film is the second
Functions as a storage capacitor electrode).

High-definition image display is possible by sufficiently taking such storage capacity.

[0007]

However, if the storage capacitor is formed in the region below the data line or the region along the scanning line as described above, the layer thickness of this portion increases and the pixel portion is relatively large. There will be a step. For example, when a storage capacitor is formed in a region below the data line, only the thickness of the storage capacitor (the total thickness of the first storage capacitor electrode, the insulating film, and the second storage capacitor electrode) and the thickness of the data line do not exist. It will be higher than the pixel section. If there is such a step, the rubbing process cannot be properly performed at the step portion.
As a result, the above-mentioned liquid crystal alignment defects occur along the data lines, and there arises a problem that contrast and definition are lowered.

The present invention has been made in view of the above-mentioned problems, and provides a liquid crystal device in which liquid crystal misalignment leading to image quality deterioration is reduced as much as possible, a method of manufacturing the same, and an electronic apparatus including the liquid crystal device. The task is to do.

[0009]

In order to solve the above-mentioned problems, the liquid crystal device of the present invention comprises a pair of substrates filled with liquid crystal, and a plurality of data lines are formed on one substrate of the pair of substrates. A plurality of scanning lines intersecting the plurality of data lines, a plurality of thin film transistors provided corresponding to the intersections of the plurality of data lines and the scanning lines, and the data lines provided corresponding to the plurality of thin film transistors. A plurality of pixel electrodes arranged above and an alignment film formed on the pixel electrodes are provided, and in the adjacent pixel electrodes, the surface of the insulating film under the pixel electrodes is a convex raised portion. And a step portion formed of the raised portion and a step portion formed of a concave portion on the surface of the insulating film below the pixel electrode, and the edge of one pixel electrode of the adjacent pixel electrodes. Is the raised part While the position to the upper surface of the step portion formed of the edges of the other pixel electrode of the adjacent pixel electrodes is characterized in that position to the step portion formed of the recessed portion.

The adjacent pixel electrodes may be formed so as to sandwich the scanning line.

The liquid crystal may be driven by a scanning line inversion driving method in which the polarity of the voltage applied to both ends of the liquid crystal is inverted for each scanning line.

Further, it is preferable that the alignment film is rubbed in a direction from a step portion formed of the raised portion to a step portion formed of the recessed portion.

Further, it is preferable that a light-shielding film is formed in a region facing the step portion formed of the depression.

Further, the step portion formed by the raised portion is
It may be formed by the wiring formed in the lower layer.

Further, it is preferable that the step portion formed by the recess is formed by recessing the lower insulating film in a concave shape.

Further, it is preferable that the surface of the insulating film under the adjacent pixel electrodes formed so as to sandwich the data line is flattened.

In order to solve the above problems, the liquid crystal device manufacturing method of the present invention comprises a pair of substrates filled with liquid crystal, and a plurality of data lines are provided on one of the pair of substrates. A plurality of scanning lines intersecting the plurality of data lines, a plurality of thin film transistors provided corresponding to the intersection of the plurality of data lines and the scanning lines, and a plurality of data lines provided corresponding to the plurality of thin film transistors. A method of manufacturing a liquid crystal device comprising a plurality of pixel electrodes arranged above and an alignment film formed on the pixel electrode, wherein the surface of the insulating film under the pixel electrode is adjacent to the pixel electrode. A step of forming a step portion formed of a convex raised portion, and a step of forming a step portion formed of a concave portion in which the surface of the insulating film below the pixel electrode is continuous with the step portion formed of the raised portion,
The edge of one pixel electrode of the adjacent pixel electrodes is located up to the upper surface of the step portion formed of the raised portion, and the edge of the other pixel electrode of the adjacent pixel electrode is located up to the step portion formed of the recessed portion. Thus, the process of forming the pixel electrode is provided.

The electronic equipment of the present invention is characterized by comprising the above liquid crystal device in order to solve the above problems.

According to this electronic apparatus, the electronic apparatus includes the above-described liquid crystal device of the present invention, and high-quality image display can be performed by the liquid crystal device with few liquid crystal alignment defects.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Liquid Crystal Device) The configuration and operation of the first embodiment of the liquid crystal device according to the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is a plan view of a pixel portion in an opening region of a TFT array substrate in which a data line, a scanning line, a pixel electrode, a light shielding film, etc. are formed. Figure 2
[FIG. 4] is a plan view of a connecting portion between a light shielding film and a constant potential line. FIG. 3 is a cross-sectional view of the liquid crystal device showing the cross section AA ′ of FIG. 1 together with a counter substrate and the like. 4 is a sectional view taken along the line BB ′ of FIG. 1, and FIG. 5 is a sectional view taken along the line CC ′ of FIG. See also FIG.
FIG. 3 is a sectional view taken along line DD ′ of FIG. 2. 3 to 6, the scales of the layers and members are different from each other in order to make the layers and members recognizable in the drawings.

In FIG. 1, a plurality of transparent pixel electrodes 9a are arranged in a matrix on the TFT array substrate of the liquid crystal device.
(The outline is shown by a dotted line portion 9a '), and the data line 6a (source electrode), the scanning line 3a (gate electrode), and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. It is provided. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film through the contact hole 5a, and the pixel electrode 9a is later described through the contact hole 8 of the semiconductor layer 1a. Is electrically connected to the drain region of the. Further, a scanning line 3a (gate electrode) is arranged so as to face a channel forming region 1a ′ (a region of a diagonal line descending to the right in the drawing) of the semiconductor layer 1a, which will be described later. Then, the light-shielding film 11a in the pixel portion is provided in the region shown by the diagonal lines rising to the right in the figure. That is, the light shielding film 11a is
In the pixel portion, the channel forming region 1 of the semiconductor layer 1a
The TFT including a ', the data line 6a, the scanning line 3a, and the capacitance line 3b are provided at positions overlapping with each other when viewed from the TFT array substrate side.

In FIG. 1, in particular, in a region surrounded by a thick line including the capacitance line 3b formed below the data line 6a, a first interlayer insulating film described later is formed in a concave shape, and the other regions are formed. In a region substantially corresponding to the pixel electrode 9a and the scanning line 3a, the first interlayer insulating film is formed to be relatively convex (planar). In addition, if the rubbing direction of the TFT array substrate 10 is the direction of the arrow in FIG. 1, the present embodiment is particularly effective.

Therefore, conventionally, the rubbing process cannot be properly performed due to a step in which the alignment film forming surface on which the data line is formed becomes the highest, or the distance between the substrates due to such a step is reduced. The misalignment of the liquid crystal caused directly by the deviation is most likely to occur in the part along the data line in the opening region, but according to the present embodiment, the misalignment in this part can be reduced by flattening.

In FIG. 2, on the TFT array substrate of the liquid crystal device, a constant potential line 6b formed of the same conductive layer as the data line 6a such as Al is provided, and in the non-pixel portion via the contact hole 5b. Light-shielding film (light-shielding wiring) 11
It is connected to b. In particular, in FIG. 2, in a region 5C surrounded by a thick line including the contact hole 5b, a later-described first interlayer insulating film is recessed and formed, and in other regions, the first interlayer insulating film is formed. Are relatively convex (planar).

As shown in FIGS. 3 to 6, the liquid crystal device 10
Reference numeral 0 includes a TFT array substrate 10 that constitutes an example of one transparent substrate, and a counter substrate 20 that constitutes an example of the other transparent substrate that is arranged to face the TFT array substrate 10. The TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 2
0 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 19 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 19 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, the counter substrate 20 is provided with a counter electrode (common electrode) 21 over the entire surface thereof, and on the lower side thereof, an alignment film 22 subjected to a predetermined alignment treatment such as rubbing treatment. Is provided. The counter electrode 21 is, for example, I
It consists of a transparent conductive thin film such as a TO film. In addition, the alignment film 22
Is an organic thin film such as a polyimide thin film.

As shown in FIG. 3, on the TFT array substrate 10, each pixel electrode 9 is provided at a position adjacent to each pixel electrode 9a.
Pixel switching TFT3 for switching control of a
0 is provided.

As shown in FIG. 3, the counter substrate 20 is further provided with a light shielding layer 23 in a region other than the opening region of each pixel. Therefore, incident light does not enter the channel forming region 1a ′ and LDD (Lightly Doped Drain) regions 1b and 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Furthermore, the light shielding layer 2
3 has functions of improving contrast, preventing color mixture of color materials, and the like.

A seal member 52, which will be described later, is provided between the TFT array substrate 10 and the counter substrate 20 which are arranged in this manner and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other.
Liquid crystal is enclosed in a space surrounded by (see FIGS. 13 and 14) to form a liquid crystal layer 50. The liquid crystal layer 50 adopts a predetermined alignment state by the alignment films 19 and 22 in a state where the electric field from the pixel electrode 9a is not applied. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material 52 is an adhesive for bonding the two substrates 10 and 20 around them and is made of, for example, a photo-curing resin or a thermosetting resin, and is used to set the distance between the two substrates to a predetermined value. A spacer such as glass fiber or glass beads is mixed.

As shown in FIG. 3, the pixel switching T
Light-shielding films 11a are provided between the TFT array substrate 10 and the pixel switching TFTs 30 at positions facing the FTs 30, respectively. The light shielding film 11a is preferably an opaque refractory metal such as Ti, Cr, W or T.
It is composed of a metal simple substance, an alloy, a metal silicide or the like containing at least one of a, Mo and Pd. With such a material, it is possible to prevent the light shielding film 11a from being destroyed or melted by the high temperature process in the process of forming the pixel switching TFT 30 performed after the process of forming the light shielding film 11a on the TFT array substrate 10. Since the light shielding film 11a is formed, the TFT array substrate 10
It is possible to prevent the return light or the like from the side from entering the channel forming region 1a ′ and the LDD regions 1b and 1c of the pixel switching TFT 30, and the characteristics of the pixel switching TFT 30 deteriorate due to the generation of photocurrent. There is nothing to do.

Further, a first interlayer insulating film 12 'consisting of a single layer or multiple layers is provided between the light shielding film 11a and the plurality of pixel switching TFTs 30. The first interlayer insulating film 12 'is provided to electrically insulate the semiconductor layer 1a forming the pixel switching TFT 30 from the light shielding film 11a. Further, the first interlayer insulating film 12 'is
By being formed on the entire surface of the TFT array substrate 10,
It also has a function as a base film for the pixel switching TFT 30. That is, it has a function of preventing the characteristics of the pixel switching TFT 30 from deteriorating due to the roughness of the surface of the TFT array substrate 10 during polishing, the stain remaining after cleaning, and the like.

Here, as shown in FIG. 4 and FIG. 5, particularly, in the first interlayer insulating film 12 ′, the region on the TFT array substrate 10 where the capacitance line 3 b is formed has a concave shape as compared with other regions. It is formed as a depression. As described later, the first interlayer insulating film 12 ′ may be composed of a single layer portion and a two layer portion, or may be composed of only a single layer.

Such a first interlayer insulating film 12 'is formed of, for example, NSG (non-doped silicate glass) or PSG.
(Phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphosilicate glass), or other high insulating glass, or a silicon oxide film, a silicon nitride film, or the like.

The first interlayer insulating film 1 configured as described above
2'allows the TF for pixel switching from the light shielding film 11a.
It is possible to electrically insulate T30 and the like and prevent the light shielding film 11a from contaminating the pixel switching TFT 30 and the like. Here, in particular, the first interlayer insulating film 12 ′ is formed to be recessed in a region where the capacitance line (second storage capacitance electrode) 3 b is formed below the data line 6 a (see FIG. 4) and the scanning line. Since the capacitor line 3b is formed in a concave shape along the region 3a (see FIG. 5), the first interlayer insulating film is formed flat and the capacitor line 3b is formed on the first interlayer insulating film. Compared with the case where the concave portion is depressed, the difference in the total layer thickness between the region where the capacitance line 3b is formed and the region where the capacitance line 3b is not formed is reduced according to the depth of the concave portion, and the planarization in the pixel portion is reduced. Be promoted.

For example, in FIG. 4, the first interlayer insulating film 1
A light-shielding film (third storage capacitor electrode) 11a on 2 ', a first storage capacitor electrode 1f extending from the drain region 1e of the semiconductor layer 1a, a capacitor forming insulating film (gate insulating film) 2, a capacitor line 3b, and If the depth of the recessed portion is set to be equal to the total layer thickness of the data line 6a, the third interlayer insulating film 7
Since the upper surface of is flat, the subsequent flattening process can be omitted. Alternatively, if it is recessed to some extent, the burden of the subsequent flattening process can be reduced. Similarly, in FIG. 5, the light shielding film 11a on the first interlayer insulating film 12 ', the first storage capacitor electrode 1f extending from the drain region 1e of the semiconductor layer 1a, the capacitor forming insulating film 2, the capacitor line 3b, and If the depth of the recessed portion is set so as to be equal to the total layer thickness of the data line 6a, the upper surface of the third interlayer insulating film 7 becomes substantially flat (the data line 6a is larger than the pixel portion). Lower). However, in FIGS. 4 and 5, the first interlayer insulating film 1
2 ′ may be formed in a concave shape with a depth corresponding to the total layer thickness of the light shielding film 11a, the first storage capacitor electrode 1f, the capacitance forming insulating film 2 and the capacitor line 3b. If the first interlayer insulating film 12 ′ is formed in this way, the upper surface of the third interlayer insulating film 7 in FIG. 5 becomes flat, and becomes substantially flat in FIG. 4 (the data line 6 a corresponds to the upper surface of the pixel portion). Will also be higher).

In this embodiment, as shown in FIG. 5, the pixel electrode 9 formed on the TFT array substrate 10 is used.
The rubbing direction with respect to the alignment film on a is the scanning line 3 with respect to the pair of scanning lines 3a and the capacitance line 3b which are adjacently arranged.
The direction is along the data line 6a from the side of a to the side of the capacitance line 3b. In general, when the rotary rubbing method is used, the rubbing process is relatively well performed on a step having a high surface in the rubbing direction, and the rubbing process is well performed on a step having a low surface in the rubbing direction. It has been found as a result of research by the present inventor that this is difficult. Therefore, as in the present embodiment, if the rubbing process is performed in the direction from the side of the scan line 3a which is not flattened to the side of the capacitance line 3b which is flattened, the upstream of the rubbing direction is obtained. The step S1 at one edge of the scanning line 3a on the pixel side located at is a step in which the surface becomes higher in the rubbing direction, so that the alignment regulating force is strong and the rubbing process is performed well. On the other hand, the scanning line 3a on the side adjacent to the capacitance line 3b
Since the step S2 at the other edge is a step whose surface is lowered in the rubbing direction, the alignment regulating force is weak and the rubbing process is not performed well. However, there is a flattened surface (small step S3) located above the capacitance line 3b between the step S2 and the pixel located downstream in the rubbing direction, and one strip of the light shielding layer 23 is present. Thus, since the pair of scanning lines 3a and the capacitance lines 3b are covered together, the step S2 is far away from the opening region. Therefore, even if the rubbing process is not favorably performed in the step S2, the alignment defect of the liquid crystal due to the rubbing process hardly affects the image. If the rubbing process is performed in the opposite direction, the level difference S in which the surface becomes lower in the rubbing direction.
The misalignment of the liquid crystal due to 1 may affect the image, or the opening region must be narrowed by further covering such a portion with the light shielding layer 23. Therefore, in such a case, the capacitance line 3b may be provided on the opposite side of the scanning line 3a in FIG.

Further, since the rubbing process is performed in this manner, in the present embodiment, when rubbing along the data lines, the liquid crystal is not deteriorated by the direct current drive and the flicker of the display image is prevented. Therefore, it is advantageous to use the scanning line inversion driving method (1H inversion driving method) in which the polarity of the voltage applied to both ends of the liquid crystal is inverted for each scanning line. That is, in general, a liquid crystal alignment defect (disclination) is likely to occur due to a step difference in the pixel portion near the scanning line, which is a step difference in the direction of the data line.

Here, as an example of such a liquid crystal alignment defect, the disclination due to the influence of the lateral electric field in the TN liquid crystal will be described with reference to FIGS. FIG. 7 shows three scanning lines and three data for the DOT (pixel) inversion driving method, the 1H (row) inversion driving method, the 1S (column) inversion driving method, and the 1V (frame) inversion driving method in order from the top. The figure shows the state of disclination in the four pixel aperture areas surrounded by the lines. Especially, the left column shows the counterclockwise TN liquid crystal and the right column shows the clockwise TN liquid crystal.
The disclination state of the liquid crystal is shown by the display of the liquid crystal device viewed from the counter substrate side. In FIG. 7, the region where disclination is generated by the lateral electric field is shown by the diagonally-downward portion in the lower left direction. In addition to this, the region in which misalignment is caused by the step difference in the data line is in the lower-right diagonal portion. Indicated by. Further, in this example, the rubbing direction with respect to the alignment film on the TFT array substrate is from the bottom to the top in the figure.

As shown in FIG. 7, liquid crystal misalignment occurs due to the step of the data line in a narrow area along the left and right of the data line regardless of whether it is counterclockwise or clockwise. In the case of the DOT inversion driving method (see the uppermost row in the figure), in the counterclockwise liquid crystal, the disclination due to the horizontal electric field occurs on the upper side of each scanning line and the right side of each data line. In the above, the disclination due to the horizontal electric field occurs on the upper side of each scanning line and the left side of each data line. On the other hand, in the case of the 1S inversion drive method (method in which the polarity of the voltage applied to both ends of the liquid crystal is inverted in units of data lines) (see the third row from the top in the figure), the counterclockwise liquid crystal has the right side of each data line. In the right-handed liquid crystal, a small amount of disclination due to the horizontal electric field is generated on the left side of each data line.
In the case of the 1V inversion driving method (the method in which the polarity of the voltage applied to both ends of the liquid crystal is inverted every frame or vertical scanning period) (see the bottom in the figure), the disclination by the horizontal electric field is the scanning line. Has hardly occurred above and below.

On the other hand, in the case of the 1H inversion driving method (see the second step from the top in the figure), the disclination due to the horizontal electric field occurs above each scanning line regardless of clockwise or counterclockwise rotation. is doing. Therefore, as shown in FIG.
With the rubbing direction of the alignment film on the T-array substrate from the bottom to the top, the capacitance lines are provided side by side in the region above the scanning lines where disclination due to the horizontal electric field occurs, and the steps of the scanning lines are formed with these capacitance lines. If it is arranged so as to be located between the scanning line and the scanning line, the disclination due to the lateral electric field will be mainly generated between the capacitance line and the scanning line, and the adverse effect on the pixel opening region will be reduced. become. Further, it can be seen from FIG. 7 that by flattening the data line portion, it is possible to reduce the alignment defect of the liquid crystal appearing along the data line in any inversion driving method.

Therefore, in this embodiment, the data line 6a is used.
The step in the direction is arranged not between the edges of the pair of scanning lines 3a and the capacitance lines 3b but between the pair of scanning lines 3a and the capacitance lines 3b. Therefore, when the scanning line inversion driving method (1H inversion driving method) is adopted, the alignment failure of the liquid crystal occurs near the center of the pixel boundary region covered with the light shielding layer 23.
That is, it occurs in a region apart from each pixel aperture region. As a result, according to the present embodiment, when the scanning line inversion driving method is used, it is possible to reduce the influence of the alignment defect of the liquid crystal along the scanning line 3a, which occurs due to the voltage polarity inversion, on the display image. Higher contrast and higher definition can be achieved.

As described above, since the predetermined region of the first interlayer insulating film 12 'which is required by providing the light shielding film 11a is formed in a concave shape, according to the present embodiment, the above-mentioned conventional method is used. The step of forming the flattened insulating film by applying the flattening film by spin coating or the like can be omitted or simplified.

In the present embodiment, as shown in FIGS. 1 and 4, the high-concentration drain region 1e of the semiconductor layer 1a is extended along the data line 6a to form the first storage capacitor electrode (semiconductor layer) 1f. Has been done. Therefore, first, the first storage capacitance electrode (semiconductor layer) 1f and the capacitance line (second storage capacitance electrode) 3
A storage capacitor is formed between the capacitor b and the insulating film 2b via the capacitor forming insulating film 2. In addition to this, the light-shielding film 11a is provided with the first storage capacitor electrode (semiconductor layer) 1 extending below the data line 6a.
Since it is also provided under f, a capacitor is formed between the first storage capacitor electrode (semiconductor layer) 1f and the light shielding film 11a via the first interlayer insulating film 12 '.

On the other hand, as shown in FIGS. 1 and 5, the high-concentration drain region 1e of the semiconductor layer 1a is extended in parallel with the scanning line 3a to serve as the first storage capacitor electrode (semiconductor layer) 1f. There is. Therefore, first, between the first storage capacitance electrode (semiconductor layer) 1f and the capacitance line (second storage capacitance electrode) 3b,
A storage capacitor is formed via the capacitance forming insulating film 2. In addition to this, since the light-shielding film 11a is also provided under the first storage capacitance electrode (semiconductor layer) 1f, the first storage capacitance electrode (semiconductor layer) 1f and the light-shielding film (third storage capacitance) are formed. A capacitor is formed between the electrode) 11a and the first interlayer insulating film 12 '.

As a result, the storage capacitance of the pixel electrode 9a can be increased by effectively utilizing the space below the opening region, which is the region under the data line 6a and the region parallel to the data line.

In the present embodiment, as shown in FIGS. 1, 4 and 5, the first interlayer insulating film 12 'is formed in a concave shape in the region where these capacitors are formed, and is therefore flat. In addition, the layer thickness in the recessed region of the first interlayer insulating film 12 ′ serving as the capacitance forming insulating film is very thin (for example, 1000 to 50).
Since the surface area of the capacitance line 3b is not increased, the light shielding film 11a and the first storage capacitance electrode 1f, which are opposed to each other with the first interlayer insulating film 12 'interposed therebetween, are provided.
The capacity between and can be increased. In this way, the storage capacitance can be increased without narrowing the pixel opening region and without impairing the flatness of the pixel portion, and this embodiment is very advantageous.

In this embodiment, as shown in FIGS. 2 and 6, the light shielding film 11b in the light shielding wiring portion (and the light shielding film 11a in the pixel portion connected thereto) is electrically connected to the constant potential line 6b. Therefore, the light shielding film 11a has a constant potential.
Therefore, the potential variation of the light shielding film 11a does not adversely affect the pixel switching TFT 30 arranged so as to face the light shielding film 11a. In this case, the constant potential of the constant potential line 6b may be equal to the ground potential or the counter electrode 21.
May be equal to the potential of Further, the constant potential line 6b may be connected to a constant potential source such as a negative power source or a positive power source of a peripheral circuit for driving the liquid crystal device 100.

In this embodiment, the first interlayer insulating film 12 'is not recessed in the region facing the pixel switching TFT 30 and the region facing the scanning line 3a. Therefore, even if the first interlayer insulating film 12 ′ is extremely thin in the recessed region, if the film thickness in the region not recessed is set to a sufficient value, the pixel switching TFT 30 for forming the channel is formed. There is no problem that the potential of the light-shielding film 11b adversely affects the region 1a ′ or that parasitic capacitance is formed between the scanning line 3a and the light-shielding film 11b. That is, if the configuration of the present embodiment is adopted, even if the film thickness in the concave region of the first interlayer insulating film 12 ′ is formed to be very thin in order to increase the storage capacity, the pixel switching TFT 30 or This is very advantageous because it does not adversely affect the scanning line 3a.

Further, as shown in FIGS. 2 and 6, the first interlayer insulating film 12 'is formed in a concave shape at the position where the light shielding film 11b and the constant potential line 6b are connected, and therefore will be described later. As described above, the process of opening the contact hole 5b by etching after forming the first interlayer insulating film 12 'is facilitated depending on the depth of the recessed portion, and the contact holes 5a and 5b are collectively opened. You can make holes. Therefore, the photolithography process and the etching process only for forming the contact hole 5b can be omitted, so that the number of processes is not increased and the yield is not reduced.

Referring again to FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a scanning line 3a (gate electrode), a semiconductor layer in which a channel is formed by an electric field from the scanning line 3a. 1a for forming a channel, a gate insulating film 2 for insulating the scanning line 3a from the semiconductor layer 1a, a low concentration source region (source-side LDD region) 1b of the semiconductor layer 1a, a data line 6a (source electrode), a semiconductor Low-concentration drain region (drain side LDD region) 1c of the layer 1a, high-concentration source region 1e of the semiconductor layer 1a, and high-concentration drain region 1 of the polysilicon layer 1
e. A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e.
Source regions 1b and 1d and drain regions 1c and 1
As described later, e is formed by doping the semiconductor layer 1a with a predetermined concentration of an n-type or p-type dopant depending on whether to form an n-type or p-type channel. An n-type channel TFT has an advantage of high operating speed and is often used as a pixel switching TFT 30 which is a pixel switching element. In the present embodiment, especially the data line 6a (source electrode) is made of Al.
And a light-shielding thin film such as an alloy film of metal silicide or the like. Further, on the scanning line 3a (gate electrode), the gate insulating film 2 and the first interlayer insulating film 12 ', the contact hole 5 leading to the high concentration source region 1d.
A second interlayer insulating film 4 is formed in which contact holes 8 leading to a and the high-concentration drain region 1e are formed. The data line 6a (source electrode) is electrically connected to the high-concentration source region 1d through the contact hole 5a to the source region 1b. Furthermore, a contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a (source electrode) and the second interlayer insulating film 4 to form a third hole.
The interlayer insulating film 7 is formed. Through the contact hole 8 to the high concentration drain region 1e, the pixel electrode 9a
Are electrically connected to the high concentration drain region 1e. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.

The pixel switching TFT 30 preferably has the LDD structure as described above, but may have the offset structure in which the impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c, or the gate electrode is used. A self-alignment type TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using 3a as a mask may be used.

In the present embodiment, the gate electrode (data line 3a) of the pixel switching TFT 30 is connected to the source-.
Although the single gate structure is provided in which only one gate electrode is disposed between the drain regions 1b and 1e, two or more gate electrodes may be disposed between them. At this time, the same signal is applied to each gate electrode. If the TFT is composed of more than dual gates (double gates),
It is possible to prevent a leak current at the junction between the channel and the source-drain region, and to reduce the current when off. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.

Here, generally, the polysilicon layers such as the channel forming region 1a ', the low concentration source region 1b and the low concentration drain region 1c of the semiconductor layer 1a are caused by the photoelectric conversion effect of polysilicon when light is incident. Although photocurrent is generated and the transistor characteristics of the pixel switching TFT 30 are deteriorated, in the present embodiment, the scanning line 3a is used.
Since the data line 6a (source electrode) is formed of a light-shielding metal thin film such as Al so as to cover the (gate electrode) from the upper side, at least the channel forming region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a. Incident light on (ie
It is possible to effectively prevent the incidence of light from the upper side in FIG. In addition, as described above, the pixel switching TFT 3
Since the light shielding film 11a is provided on the lower side of 0, the return light to at least the channel forming region 1a ′ of the semiconductor layer 1a and the LDD regions 1b and 1c (that is, the light from the lower side in FIG. 3). Can be effectively prevented.

Incidentally, in FIG. 6, the first interlayer insulating film 12 'is formed.
Is composed of two insulating films 12 and 13. Such a configuration will be described in detail in the manufacturing process.

(Second Embodiment of Liquid Crystal Device) Second Embodiment of Liquid Crystal Device According to the Present Invention FIGS. 8 and 9
It will be described based on. In the second embodiment, the light shielding film 11a is not provided on the TFT array substrate 10 side, and further, the first interlayer insulating film 12 'is formed only in the region where the capacitance line 3b is formed below the data line 6a. It is different from the first embodiment in that it is formed in a concave shape. Needless to say, the light shielding film 11a may be provided as shown in FIG. FIG. 8 is a plan view of a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. Also in FIG.
FIG. 9 is a sectional view taken along line BB ′ of FIG. 8. In FIG. 9, the scales of the layers and members are different in order to make the layers and members recognizable in the drawing.
Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 8, the capacitance line 3 is provided below the data line 6a.
In the region surrounded by the thick line in which b is formed, as shown in FIG. 9, the first interlayer insulating film 12 'is recessed and formed, and the other capacitance lines 3b, pixel electrodes 9a, and scanning lines are formed. In a region substantially corresponding to 3a, the first interlayer insulating film 12 'is formed relatively convexly (planarly).

Therefore, only when the flattening process is not performed as in the present embodiment, only the region where the highest level difference occurs on the upper surface of the third interlayer insulating film 7, that is, the region where the liquid crystal alignment defect is the most problematic. Is planarized by the concave recess of the first interlayer insulating film 12 ′, the planarization efficiency is very good based on the cost and labor required for the planarization process.

Further, the first interlayer insulating film 12 'shown in FIG.
Is the same as in the case of the first embodiment.
It may be composed of a layer portion or may be composed of only a single layer.

In this embodiment, as shown in FIG. 9, the high-concentration drain region 1e of the semiconductor layer 1a extends along the data line 6a to serve as the first storage capacitor electrode (semiconductor layer) 1f. Therefore, the first extended along the data line 6a
A capacitance is formed between the storage capacitance electrode (semiconductor layer) 1f and the capacitance line (second storage capacitance electrode) 3b via the first interlayer insulating film 12 ′. Further, flattening is achieved in a region where such a capacitance is formed.

(Third Embodiment of Liquid Crystal Device) A third embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. The third embodiment is different from the first embodiment in that the light shielding film 11a is not provided on the TFT array substrate 10 side. FIG. 10 is a cross-sectional view of the liquid crystal device at a position corresponding to the CC ′ cross section of FIG. 1. Note that, in FIG. 10, the scales of the layers and members are made different in order to make the layers and members recognizable in the drawing. Further, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 10, the liquid crystal device of the third embodiment is not provided with the light shielding film 11a as compared with FIG. 5 showing the first embodiment. The other configurations are similar to those of the first embodiment, and thus the description thereof will be omitted.

Further, the first interlayer insulating film 1 shown in FIG.
As in the case of the first embodiment, 2 ′ may be composed of a single-layer part and a two-layer part, or may be composed of only a single layer.

Therefore, when the flattening process is not performed as in the present embodiment, the region where the capacitance line 3b is formed below the data line 6a where the highest step is formed on the upper surface of the third interlayer insulating film 7 and the scanning are performed. Flattening is achieved by the concave depression of the first interlayer insulating film 12 ′ both in the region where the capacitance line 3b is formed along the line 3a.

(Fourth Embodiment of Liquid Crystal Device) A fourth embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. In the fourth embodiment, the TFT array substrate 10 also serves as the first interlayer insulating film 12 ′ serving as a base film of the semiconductor layer 1 a, and there is no first interlayer insulating film 12 ′ and there is no light shielding film 11 a. This is different from the first embodiment. FIG. 11 is a cross-sectional view of the liquid crystal device at a position corresponding to the BB ′ cross section of FIG. 1. In addition, in FIG. 11, in order to make each layer and each member recognizable in the drawing,
The scale is made different for each layer and each member. Also, the first
The same components as those in the embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 11, the liquid crystal device of the fourth embodiment is different from the first embodiment in that the light shielding film 11
a is not provided. Furthermore, the first storage capacitor electrode (semiconductor layer) 1f is provided directly on the TFT without the first interlayer insulating film 12 '.
It is formed on the array substrate 10. Then, in the region where the capacitance line 3b is formed below the data line 6a, the second interlayer insulating film 4 is formed in a concave shape, and thereby the upper surface of the third interlayer insulating film 7 is flattened. Has been. In addition, in the region where the capacitance line 3b is formed along the scanning line 3a, the second interlayer insulating film 4 may be recessed and formed to be flat, or as in the second embodiment. It does not have to be flattened.

Further, the second interlayer insulating film 4 shown in FIG.
As in the case of the first interlayer insulating film 12 ′ in the first embodiment, may be composed of a single-layer part and a two-layer part, or may be composed of only a single layer.

As described above, the second interlayer insulating film 4 can be used for planarization.

Needless to say, as shown in FIG. 1, a light shielding film 11a and a first interlayer insulating film 12 'may be provided.

(Fifth Embodiment of Liquid Crystal Device) A fifth embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. In the fifth embodiment, the TFT array substrate 10 also serves as the first interlayer insulating film 12 ′ serving as a base film of the semiconductor layer 1 a, and there is no first interlayer insulating film 12 ′ and there is no light shielding film 11 a. This is different from the first embodiment. FIG. 12 is a cross-sectional view of the liquid crystal device at a position corresponding to the BB ′ cross section of FIG. 1. In addition, in FIG. 12, in order to make each layer and each member recognizable in the drawing,
The scale is made different for each layer and each member. Also, the first
The same components as those in the embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 12, in the liquid crystal device of the fourth embodiment, the light shielding film 11 is different from that of the first embodiment.
a is not provided. Furthermore, the first storage capacitor electrode (semiconductor layer) 1f is provided directly on the TFT without the first interlayer insulating film 12 '.
It is formed on the array substrate 10. Then, in the region where the capacitance line 3b is formed under the data line 6a, the third interlayer insulating film 7 is recessed and formed, whereby the upper surface of the third interlayer insulating film 7 is flattened. Has been. Incidentally, in the region where the capacitance line 3b is formed along the scanning line 3a, the third interlayer insulating film 7 may be recessed in a concave shape to be flattened, or as in the second embodiment. It does not have to be flattened.

Further, the third interlayer insulating film 7 shown in FIG.
As in the case of the first interlayer insulating film 12 ′ in the first embodiment, may be composed of a single-layer part and a two-layer part, or may be composed of only a single layer.

As described above, it is possible to use the third interlayer insulating film 7 for planarization.

Needless to say, a light-shielding film 11a and a first interlayer insulating film 12 'may be provided as shown in FIG.

(Overall Configuration of Liquid Crystal Device) The overall configuration of each embodiment of the liquid crystal device configured as described above will be described with reference to FIGS. 13 and 14. 13 is a plan view of the TFT array substrate 10 together with the constituent elements formed thereon as viewed from the side of the counter substrate 20, and FIG. 14 is a plan view of FIG. It is a H'sectional view.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel to the inside of the sealing material 52, for example, a light shielding property made of the same material as or a material different from that of the light shielding layer 23 is provided. A peripheral parting line 53 is provided. In the area outside the sealing material 52, the data line driving circuit 101 and the mounting terminals 102 are provided on the TFT array substrate 1.
The scanning line driving circuit 10 is provided along one side of the scanning line 0.
4 are provided along two sides adjacent to this one side. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line 3a does not matter. In addition, the data line drive circuit 10
1 may be arranged on both sides along the side of the screen display area.
For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the screen display area, and the even-numbered data lines 6a extend along the opposite side of the screen display area. The image signal may be supplied from the data line driving circuit arranged as described above. By thus driving the data lines 6a in a comb shape, the occupied area of the data line driving circuit can be expanded, and a complicated circuit can be configured. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the screen display area are provided. Further, at least one of the corners of the counter substrate 20 is provided with a silver dot 106 made of a conductive material for establishing electrical conduction between the TFT array substrate 10 and the counter substrate 20. Then, as shown in FIG. 14, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52.

The data line driving circuit 101 and the scanning line driving circuit 104 are electrically connected to the data line 6a (source electrode) and the scanning line 3a (gate electrode) by wiring. An image signal converted into a format that can be displayed immediately is input to the data line driving circuit 101 from a control circuit (not shown), and the scanning line driving circuit 104 sends a gate voltage to the scanning lines 3a in sequence in a pulsed manner. Then, the data line driving circuit 101 sends a signal voltage corresponding to the image signal to the data line 6a (source electrode). Particularly in this embodiment, since the pixel switching TFT 30 is a p-Si (polysilicon) type TFT, the data line driving circuit 101 and the scanning line driving circuit 104 are formed in almost the same process when the pixel switching TFT 30 is formed. It is also possible to form a complementary TFT which constitutes, which is advantageous in manufacturing.

Next, FIG. 15 shows the TFT array substrate 10 of the light shielding film 11b forming the light shielding wiring portion in the first embodiment.
A two-dimensional layout on 0 is shown.

As shown in FIG. 15, the light-shielding film 11a is laid out so as to cover the scanning lines 3a, the capacitance lines 3b and the data lines 6a in the screen display area in the peripheral partition 53, and outside the screen display area. Then, the wiring is provided so as to pass through the lower part of the peripheral partition 53 on the counter substrate 20, and is connected to the constant potential line as shown in FIG. By wiring in this way, the dead space under the peripheral partition 53 can be effectively used,
It is possible to take a large area to cure the sealing material. In addition, the peripheral partition 53 provided on the counter substrate 20 is TF
It may be provided on the T-array substrate 10 in the same layer and the same material as the light shielding film 11a so as to be electrically connected to the light shielding films 11a and 11b. As described above, by incorporating the peripheral parting line 53, the light-shielding layer on the counter substrate 20 is not necessary.
The precision when the TF array substrate 10 and the counter substrate 20 are bonded together can be neglected, and a bright liquid crystal device having a uniform transmittance can be realized.

In FIGS. 13 to 15, on the TFT array substrate 10, a precharge circuit for supplying a precharge signal of a predetermined voltage level to each of the plurality of data lines 6a prior to the image signal, and an image signal. A sampling circuit for sampling and supplying the data to the plurality of data lines 6a, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or shipping may be formed. In addition, the data line driving circuit 101 and the scanning line driving circuit 104 are set to TF.
Instead of providing it on the T array substrate 10, for example, TAB
The drive LSI mounted on the (tape automated bonding substrate) may be electrically and mechanically connected via an anisotropic conductive film provided in the peripheral portion of the TFT array substrate 10.

Although not shown in FIGS. 1 to 15, the side of the counter substrate 20 on which the projected light is incident and the side of the TFT array substrate 10 on which the emitted light is emitted are, for example, T 1
Depending on the operating mode such as N (twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, normally white mode / normally black mode, a polarizing film,
A retardation film, a polarizing plate, etc. are arranged in a predetermined direction.

Next, the operation of the present embodiment configured as described above will be described with reference to FIGS. 3 and 13 to 15.

First, the data line driving circuit 101 which receives the image signal from the control circuit supplies the signal voltage to the data line 6a (source electrode) at the timing and magnitude corresponding to the image signal.
To the scanning line driving circuit 104 in parallel with this.
The gate voltage is sequentially applied in a pulsed manner to the scanning line 3a (gate electrode) at a predetermined timing, and the pixel switching TFT
30 is driven. As a result, in the pixel switching TFT 30 to which the source voltage is applied when the gate voltage is turned on, the source regions 1d and 1b, the channel formed in the channel forming region 1a ′ of the semiconductor layer 1a, and the drain region 1c. And 1e, the voltage is applied to the pixel electrode 9a. The voltage of the pixel electrode 9a is held by the storage capacitor (see FIGS. 4 and 5) for a time that is, for example, three digits longer than the time when the source voltage is applied.

As described above, when the voltage is applied to the pixel electrode 9a, the alignment state of the liquid crystal in the portion of the liquid crystal layer 50 sandwiched between the pixel electrode 9a and the counter electrode 21 changes, and the normally white mode is obtained. If so, the incident light cannot pass through the liquid crystal portion according to the applied voltage, and in the normally black mode, the incident light can pass through the liquid crystal portion according to the applied voltage. As a whole, the liquid crystal device 100 emits light having a contrast corresponding to the image signal.

Particularly in the present embodiment, since the pixel portion is flattened by forming the interlayer insulating film in a concave shape, the alignment failure of the liquid crystal is particularly caused in the vicinity of the region where the capacitance line is formed. The liquid crystal device 100 can display a high-contrast image with high contrast.

Since the liquid crystal device 100 described above is applied to a color liquid crystal projector, the three liquid crystal devices 10 are used.
0 is used as a light valve for RGB, and the light of each color decomposed through the dichroic mirror for RGB color separation is incident on each panel as projection light. Therefore, in each embodiment, the counter substrate 2
0, no color filter is provided. However, also in the liquid crystal device 100, an RGB color filter may be formed on the counter substrate 20 together with its protective film in a predetermined region facing the pixel electrode 9a where the light shielding layer 23 is not formed. By doing so, the liquid crystal device of the present embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector. Further, microlenses may be formed on the counter substrate 20 so as to correspond to each pixel. By doing so, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light.
Furthermore, by stacking many interference layers having different refractive indexes on the counter substrate 20, the RG is utilized by utilizing the interference of light.
You may form the dichroic filter which produces B color. This counter substrate with a dichroic filter can realize a brighter color liquid crystal device.

In the liquid crystal device 100, the incident light is made incident from the counter substrate 20 side as in the conventional case. However, when the light shielding film 11a is provided as in the first embodiment, T
The incident light may be incident from the FT array substrate 10 side and emitted from the counter substrate 20 side. That is, even when the liquid crystal device 100 is attached to the liquid crystal projector in this manner, the channel forming region 1a ′ of the semiconductor layer 1a and the LD are formed.
It is possible to prevent light from entering the D regions 1b and 1c, and it is possible to display a high quality image. Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 100, it was necessary to separately dispose a polarizing plate coated with an AR film for antireflection or to attach an AR film. However, in the first embodiment, the light-shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel forming region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a. It is not necessary to use a polarizing plate or AR film coated with an AR film, or to use a substrate obtained by subjecting the TFT array substrate 10 itself to an AR treatment. Therefore, according to this embodiment, the material cost can be reduced, and when the polarizing plate is attached, dust, scratches, etc.
It is very advantageous because it does not reduce the yield. Further, since the light resistance is excellent, even if the light utilization efficiency is improved by using a bright light source or polarization conversion by the polarization beam splitter, image deterioration such as crosstalk due to light does not occur.

The switching element of the liquid crystal device 100 is a positive stagger type or coplanar type polysilicon TFT.
However, the present embodiment is also effective for other types of TFTs such as a reverse stagger type TFT and an amorphous silicon TFT.

Further, in the liquid crystal device 100, as an example, the liquid crystal layer 50 is made of nematic liquid crystal, but if the polymer dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in the polymer is used, the alignment films 19 and 22 are formed. In addition, the polarizing film, the polarizing plate, and the like described above are not necessary, and the advantages of higher brightness and lower power consumption of the liquid crystal device due to the increased light utilization efficiency can be obtained. Further, when the liquid crystal device 100 is applied to a reflective liquid crystal device by forming the pixel electrode 9a from a metal film having a high reflectance such as Al, the SH in which liquid crystal molecules are substantially vertically aligned in the state where no voltage is applied is used. A (super homeotropic) type liquid crystal or the like may be used. Furthermore, in the liquid crystal device 100, the counter electrode 21 is provided on the counter substrate 20 side so as to apply an electric field perpendicular to the liquid crystal layer 50 (longitudinal electric field).
However, the pixel electrodes 9a are each composed of a pair of electrodes for generating a horizontal electric field so as to apply a parallel electric field (horizontal electric field) to the liquid crystal layer 50 (that is, a vertical electric field is provided on the counter substrate 20 side). TFT array substrate 1 without providing electrodes for generation
It is also possible to provide an electrode for generating a horizontal electric field on the side of 0). The use of the horizontal electric field in this manner is advantageous in widening the viewing angle as compared with the case of using the vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.

(Manufacturing Process) Next, a manufacturing process of the liquid crystal device having the above-described structure will be described with reference to FIGS. 16 to 23, taking the liquid crystal device of the first embodiment as an example. 16 to 19 show the TFT in each process.
FIG. 20 is a process diagram showing each layer on the array substrate side in correspondence with the BB ′ cross section of FIG. 4 including the characteristic portions in the first embodiment, and FIGS. 20 to 23 are TFTs in each process. FIG. 7 is a process diagram showing each layer on the array substrate side in correspondence with the DD ′ cross section of FIG. 6. The steps (1) to (20) shown in these figures are collectively performed as the same step in different parts on the TFT array substrate 1.

First, referring to FIGS. 16 to 19, FIG.
The manufacturing process of the portion including the data line 3a corresponding to the BB 'cross section, the capacitance line 3b formed thereunder, and the first storage capacitance electrode (semiconductor layer) 1f will be mainly described.
The manufacturing process of the components shown in the section AA 'in FIG. 3 and the manufacturing process of the components shown in the section CC' in FIG. 5 are the same as those shown in FIGS. Since these processes are collectively performed, the manufacturing process of these processes will be appropriately described for each process.

As shown in step (1) of FIG. 16, a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, preferably, annealing treatment is performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so that distortion occurring in the TFT array substrate 10 in a high temperature process performed later is reduced. I'll do it. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest temperature of the manufacturing process.

The TFT array substrate 1 thus processed
A metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pd or a metal silicide such as metal silicide is sputtered on the entire surface of 0 to form a layer thickness of about 1000 to 5000 Å, preferably about 2
A light shielding film 11 having a layer thickness of 000Å is formed.

Subsequently, as shown in step (2), a resist mask corresponding to the pattern (see FIG. 1) of the light shielding film 11a is formed on the formed light shielding film 11 by photolithography, and the resist mask is formed. The light-shielding film 11a is formed by etching the light-shielding film 11 through.

Next, as shown in the step (3), the light shielding film 11
On top of a, for example, TE by normal pressure or low pressure CVD method or the like.
OS (tetra-ethyl-ortho-silicate) gas, T
EB (Tetra-Ethyl-Borate) gas, TMOP
(Tetra-methyl-oxy-foslate) gas or the like is used to form the first insulating film 12 (two-layered first insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, BPSG), a silicon nitride film, a silicon oxide film, or the like. A lower layer of the interlayer insulating film 12 'is formed. The layer thickness of the first insulating film 12 is, for example, about 5000 to 20000 Å, and the thickness of the first insulating film 12 is determined by the film thickness of the film to be embedded in a later step.

Next, as shown in step (4), the capacitance line 3b
Is etched in a region (see FIGS. 1, 4 and 5) which is to be formed above, and the first insulating film 12 in this region is removed. Here, when the etching is processed by dry etching such as reactive etching or reactive ion beam etching, the first insulating film 12 can be anisotropically removed with substantially the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to the design dimensions. On the other hand, when wet etching is used at least, the opening region of the first insulating film 12 expands because of the isotropic property, but the side wall surface of the opening can be formed in a tapered shape, so that the post-process For example, the polysilicon film 3 and the resist for forming the scanning line 3a do not remain around the sidewall of the opening without being etched or peeled off, and the yield is not reduced. The first insulating film 1
As a method of forming the side wall surface of the second opening in a tapered shape, dry etching may be performed once after the etching is performed once by dry etching. It goes without saying that dry etching and wet etching may be combined.

Next, as shown in step (5), the light shielding film 11
On the a and the first insulating film 12, a second insulating film 13 (two-layer first interlayer insulating film 12) made of a silicate glass film, a silicon nitride film, a silicon oxide film, or the like is formed, similarly to the first insulating film 12. 'Upper layer). The layer thickness of the second insulating film 13 is, for example, about 1000 to 2000Å. Second
The insulating film 13 may be annealed at about 900 ° C. to prevent contamination and flatten it.

In the present embodiment, particularly, the first interlayer insulating film 1
As shown in FIG. 4, the layer thicknesses of the first insulating film 12 and the second insulating film 13 forming 2 ′ are below the data line 6a and the capacitance line 3b.
In the region where the pixel electrode 9a is formed, the pixel region is set to be substantially flat before the pixel electrode 9a is formed.

Next, as shown in the step (6), the temperature is about 450 to 550 ° C., preferably about 500, on the second insulating film 13.
Flow rate of about 400-600cc /
An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using min monosilane gas or disilane gas. Then, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 1 is solid-phase grown to a thickness of about 500 to 2000 Å, preferably about 1000 Å, by performing an annealing treatment for 4 to 6 hours.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG. 3, Sb (antimony), As (arsenic), P ( A dopant of a group V element such as phosphorus is slightly doped by ion implantation or the like. In addition, the pixel switching TFT 30 is set to p
In the case of the channel type, a dopant of a group III element such as B (boron), Ga (gallium), In (indium) is slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, by implanting silicon ions into a polysilicon film deposited by a low pressure CVD method or the like to temporarily make it amorphous,
After that, the polysilicon film 1 may be formed by recrystallizing by annealing treatment or the like.

Next, as shown in step (7) of FIG. 17, a photolithography step, an etching step, etc.
The semiconductor layer 1a having a predetermined pattern as shown in 1 is formed.
That is, especially in the region where the capacitance line 3b is formed under the data line 6a and the region where the capacitance line 3b is formed along the scanning line 3a, from the semiconductor layer 1a (see FIG. 3) that constitutes the pixel switching TFT 30. The extended first storage capacitor electrode (semiconductor layer) 1f is formed (see FIGS. 4 and 5).

Next, as shown in step (8), the first layer is formed together with the semiconductor layer 1a constituting the pixel switching TFT 30.
Storage capacitor electrode (semiconductor layer) 1f at about 900-1300 ° C
By thermal oxidation at a temperature of about 1000 ° C., preferably a temperature of about 1000 ° C., to form a relatively thin thermal oxide silicon film of about 300 Å. About 500Å silicon film
And a gate insulating film 2 (see FIG. 3) of the pixel switching TFT 30 having a multi-layered structure and a capacitance forming insulating film 2 (see FIGS. 4 and 5). As a result, the first storage capacitor electrode 1f (semiconductor layer 1
The thickness of a) is about 300 to 1500 Å, preferably about 350 to 500 Å, and the thickness of the capacity forming insulating film (gate insulating film) 2 is about 200 to 1500 Å. The thickness is preferably about 300 to 1000Å.
By shortening the high temperature thermal oxidation time in this way, it is possible to prevent warpage due to heat, especially when a large wafer of about 8 inches is used. However, the polysilicon layer 1
The capacitor-forming insulating film 2 (gate insulating film 2) having a single-layer structure may be formed only by thermally oxidizing.

Although not particularly limited in the step (8), the semiconductor layer portion serving as the first storage capacitor electrode 1f is doped with, for example, P ions at a dose amount of about 3 × 10 ¹² / cm ² to obtain a low resistance. You may make it.

Next, as shown in step (9), low pressure CVD
After depositing the polysilicon layer 3 by a method such as phosphorus (P)
Are thermally diffused to render the polysilicon film 3 conductive. Or P
A doped silicon film in which ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. As shown in step (10), the capacitance line 3b is formed together with the scanning line 3a (gate electrode) having a predetermined pattern as shown in FIG. 1 by a photolithography process using a resist mask, an etching process, and the like. The layer thickness of these capacitance lines 3b (scanning lines 3a) is, for example, about 3500Å.

However, the capacitance lines 3b and the scanning lines 3a may be formed of a refractory metal film such as W or Mo or a metal silicide film instead of the polysilicon layer, or these metal films or metal silicide films. And a polysilicon film may be combined to form a multi-layer. In this case, if the capacitance line 3b and the scanning line 3a are arranged as a light-shielding film corresponding to a part or the whole of the region covered by the light-shielding layer 23, the light-shielding property of the metal film or the metal silicide film causes one of the light-shielding layers 23 to be formed. It is also possible to omit some or all of them. In this case, in particular, there is an advantage that it is possible to prevent a decrease in the pixel aperture ratio due to the misalignment between the opposing substrate 20 and the TFT array substrate 10.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, the semiconductor layer 1a is first provided with the low concentration source region 1b and the low concentration source region 1b. In order to form the concentration drain region 1c, the scanning line 3a (gate electrode) is used as a diffusion mask, and the dopant 200 of the group V element such as P is used at a low concentration (for example, P ion is 1 to 3 × 10 ¹³ / cm ^2). Dope). As a result, the semiconductor layer 1a below the scanning line 3a (gate electrode) is formed into the channel forming region 1a '.
Becomes The resistance of the capacitance lines 3b and the scanning lines 3a is also lowered by the doping of the impurities (see FIGS. 4 and 5).

Then, as shown in step (12) of FIG. 18, in order to form the high-concentration source region 1b and the high-concentration drain region 1c constituting the pixel switching TFT 30, the scanning line 3a (gate electrode) is used. After forming the resist layer 202 on the scanning line 3a (gate electrode) with a mask having a wide width, the dopant 201 of the group V element such as P is also formed.
At a high concentration (for example, P ions of 1 to 3 × 10 ¹⁵ / cm 2
Dope (with a dose of ² ). When the pixel switching TFT 30 is a p-channel type, the semiconductor layer 1
a, a low concentration source region 1b and a low concentration drain region 1
In order to form c and the high-concentration source region 1d and the high-concentration drain region 1e, doping is performed using a Group III element dopant such as B. When the LDD structure is used as described above, there is an advantage that the short channel effect can be reduced. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT is formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a (gate electrode) as a mask. May be

By doping this impurity, the resistance of the capacitance line 3b and the scanning line 3a is further reduced (see FIGS. 4 and 5).

In parallel with these steps, n-channel type T
Data line driving circuit 101 and scanning line driving circuit 10 having a complementary structure composed of FT and p-channel TFTs
4 are formed on the periphery of the TFT array substrate 10. Thus, in the present embodiment, the pixel switching TF
Since T30 is a polysilicon TFT, the data line driving circuit 101 and the scanning line driving circuit 104 can be formed in almost the same step when the pixel switching TFT 30 is formed, which is advantageous in manufacturing.

Next, as shown in the step (13), the pixel line TFT 30 is covered with the scanning line 3a (gate electrode) and the capacitance line 3b and the scanning line 3a (see FIGS. 4 and 5), for example, normally. Pressure or low pressure CVD method or T
NSG, PSG, BSG, BP using EOS gas etc.
A second interlayer insulating film 4 made of a silicate glass film such as SG, a silicon nitride film, a silicon oxide film or the like is formed. The layer thickness of the second interlayer insulating film 4 is preferably about 5000 to 15000Å.

Next, in the step (14), as shown in FIG. 3, the high concentration source region 1d and the high concentration drain region 1e are formed.
Anneal treatment at about 1000 ° C. to activate
After about a minute, the contact hole 5a for the data line 31 (source electrode) is formed by dry etching such as reactive etching or reactive ion beam etching. At this time, when the contact hole 5a or the like is opened by anisotropic etching such as reactive etching or reactive ion beam etching, there is an advantage that the opening shape can be made substantially the same as the mask shape. However, by combining dry etching and wet etching to open the holes, these contact holes 5a and the like can be tapered, so that there is an advantage that disconnection at the time of wiring connection can be prevented. In addition, the scanning line 3a and the capacitance line 3b (see FIG. 5)
A contact hole for connecting to the wiring (not shown) is also opened in the second interlayer insulating film 4 by the same process as the contact hole 5a.

Next, as shown in step (15), a light-shielding Al film is formed on the second interlayer insulating film 4 by sputtering or the like.
As a metal film 6, a low resistance metal such as
Thickness of about 1000-5000Å, preferably about 3000
Then, the data line 6 is deposited by the photolithography process, the etching process, etc. as shown in step (16).
a (source electrode) is formed.

Next, as shown in step (17) of FIG.
To cover the data line 6a (source electrode), for example,
NS using normal pressure or low pressure CVD method or TEOS gas
A third interlayer insulating film 7 made of a silicate glass film such as G, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The layer thickness of the third interlayer insulating film 7 is preferably about 5000 to 15000Å.

In the present embodiment, the first interlayer insulating film is formed in a concave shape in the region where the capacitance line 3b is formed, particularly by the steps (4) and (5) in FIG. When the step (17) is completed, the capacitance line 3b
The surface of the pixel region located above is substantially flat.
In the liquid crystal device 100, a flattening film may be further applied on the third interlayer insulating film 7 by spin coating or the like in order to further suppress the alignment failure of the liquid crystal molecules on the TFT array substrate 10 side, or CMP processing may be performed. Alternatively, the third interlayer insulating film 7 may be formed of a flattening film. In the present embodiment, as shown in FIG. 4 to FIG.
Since the portion where the capacitance line and the like are formed and the other portion have almost the same height due to the concave depression of the interlayer insulating film 12 ', such a flattening process is not generally required, but a higher quality image is obtained. In order to display, even when further flattening is performed on the uppermost layer in this manner, the flattening film can be made very thin, or a small amount of flattening processing is required. It is very advantageous.

Next, in the step (18), as shown in FIG. 3, in the pixel switching TFT 30,
The contact hole 8 for electrically connecting the pixel electrode 9a and the high-concentration drain region 1e is formed by reactive etching,
It is formed by dry etching such as reactive ion beam etching. At this time, by anisotropic etching such as reactive etching or reactive ion beam etching,
Opening the contact hole 8 has an advantage that the opening shape can be made substantially the same as the mask shape. However,
The contact hole 8 can be formed into a tapered shape by combining dry etching and wet etching to form an opening, and thus there is an advantage that disconnection at the time of wiring connection can be prevented.

Next, as shown in step (19), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 500 to 2000 Å. Further, as shown in step (20), the pixel electrode 9a is formed by a photolithography step, an etching step, and the like. When the liquid crystal device 100 is used in a reflective liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid of a polyimide type alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, as shown in FIG. The alignment film 19 is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and the light shielding layer 23 and the light shielding peripheral partition 53 are sputtered with, for example, metallic chromium, followed by a photolithography process and an etching process. Is formed through. In addition, the light shielding layer 23 and the peripheral parting 53 are C
In addition to metallic materials such as r, Ni, and Al, carbon black or Ti may be formed from a material such as resin black in which photoresist is dispersed.

Thereafter, a transparent conductive thin film of ITO or the like is formed on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 500.
By depositing to a thickness of 2000Å, the counter electrode 21
To form. Further, the alignment film 22 is formed by applying a polyimide-based alignment film coating liquid on the entire surface of the counter electrode 21 and then performing a rubbing treatment in a predetermined direction so as to have a predetermined pretilt angle.

In the present embodiment, as described above, the capacitance line 3 is arranged from the scanning line 3a side adjacent to the data line 6a.
The rubbing process is performed in the direction toward b. As a result, the step S2 (see FIG.
Since the reference) is located near the center of the boundary region covered by the light shielding layer 23, the misalignment in the step S2 has little or no adverse effect on the pixel opening region.

Finally, the T on which each layer was formed as described above.
The FT array substrate 10 and the counter substrate 20 are pasted together with a sealing material 52 so that the alignment films 19 and 22 face each other, and by vacuum suction or the like, for example, a plurality of types of nematic liquid crystals are mixed in the space between the substrates. The resulting liquid crystal is sucked to form a liquid crystal layer 50 having a predetermined layer thickness.

Next, referring to FIGS. 20 to 23, FIG.
A manufacturing process of a portion including a connection portion between the light-shielding film and the constant potential line corresponding to the DD ′ cross section will be described.

Step (1) in FIG. 20 to step (2) in FIG.
0) is performed as the same manufacturing process as steps (1) to (20) of FIG. 19 described above.

That is, as shown in step (1) of FIG.
After forming the light shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), the light shielding film 11b is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding film 11
b on top of the first insulating film 12 (two layers of the first interlayer insulating film 1
2 ′ is formed as a lower layer), and as shown in step (4), the region where the connecting portion is to be formed above is etched to remove the first insulating film 12 in this region.
Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating film 12 can be anisotropically removed with substantially the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to the dimensions.
On the other hand, when wet etching is used at least, the opening area of the first insulating film 12 expands due to the isotropic property, but the side wall surface of the opening can be formed in a tapered shape, so that the post-process For example, a polysilicon film or a resist for forming the scanning line 3a does not remain around the sidewall of the opening without being etched or peeled off, and the yield is not reduced. As a method of forming the side wall surface of the opening portion of the first insulating film 12 in a tapered shape, dry etching is performed once, and then the resist pattern is retracted,
Dry etching may be performed again.

Then, as shown in step (5), the second insulating film 13 (2) is formed on the light shielding film 11b and the first insulating film 12.
Forming an upper layer of the first interlayer insulating film 12 '.

Next, as shown in step (6), after forming an amorphous silicon film on the second insulating film 13, the polysilicon film 1 is solid-phase grown.

Next, in steps (7) and (8) of FIG.
The formation of the semiconductor layer 1a and the gate insulating film 2 in the pixel portion is waited, and then, as shown in step (9), the polysilicon layer 3 is once deposited, and then, as shown in step (10), at this connection portion, The polysilicon layer 3 is entirely removed.

Then, as shown in step (11) of FIG. 21 and step (12) of FIG. 22, the doping of impurity ions for the semiconductor layer 1a is completed.

Next, as shown in step (13), the second interlayer insulating film 4 is formed so as to cover the first insulating film 13, and as shown in step (14), the light shielding film 11b and the constant potential line. A contact hole 5b for connecting with 6b is opened in the second interlayer insulating film 4. At this time, what is formed below the second interlayer insulating film 4 is the second insulating film 1 of the first interlayer insulating film 12 ′.
Since only 3 is provided, the second interlayer insulating film 4 is opened on the high-concentration source region 1d of the semiconductor layer 1a, and the contact hole 5a is formed.
The holes can be opened at once by the same etching step as the step of forming (step (14) in FIG. 18).

Next, as shown in step (15), after depositing Al or the like as the metal film 6 on the second interlayer insulating film 4 by sputtering or the like, as shown in step (16),
A constant potential line 6b made of the same layer (Al or the like) as the data line is formed by a photolithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
A third interlayer insulating film 7 is formed so as to cover the constant potential line 6b and the second interlayer insulating film 4.

Next, in the step (18), after waiting for the contact hole 8 shown in FIG. 3 to be opened, the step (19) is performed.
As shown in FIG. 4, a transparent conductive thin film 9 such as an ITO film is once deposited on the third interlayer insulating film 7, and as shown in step (20), this portion is formed by a photolithography step, an etching step, etc. Remove all.

As described above, according to the method of manufacturing a liquid crystal device in the present embodiment, the second interlayer insulating layer is formed as the contact hole 5b for connecting the light shielding film 11b and the constant potential line 6b to the light shielding film 11b. Film 4 and first insulating film 13
(Upper layer of the first interlayer insulating film) is opened, and at the same time, the second interlayer insulating film 4 is opened until reaching the semiconductor layer 1a as a contact hole 5a for connecting the pixel switching TFT 30 and the data line 6a. To be done. Therefore, these two
Since the contact holes 5a and 5b of various types can be collectively opened, it is advantageous in manufacturing. For example, by wet etching with the selection ratio set to an appropriate value, it becomes possible to collectively open such two types of contact holes 5a and 5b so as to each have a predetermined depth. In particular, the step of opening these contact holes becomes easy depending on the depth of the recessed portion of the first interlayer insulating film. Since the contact hole opening step (photolithography step, etching step, etc.) for connecting the light-shielding film and the constant potential line can be eliminated, the manufacturing cost and the yield are not increased due to the increase in the steps.

As described above, according to the manufacturing process of the present embodiment, the first part in the concave portion is
By controlling the layer thickness of the second insulating film 13, the layer thickness of the interlayer insulating film 12 ′ can be controlled relatively easily, reliably and highly accurately. Therefore, the layer thickness of the first interlayer insulating film 12 ′ in the recessed portion can be made extremely thin.

When the first interlayer insulating film 12 is composed of a single layer, a slight modification is added to the steps (3), (4) and (5) shown in FIGS. 16 and 20, respectively. The steps (1) to (20) may be performed. That is, in step (3), for example, about 10,000 to
A slightly thicker single layer first interlayer insulating film 12 such as 15000Å is deposited, and in the step (4), the capacitance line 3b is formed.
Is etched in a region which is to be formed above, and the first interlayer insulating film 12 in this region is set to 1000-
Leave a thickness of about 2000Å. Then, the step (5) is omitted. Also in this case, the first interlayer insulating film 12
The layer thickness of the non-etched portion and the layer thickness of the etched portion are set so that the pixel region becomes substantially flat before the pixel electrode 9a is formed later. If the first interlayer insulating film 12 is composed of a single layer as described above, it is not necessary to increase the number of layers as compared with the conventional case, and the layer thickness of the recessed portion and the other portion is etched. If it is controlled by time management, it is convenient because flattening can be achieved.

(Electronic Device) Next, an embodiment of an electronic device including the liquid crystal device 100 described in detail above will be described with reference to FIGS. 24 to 28.

First, FIG. 24 shows the liquid crystal device 100 as described above.
1 shows a schematic configuration of an electronic device equipped with.

In FIG. 24, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Memory), R
An AM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like are included, and display information such as an image signal of a predetermined format is displayed based on a clock signal from a clock generation circuit 1008. It is output to the information processing circuit 1002. The display information processing circuit 1002 is configured to include various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. Digital signals are sequentially generated from the information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The driving circuit 1004 may be mounted on the TFT array substrate that constitutes the liquid crystal device 100, or in addition to this, the display information processing circuit 1002 may be mounted.

Next, FIG. 25 to FIG. 28 show specific examples of the electronic apparatus configured as described above.

In FIG. 25, a liquid crystal projector 1100, which is an example of electronic equipment, is provided with three liquid crystal modules including the liquid crystal device 100 in which the above-mentioned drive circuit 1004 is mounted on a TFT array substrate, and light valves for RGB respectively. It is configured as a projector used as 100R, 100G, and 100B. Liquid crystal projector 11
In 00, when the projection light is emitted from the lamp unit 1102 of the white light source such as the metal halide lamp, the three mirrors 1106 and the two dichroic mirrors 1108.
The light components R, G, B corresponding to the three primary colors RGB.
Light valve 100R, which is divided into
00G and 100B respectively. At this time, in particular, the B light is incident on the incident lens 1 in order to prevent light loss due to a long optical path.
122, relay lens 1123 and emission lens 1124
Is guided through the relay lens system 1121. Then, the light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

Particularly in this embodiment, since the light shielding film is also provided on the lower side of the TFT, the reflected light and the projected light by the projection optical system in the liquid crystal projector based on the projected light from the liquid crystal device 100 pass through. Even when the reflected light from the surface of the TFT array substrate at the time of performing, part of the projected light that passes through the dichroic prism 1112 after being emitted from another liquid crystal device, etc. enters from the side of the TFT array substrate as return light, It is possible to sufficiently shield the channel region such as the switching TFT of the pixel electrode from light. Therefore, even if a prism suitable for miniaturization is used in the projection optical system,
Since it is not necessary to attach an AR film for preventing return light or to apply an AR coating treatment to the polarizing plate between the TFT array substrate and the prism of each liquid crystal device, the configuration is small and simplified. It is very advantageous above.

In FIG. 26, a laptop personal computer (PC) 1200 for multimedia, which is another example of electronic equipment, is provided with the liquid crystal device 100 described above in a top cover case, and further includes a CPU,
A keyboard 1202 as well as a memory, a modem, etc.
A main body 1204 in which

In FIG. 27, a pager 1300 as another example of an electronic apparatus includes a backlight 1306a in which a liquid crystal device 100, which is a liquid crystal display module in which the above-mentioned drive circuit 1004 is mounted on a TFT array substrate in a metal frame 1302. Including light guide 1306, circuit board 13
08, first and second shield plates 1310 and 131
It is housed with two, two elastic conductors 1314 and 1316, and a film carrier tape 1318.
In the case of this example, the display information processing circuit 1002 (see FIG.
4) may be mounted on the circuit board 1308 or may be mounted on the TFT array substrate of the liquid crystal device 100. Further, the above-mentioned drive circuit 1004 can be mounted on the circuit board 1308.

Since the example shown in FIG. 27 is a pager, a circuit board 1308 and the like are provided. However, the drive circuit 1004 and further the display information processing circuit 1002
In the case of a liquid crystal device 100 that is mounted with a liquid crystal module to form a liquid crystal module, a liquid crystal device in which the liquid crystal device 100 is fixed in a metal frame 1302 is used as a liquid crystal device, or in addition to this, a light guide device 1306 is incorporated in a backlight type liquid crystal device It is also possible to produce, sell, use, etc.

As shown in FIG. 28, the drive circuit 100
4 and the liquid crystal device 1 not equipped with the display information processing circuit 1002
In the case of 00, the IC 1324 including the drive circuit 1004 and the display information processing circuit 1002 is the polyimide tape 132.
TCP (Tape Carrier Package) 1 mounted on 2
It is also possible to physically and electrically connect to 320 via an anisotropic conductive film provided in the peripheral portion of the TFT array substrate 10 to produce, sell, or use as a liquid crystal device.

In addition to the electronic devices described with reference to FIGS. 25 to 28, liquid crystal televisions, viewfinder type or monitor direct-view type video tape recorders, car navigation devices, electronic notebooks, calculators, word processors, engineering A workstation (EWS), a mobile phone, a videophone, a POS terminal, a device having a touch panel, and the like are examples of the electronic device shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices including the liquid crystal device 100 having high manufacturing efficiency and capable of displaying a high-contrast and high-quality image.

[0150]

According to the liquid crystal device of the present invention, the space below the data line and the space at the pixel boundary along the scanning line, which cannot be used as the pixel opening region, are provided to give the storage capacitance to the pixel electrode. At the same time as it can be effectively used, the flattening of the pixel area located above the data line is achieved, and the alignment failure of the liquid crystal that was most likely to occur in this area can be efficiently reduced, resulting in high contrast and high definition It becomes possible to display. On the other hand, by applying a rubbing treatment in a predetermined direction,
It is possible to dispose a portion where it is difficult to properly perform rubbing treatment and liquid crystal alignment failure easily occurs at a position that does not adversely affect image display, in other words, it is possible to efficiently increase the pixel aperture ratio. This effect is particularly remarkable when the scanning line inversion driving method (1H inversion driving method) is used. In addition, it is recessed in a concave shape for flattening, and therefore, by using the thin insulating film portion as the insulating film for forming capacitance,
The storage capacity of the pixel electrode can be efficiently increased in a limited space. Further, the storage capacitance can be increased more efficiently by utilizing the light-shielding film arranged below the TFT. Furthermore, it is possible to facilitate the connection between the light shielding film and the constant potential source.

On the other hand, according to the method for manufacturing a liquid crystal device of the present invention, the liquid crystal device of the present invention can be manufactured by a relatively simple process control or a highly reliable process.
Also, by making the insulating film for capacitance formation very thin,
It is also possible to efficiently increase the storage capacity of the pixel electrode. Furthermore, it is possible to reduce the cost of the liquid crystal device by collectively opening various contact holes.

Further, according to the electronic apparatus of the present invention, deterioration in image quality due to poor alignment of liquid crystal is reduced, high-contrast high-quality image display is possible, and a low-cost liquid crystal projector or personal computer. Various electronic devices such as a pager and a pager can be realized.

[Brief description of drawings]

FIG. 1 is a plan view of a TFT array substrate provided with a data line, a scanning line, a pixel electrode, a light-shielding film, etc., which is provided in a liquid crystal device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a TFT array substrate showing a connection portion between a light shielding film and a constant potential line in the first embodiment.

FIG. 3 is a cross-sectional view of a liquid crystal device showing a cross section AA ′ of FIG. 1 together with a counter substrate and the like.

FIG. 4 is a sectional view taken along the line B-B ′ of FIG.

5 is a cross-sectional view taken along the line C-C ′ of FIG.

6 is a cross-sectional view of a liquid crystal device showing a cross section DD ′ of FIG. 1 together with a counter substrate and the like.

FIG. 7 is an explanatory diagram schematically showing disclinations in a TN liquid crystal under the influence of a lateral electric field for various driving methods.

FIG. 8 is a plan view of a TFT array substrate provided with a data line, a scanning line, a pixel electrode, etc., which is provided in a liquid crystal device according to a second embodiment of the present invention.

9 is a cross-sectional view taken along the line B-B ′ of FIG.

FIG. 10 is a partial cross-sectional view of a portion of the liquid crystal device according to the third embodiment of the present invention, which corresponds to a cross section taken along the line CC ′ of FIG. 8.

FIG. 11 is a partial cross-sectional view of a portion corresponding to the BB ′ cross section of FIG. 8 of the liquid crystal device according to the fourth embodiment of the present invention.

FIG. 12 is a partial cross-sectional view of a portion corresponding to the BB ′ cross section of FIG. 8 of the liquid crystal device according to the fifth embodiment of the present invention.

FIG. 13 is a plan view showing the overall configuration of the liquid crystal device according to the present embodiment.

FIG. 14 is a cross-sectional view showing the overall configuration of the liquid crystal device according to the present embodiment.

FIG. 15 is a plan view on a TFT array substrate showing a two-dimensional layout of a light shielding film forming a light shielding wiring.

FIG. 16 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 4.

FIG. 17 is a process diagram (No. 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal device for the portion shown in FIG.

FIG. 18 is a process chart (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 4.

FIG. 19 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal device for the portion shown in FIG.

FIG. 20 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 6.

FIG. 21 is a process chart (No. 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 6.

FIG. 22 is a process chart (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 6.

FIG. 23 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal device with respect to the portion shown in FIG. 6.

FIG. 24 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a liquid crystal projector as an example of an electronic device.

FIG. 26 is a front view showing a personal computer as another example of the electronic apparatus.

FIG. 27 is an exploded perspective view showing a pager as an example of an electronic device.

FIG. 28 is a perspective view showing a liquid crystal device using TCP as an example of an electronic apparatus.

[Explanation of symbols]

1a ... semiconductor layer 1a '... Channel forming region 1b ... low-concentration source region (source-side LDD region) 1c ... Low concentration drain region (drain side LDD region) 1d ... High-concentration source region 1e ... high-concentration drain region 1f ... First storage capacitor electrode 2 ... Insulating film for forming capacitance (gate insulating film) 3a ... Scan line (gate electrode) 3b ... Capacitance line (second storage capacity electrode) 4 ... Second interlayer insulating film 5a, 5b ... Contact holes 6a ... Data line (source electrode) 6b ... Constant potential line 7 ... Third interlayer insulating film 8 ... Contact hole 9a ... Pixel electrode 10 ... TFT array substrate 11a, 11b ... Shading film (third storage capacitor electrode) 12 ... First insulating film (lower layer of first interlayer insulating film) 12 '... First interlayer insulating film 13 ... Second insulating film (upper layer of first interlayer insulating film) 19 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 23 ... Light-shielding layer 30 ... TFT 50 ... Liquid crystal layer 52 ... Sealing material 53 ... Surrounding area 70 ... Storage capacity 100 ... Liquid crystal device 101 ... Data line drive circuit 104 ... Scan line drive circuit

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G02F 1/1337 500 G02F 1/1337 500 1/1368 1/1368 F term (reference) 2H090 HA03 HA04 HB04X HD03 HD05 HD14 JA02 JA06 MA01 2H091 FA34Y FB08 FC02 FD02 GA07 GA13 LA30 MA07 MA10 2H092 GA17 GA25 GA29 HA04 JA24 JB22 JB31 JB51 JB58 JB63 JB66 JB69 KB22 KB25 NA04 PA02 PA09 RA05 RA10 2H093 NA16 NA32 NC34 ND60 NE20 NE03 NE06 NE02 NE03 NE06

Claims (10)

[Claims] 1. A liquid crystal is sealed between a pair of substrates,
A plurality of data lines, a plurality of scanning lines intersecting the plurality of data lines, and a plurality of thin film transistors provided corresponding to the intersections of the plurality of data lines and the scanning lines on one substrate of the pair of substrates. And a plurality of pixel electrodes provided corresponding to the plurality of thin film transistors and arranged above the data lines, and an alignment film formed on the pixel electrodes. The insulating film under the pixel electrode has a stepped portion formed by a convex raised portion, and a stepped portion formed by the raised portion followed by a stepped portion formed by a concave portion on the surface of the insulating film under the pixel electrode. The edge of one pixel electrode of the adjacent pixel electrodes is located up to the upper surface of the step portion formed of the raised portion, and the edge of the other pixel electrode of the adjacent pixel electrode is formed of the step portion. Until A liquid crystal device which is characterized in that location. 2. The liquid crystal device according to claim 1, wherein the adjacent pixel electrodes are formed so as to sandwich the scanning line. 3. The liquid crystal device according to claim 2, wherein the liquid crystal is driven by a scanning line inversion driving method in which a polarity of a voltage applied to both ends of the liquid crystal is inverted for each scanning line. 4. The rubbing process is performed on the alignment film in a direction from a step portion formed of the raised portion to a step portion formed of the recessed portion. The liquid crystal device according to item 1. 5. A light-shielding film is formed in a region facing the stepped portion, which is the recessed portion.
5. The liquid crystal device according to any one of items 4 to 4. 6. The liquid crystal device according to claim 1, wherein the step portion formed of the raised portion is formed by a wiring formed in a lower layer. 7. The liquid crystal device according to claim 1, wherein the step portion formed by the recess is formed by recessing an underlying insulating film in a concave shape. 8. The surface of an insulating film as a lower layer of adjacent pixel electrodes formed with the data line interposed therebetween is flattened. Liquid crystal device. 9. A liquid crystal is sealed between a pair of substrates,
A plurality of data lines, a plurality of scanning lines intersecting the plurality of data lines, and a plurality of thin film transistors provided corresponding to the intersections of the plurality of data lines and the scanning lines on one substrate of the pair of substrates. A method for manufacturing a liquid crystal device comprising a plurality of pixel electrodes provided corresponding to the plurality of thin film transistors and arranged above the data lines, and an alignment film formed on the pixel electrodes, In the adjacent pixel electrodes, a step of forming a stepped portion having a convex raised portion on the surface of the insulating film under the pixel electrode, and a step of the stepped portion formed by the raised portion, followed by a surface of the insulating film under the pixel electrode Forming a stepped portion formed of a concave portion, and the edge of one pixel electrode of the adjacent pixel electrodes is located up to the upper surface of the stepped portion formed of the raised portion, and the other of the adjacent pixel electrodes As the edge of the pixel electrode is located to the step portion formed of the recessed portion, the method of manufacturing the liquid crystal device is characterized in that a step of forming the pixel electrode. 10. An electronic apparatus comprising the liquid crystal device according to claim 1. Description: