JPH0675248A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To increase the capacity of the auxiliary capacitive elements formed on the active matrix substrate. CONSTITUTION:This active matrix substrate has pixel electrodes arranged in a matrix form, thin film transistors(TFTs) connected to these pixel electrodes and the auxiliary capacitor for holding charges via these TFTs. the auxiliary capacitor 1 are provided within non-plane regions having plural projecting parts or recessed parts formed on the main surface of the substrate. More specifically the auxiliary capacitor 1 are provided in >=2 pieces of trench recessed parts or trench cells 2 formed on the main surface of the active matrix substrate. The auxiliary capacitor 1 are constituted of first electrode layers 4 formed along the inside walls of the respective trench cells 2, dielectric films formed on the first electrode layers 4 and second electrode layers 6 formed on these dielectric film. The trench cells 2 provide the assemblages finely segmented by partition walls 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate in which pixel electrodes, thin film transistors, auxiliary capacitors, etc. are integrally formed. The substrate having such a structure is used as, for example, a driving substrate of an active matrix type liquid crystal display device. More specifically, the present invention relates to a technology for increasing the capacitance of auxiliary capacitance elements.

[0002]

2. Description of the Related Art To clarify the background of the present invention, FIG.
0 shows an equivalent circuit of a general active matrix type liquid crystal display device. M gate lines (G1, G2, ..., Gm) and n signal lines (S1, S) arranged orthogonal to each other.
, ..., Sn), a liquid crystal cell 103 including a thin film transistor 101, an auxiliary capacitance 102, and a pixel electrode is formed. A scanning signal having a pulse width set in one horizontal scanning period is sequentially applied to the gate lines (G1, G2, ..., Gm). During the period in which one gate line is selected, the sampled image signals are signal lines S1, S2,
, And Sn are sequentially held, and immediately after that, writing is performed on each pixel electrode. The image signal written in the pixel electrode is held for one field period by the liquid crystal cell 103 and the auxiliary capacitor 102, and is rewritten to an image signal of opposite polarity in the next field.

The larger the pixel capacity of each liquid crystal cell 103, the more reliably the pixel potential can be held, so that a uniform display quality can be secured without uneven brightness. Therefore, when the pixel electrode area is large (for example, 200 μm square or more), it is not necessary to provide the auxiliary capacitance. However, when the pixel is made finer or finer in a small-sized display device, the pixel electrode area is remarkably reduced (for example, 100 μm square or less), so that an auxiliary capacitance is indispensable to supplement the pixel capacitance. Generally, in order to perform stable sampling and holding of an image signal, the auxiliary capacitance is required to have a size of about 5 times the pixel capacitance. This storage capacitor generally has a MOS structure and is formed on the plane of the substrate. In order to secure the necessary capacitance, it is necessary to increase the electrode area, and when the pixel is miniaturized, the proportion of the capacitance electrode increases, so that the aperture ratio (ratio of the pixel area to the display area) decreases. In particular, when the pixel area is 50 μm square or less, there is a drawback that the aperture ratio is extremely deteriorated due to the auxiliary capacitance.

As a countermeasure against this, for example, Japanese Patent Laid-Open No. 1-81
Japanese Patent Laid-Open No. 262 discloses an improved example using a so-called trench type auxiliary capacitance. This example will be briefly described with reference to FIG. A groove or trench 105 is formed on the surface of the quartz substrate 104. A first electrode layer 106, a dielectric film 107, and a second electrode layer 108 are sequentially deposited on the inner wall of the trench 105 to form a so-called trench capacitor element 109. As is clear from the figure, the effective area of the pair of electrode layers 106 and 108 is larger than the planar opening area of the trench 105, and only the capacitance value can be increased without increasing the element size. Therefore, when such a trench-type capacitance element 109 is used, the proportion occupied in the display surface can be suppressed to a small value, and a predetermined aperture ratio can be achieved even when the pixel is made finer. On the other hand, the thin film transistor 110 is a planar type, and is formed on the polysilicon thin film 111 that constitutes the semiconductor region. A gate electrode 114 is formed on the semiconductor region via two layers of gate insulating films 112 and 113, and a pixel electrode 116 is electrically connected to the drain region of the thin film transistor 110 via an interlayer insulating film 115. . In addition, a metal wiring 117 connected to each signal line is provided in the source region of the thin film transistor 110. A passivation film 118 is coated on the uppermost part of these laminated structures.

[0005]

FIG. 12 shows a schematic structure of the trench capacitor element 109. The inner wall and bottom surface of the trench 105 are covered with the first electrode layer 106. The first electrode layer 106 is continuously extended from the opening 119 of the trench to the main surface of the substrate. A second electrode layer 108 is laid over a dielectric film (not shown) to fill the inside of the trench 105. Note that the central portion of the second electrode layer 108 is omitted for clarity. The covering area of the first electrode layer 106 is larger than the opening area of the trench 105, so that the capacitance value can be improved. However, the internal space of the trench 105 is only filled with the constituent material of the second electrode layer 108, and there is a problem that it is still insufficient from the viewpoint of space utilization efficiency. As described above, the higher the auxiliary capacity is, the more the image signal holding ability of the pixel is improved, and uniform display without brightness unevenness can be obtained.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to further increase the auxiliary capacitance value. Further, as a result of higher capacity, it is another object to reduce the planar size of the auxiliary capacity element and improve the aperture ratio. The following measures have been taken in order to achieve this object. That is, the present invention is basically applied to an active matrix substrate including pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors. It
As a feature of the present invention, a non-planar region having a plurality of convex portions or concave portions is formed on the main surface of the substrate. The storage capacitor is composed of a first electrode layer formed on the non-planar region, a dielectric film formed on the first electrode layer, and a second electrode layer formed on the dielectric film. Has been done.

Specifically, the non-planar region has a plurality of trench recesses formed by anisotropic etching.
The plurality of trench recesses is an aggregate of trench cells subdivided by partition walls. Alternatively, the aspherical region has a plurality of spherical recesses formed by isotropic etching. Alternatively, the aspherical region has a plurality of convex portions formed by abnormal crystal grain growth of the first electrode layer.

When the auxiliary capacitance has a trench structure,
The thin film transistor also preferably has a trench structure. That is, it is provided along the inner wall of another trench recess formed on the main surface of the active matrix substrate at the same time as the trench recess for the auxiliary capacitor. Specifically, the thin film transistor includes a semiconductor layer formed of the same material as the first electrode layer, a gate electrode formed of the same material as the second electrode layer, and a gate electrode formed between the gate electrode and the semiconductor layer. And a gate insulating film sandwiched between. The active matrix substrate having such a structure can be used as, for example, a driving substrate of a liquid crystal display device.

[0009]

According to the present invention, the auxiliary capacitance is provided in the non-planar region having the plurality of convex portions or concave portions. Unlike the conventional structure using a single trench recess, the non-planar region according to the present invention includes as many recesses or protrusions as possible. Therefore, the effective surface area in the non-planar region becomes extremely large, and the auxiliary capacitance value can be significantly increased. Specifically, for example, the auxiliary capacitance is formed in an aggregate of trench cells subdivided by partition walls. That is, partition walls are arranged at predetermined intervals along the longitudinal direction of one trench to subdivide the trench space. Therefore, not only the bottom surface and the side wall of the trench but also the front and back surfaces of the partition can be covered with the first electrode layer, and the total electrode area is significantly increased as compared with the conventional case. By providing the partition wall, the trench side wall area is sacrificed by the thickness of the partition wall, but by reducing the partition wall thickness, a surplus increase in the electrode area can be obtained by compensating for this loss. Such a partition can be formed at the same time as the trench by etching the substrate, for example.

By the way, the above-mentioned trench cell is generally formed by anisotropic etching. This anisotropic etching may have a problem of controllability and requires a complicated and expensive device. In addition, since the trench cell has a steep step shape, the step coverage of the electrode film is poor and a defect may occur inside the auxiliary capacitance. Therefore, in some cases, a plurality of spherical recesses may be provided by isotropic etching to form a non-planar region. Isotropic etching has better controllability and is simpler in apparatus than anisotropic etching. Further, since the etching shape is a curved surface, it is also advantageous in terms of step coverage. Further, the present invention is not limited to the concave portion, but conversely, a plurality of convex portions may be formed to provide the non-planar region. This convex portion is, for example, the first
It can be formed by abnormal crystal grain growth of the electrode layer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic perspective view showing an example of an auxiliary capacitance element according to the present invention and relates to a trench type. The trench storage capacitor element 1 is composed of at least two trench recesses or trench cells 2. The trench cells 2 are formed in the main surface of the substrate by anisotropic etching and are separated from each other by the partition walls 3. In other words, it has a structure in which the conventional trench is subdivided by the partition walls along the longitudinal direction. The inner wall portion and the bottom portion of each trench cell 2 are covered with the first electrode layer 4. The end portion of the first electrode layer 4 extends to the main surface 5 of the substrate, and connects the electrode portions provided inside the individual trench cells 2 to each other. A second electrode layer 6 is formed on the first electrode layer 4 on the main surface 5 via a dielectric film (not shown).
Are stacked to fill the inside of the trench cell 2. The central portion of the second electrode layer 6 is not shown in order to make the drawing easier to see.

FIG. 2 shows a planar array shape of trench cells. In addition, the opening shape of the conventional trench is also shown for comparison. As shown, the conventional trench 20 has a single continuous longitudinal opening. For the subsequent capacity calculation, the width dimension of the opening is a and the longitudinal dimension is b.

On the other hand, in the present invention, the plurality of trench cells 2 are aligned in the longitudinal direction with the partition walls 3 interposed therebetween. The inner wall and bottom surface of each trench cell 2 are all formed by the first electrode layer 4
Is covered by. For the later capacity calculation, the plane dimensions of the individual trench cells 2 are represented by c and d, and the thickness of the partition wall 3 is represented by e. In order to clarify the comparison with the conventional example, the plurality of trench cells 2 are provided in the conventional trench 20.
Is provided within a range corresponding to the longitudinal dimension b of the. Therefore, the total length of the aggregate of the trench cells 2 is represented by b. The depths of the trench cell 2 and the trench 20 are both h
Is.

Next, the capacitance value of the trench capacitive element is calculated based on each dimension parameter set in FIG. First, the capacitance value C of the conventional trench capacitive element is expressed by the following mathematical formula 1.
Given by.

## EQU1 ## C = (2a × h + 2b × h + a × b) × Ci In Formula 1, Ci represents the capacitance value of the dielectric film per unit area. The first term 2a × h in the bracketed portion represents the widthwise side wall area of the trench 20, the second term 2b × h represents the longitudinal direction sidewall area, and the third term axb represents the bottom area dimension. .

On the other hand, the capacitance value Ct of the trench auxiliary capacitance element according to the present invention is given by the following equation 2.

## EQU2 ## Ct = (2c × h + 2d × h + c × d) × Ci × n In Equation 2, n represents the number of trench cells 2. The first term and the second term 2c × h + 2d × h in the parentheses represent the total inner wall area of each trench cell, and the third term c × d
Represents the bottom area size of each trench cell.

The opening size c of each trench cell 2, the partition wall thickness e, and the total length b have a relationship represented by the following mathematical formula 3.

[Mathematical formula-see original document] c = (b-e * (n-1)) / n [Expression 4]
Is obtained.

## EQU00004 ## Ct = (2 (b-e * (n-1)) / n * h + 2d * h + c * d) * Ci * n = (2 (b-e * n-e) / n * h + 2d * h + c Xd) × Ci × n Here, the opening dimension d of each trench cell 2 is set to the trench 2
When the width dimension a is set equal to 0, the above equation 4 is converted into the following equation 5.

Ct = (2 (b−e × n−e) / n × h + 2a × h + a × (b−e × n−e) / n) × Ci × n = (2 (b−e × n) −e) × h + a (b−e × n−e)) × Ci + 2a × h × Ci × n As is clear from Equation 5, when the dimensions a, b and h are constant, the trench capacitance Ct is the width of the partition wall 3. You can see that it depends on e. In order for the trench storage capacitor according to the present invention to be more effective than the conventional trench storage capacitor, it is necessary to satisfy the following formula 6.

[Equation 6] C ≦ Ct By substituting the equations 1 and 5 for the equation 6 and solving for e, the following equation 7 is obtained.

## EQU00007 ## 2ahn / (2h (n + 1) + a (n + 1)). Gtoreq.e That is, if the thickness dimension e of the partition wall 3 is set so as to satisfy the relationship expressed by the mathematical expression 7, a trench type auxiliary having a larger capacity than the conventional one can be obtained. Capacitive element can be obtained.

For example, a = 5 μm, b = 40 μm, h =
By setting 3 μm and e = 1 μm, the capacitance Ct
When is calculated, it becomes like the following formula 8.

## EQU00008 ## Ct = (7 (4-n) .times.Ci + 30n.times.Ci) .times.10.sup.- ⁸ (F) where, as the value of Ci in Expression 8, 5.2.times.10.sup.- ⁸ F / cm.
^When the trench capacitance Ct is calculated using ² , the graph of FIG. 13 is obtained. The vertical axis of this graph represents the trench capacitance, and the horizontal axis represents the number n of trench cells. As is clear from this graph, as the number n of trench cells is increased, that is, as the trench is subdivided, the trench capacitance is significantly increased as compared with the conventional case.

Next, a method of manufacturing the active matrix substrate according to the present invention will be described with reference to FIGS. In this example, the thin film transistor has a trench structure in addition to the auxiliary capacitance element. With this structure, the pixel aperture ratio can be further improved. Further, the trench has a tapered cross-sectional shape, which facilitates solid phase growth of the polysilicon thin film. First, FIG. 3 is a process diagram showing the formation of the trench recess and the formation of the first polysilicon. In this example, a quartz substrate 31 is prepared as an insulating substrate. After coating a photoresist film on the surface of the quartz substrate 31 and performing exposure and development processing for patterning, wet etching is performed using a 1 to 6 solution of HF and NH ₄ F to form a groove 32 having a shallow but substantially vertical wall. Form. Although only one groove 32 on the left side that forms the auxiliary capacitance is shown, actually, a plurality of grooves subdivided by partition walls are formed at the same time. Next, CF ₄
Plasma dry etching is performed using a mixed gas of 95: 5 and O ₂ as a reaction gas to form a trench recess 33 having a substantially tapered shape. Unlike isotropic wet etching, plasma dry etching has anisotropy, so by appropriately setting various parameters such as the acceleration energy of plasma particles and the vapor pressure of reaction gas, a trench having a desired tapered shape can be obtained. The recess 33 is obtained. In this example, the trench is formed by combining wet etching and dry etching, but in some cases, in the case of a quartz substrate, the taper shape can be formed only by dry etching. Then, the first surface is formed on the entire surface of the quartz substrate 31.
Deposit polysilicon layer 34. A low pressure chemical vapor deposition method (LPCVD method) is used to deposit a film having a thickness of 800 angstrom. By this treatment, the first polysilicon layer 34 can be formed with a substantially uniform film thickness not only on the substrate surface but also on the inner wall portion of the trench recess 33. Then, the first polysilicon layer 3
In order to perform the solid phase growth process of 4, Si ⁺ ions are implanted by ion implantation. For example, the dose is set to 1 × 10 ¹⁵ particles / cm ² with an acceleration energy of 30 keV. Alternatively, the acceleration energy of Si ⁺ ions may be set to 50 keV. By this implantation process, the first polysilicon having an average crystal grain size of 100 angstroms to 500 angstroms is miniaturized and once brought into an amorphous state. Next, heat treatment or annealing is performed at about 620 ° C. for a certain period of time to cause recrystallization and obtain a film having an average crystal grain size of about 5000 Å. Since this film has a crystal structure close to that of a single crystal, a thin film transistor having excellent electric characteristics can be manufactured. If solid phase growth processing is not performed, deterioration of transistor frequency characteristics cannot be avoided. Finally, the first polysilicon layer 34 is patterned into a predetermined shape so that the semiconductor layer 35 of the thin film transistor and the first electrode 3 of the storage capacitor are formed.
6 and 6 are simultaneously formed in the corresponding trench recesses 33.

Next, the step of forming the gate insulating film will be described with reference to FIG. First, the surface of the first polysilicon layer 34 is thermally oxidized to form a SiO ₂ thermal oxide film 37 having a film thickness of about 500 Å. Next, a photoresist 38 is formed in the region where the transistor is to be formed.
After being partially covered with, arsenic cation particles are ion-implanted into the exposed region. The conditions at this time are, for example, an acceleration energy of 30 keV and a dose of 5 × 10 ¹⁴ / cm ² . By this ion implantation, the resistance of the first electrode 36, which constitutes the auxiliary capacitance, is reduced. This ion implantation is performed through the thermal oxide film 37. Next, after removing the resist 38, the surface of the thermal oxide film 37 is subjected to about 3 by LPCVD.
A silicon nitride film having a film thickness of 00 angstrom is deposited. This silicon nitride film is further thermally oxidized to form a thermal oxide film of about 20 angstrom on the surface thereof. In this way, the gate insulating film 39 having a three-layer structure is formed. Since it has a three-layer structure, the pressure resistance is improved.

Next, the formation of the gate electrode of the transistor and the second electrode of the auxiliary capacitance will be described with reference to FIG. L
A second polysilicon layer 40 is deposited on the gate insulating film 39 with a film thickness of about 3500 angstroms using the PCVD method. A phosphor-doped glass (PSG) film (not shown) is deposited on this. Subsequently, heat treatment is performed to diffuse phosphorus in PSG into the second polysilicon layer 40 to reduce the resistance. After removing the PSG, the gate electrode 41 and the second electrode 42 having a predetermined shape are formed. These electrodes are embedded in the trench recess 33, respectively. Therefore, the surface of the trench recess can be processed to be substantially flat. This patterning is performed by plasma etching using a 95: 5 mixed gas of CF ₄ and O ₂ as a reaction gas. The gate electrode 41 is formed in the trench recess 3
It is connected to the gate line or the scanning line through 3. On the other hand, the second electrode 42 is also connected to a predetermined common line through the trench recess 33. By the above processing,
A trench type auxiliary capacitance 56 including the first electrode 36, the dielectric film or insulating film 34, and the second electrode 42 can be formed in the trench recess 33 on the right side. Since it is a subdivided trench type, it has a larger electrode area than the conventional single opening trench type and has an increased capacitance. Further, since the trench has a taper shape, it has a structure in which disconnection failure or the like does not easily occur in the step portion. On the other hand, in the trench recess 33 on the left side, the semiconductor layer 35, the gate insulating film 34, and the gate electrode 41.
The basic structure of the transistor is formed. Similarly, because of the trench structure, the apparent two-dimensional channel length can be shortened compared to the actual three-dimensional channel length, miniaturization of the transistor can be achieved, and the semiconductor layer 35 is formed along the tapered surface. Therefore, there is little fear of breakage failure. In addition, since the semiconductor layer 35 was initially exposed almost completely in plan view, Si ⁺ ion implantation in the solid phase growth process can be performed substantially uniformly as described above.

Next, the process of forming the source and drain regions of the thin film transistor will be described with reference to FIG. First, the upper portion of the left trench recess 33 is covered with a resist film 43, and then arsenic cation particles are ion-implanted to form a lightly doped drain region (LDD). The implantation conditions at this time are as follows: acceleration energy is set to 160 keV and dose is set to 1 × 10 ¹³ / cm ² . The so-called LDD structure aims to prevent short channel effects. In this example, since the transistor has a trench structure, a sufficient channel length can be secured, and it is not always necessary to adopt the LDD structure. Then, the trench recess 3 is formed by using the resist film 44 having a size larger than that of the resist film 43 described above.
After masking 3, arsenic cations are implanted to form an N-channel type source region S and drain region D. The ion implantation conditions at this time are that the acceleration energy is set to 140 keV and the dose is set to 2 × 10 ¹⁵ / cm ² . The N-channel MOS-FET transistor thus produced is used for driving pixels. On the other hand, since CMOS structures are often used in peripheral circuits such as scanning circuits and drive circuits, it is also necessary to create P-channel MOS-FETs. In this case, boron cation particles are ion-implanted into the flat portion of the semiconductor layer 34 through the resist film 45 to form the source region S and the drain region D in which the P-type impurity is highly doped. The ion implantation conditions at this time were an acceleration energy of 30 keV and a dose of 2 × 10 ¹⁵ / cm ² .

Next, the wiring process will be described with reference to FIG.
First, the first interlayer insulating film 46 made of PSG is deposited on the flattened insulating film 39 by the LPCVD method. This first interlayer insulating film 46 is selectively etched to form a first contact hole 47. This process is HF and NH
_It is performed by wet etching using a mixed solution of ₄ F. Next, an aluminum thin film or amorphous silicon thin film 48 to be wiring is deposited by sputtering to a film thickness of about 6000 angstroms. At this time, the deposited film fills the contact hole 47 and conducts to the source region S of the thin film transistor 49. Finally, H ₃ PO ₄
The aluminum thin film or the amorphous silicon thin film 48 is selectively etched using a mixed solution of 2 and 10 of H ₂ O and H ₂ O to perform electrode patterning to form the wiring 50. The wiring 50 is connected to the signal line.

Next, the hydrogen diffusion process for the first polysilicon layer 34 will be described with reference to FIG. First, the second interlayer insulating film 51 is formed on the first interlayer insulating film 46. This film is formed by depositing PSG by the LPCVD method.
Then, a silicon nitride film 52 serving as a hydrogen diffusion source is formed on the second interlayer insulating film 51. The nitride film 52 is formed by physical vapor deposition (PCVD) to a thickness of 4000 angstroms. It contains about 20% hydrogen atoms. When annealing or heat treatment at 400 ° C. is performed in this state, hydrogen atoms pass through the second interlayer insulating film 51, the first interlayer insulating film 46, and the gate insulating film 39 and are trapped in the first polysilicon film 34. Join. As a result, the charge mobility of the first polysilicon film 34 is further improved. It should be noted that, when the hydrogen diffusion process is completed, the silicon nitride film 52 that has become the diffusion source is completely removed.

Finally, the process of forming the pixel electrode will be described with reference to FIG. The second interlayer insulating film 51 and the first interlayer insulating film 46 are formed by dry etching and / or wet etching.
And partially removing the laminated structure of the gate insulating film 39
The contact hole 53 is formed. The hole 53 communicates with the drain region D of the thin film transistor 49.
The dry etching can be performed, for example, by plasma etching using a mixed gas of CF ₄ / O ₂ 95: 5.
In the case of wet etching, a mixed solution of HF and NH ₄ F is used. An ITO film 54 is formed on the second interlayer insulating film 51. For example, 1400 at a film forming temperature of 400 ° C
The film thickness should be about angstrom. At this time, the second contact hole 53 is filled with the ITO film 54 to establish electrical conduction. Finally, the ITO film 54 is patterned to form a pixel electrode 55 which is electrically connected to the drain region D of the thin film transistor 49. This patterning is, for example,
It is performed by wet etching using a 300/300/50 mixed solution of HCl / H ₂ O / NO ₃ . Although not shown, an active matrix type liquid crystal display device can be obtained by bonding a counter substrate having a counter electrode formed thereon to the thus obtained active matrix substrate and enclosing a liquid crystal layer in the gap.

FIG. 14 is a schematic partial sectional view showing a second embodiment of the active matrix substrate according to the present invention. As shown in the figure, a substrate 201 made of quartz glass or the like has pixel electrodes 202 arranged in a matrix. Further, a thin film transistor 203 connected to each pixel electrode 202 and an auxiliary capacitor 204 for holding an electric charge via this thin film transistor 203 are also integrally formed. A non-planar region 205 having a plurality of convex portions or concave portions is formed on the main plane of the active matrix substrate 201. The above-mentioned auxiliary capacitance 204 is the non-planar region 2
05, a first electrode layer 206 formed on the first electrode layer 206, a dielectric film 207 formed on the first electrode layer 206, and a second electrode layer 208 formed on the dielectric film 207. There is. The non-planar region 205 has a plurality of recesses 209 formed by isotropic etching. Alternatively, instead of this, the non-planar region 205 may have a plurality of convex portions formed by the above-described abnormal grain growth of the first electrode layer 206.

On the other hand, the thin film transistor 203 includes the first
Layer 210 formed of the same material as the electrode layer 206 of
A gate electrode 211 made of the same material as the second electrode layer 208, and the gate electrode 211 and the semiconductor layer 2
The gate insulating film 212 is sandwiched between the gate insulating film 212 and the gate insulating film 212. The gate insulating film 212 is the dielectric film 207.
It is made of the same layer as. The source electrode of the thin film transistor 203 is connected to the wiring electrode 2 through the first interlayer insulating film 213.
14 are connected. Further, the pixel electrode 202 described above is electrically connected to the drain region of the thin film transistor 203 through the first interlayer insulating film 213 and the second interlayer insulating film 215. Further, a nitride film 216 containing a large amount of hydrogen is patterned on the second interlayer insulating film 215. The contained hydrogen atoms are diffused in the semiconductor layer 210 by performing an annealing treatment and subjected to a hydrogenation treatment.

FIG. 15 shows a planar shape of the active matrix substrate shown in FIG. In this embodiment, the auxiliary capacitance 2
In order to make the occupied area of 04 as small as possible, the auxiliary capacitance 204 is formed only in the gate line formed of polysilicon. That is, the gate line is the second electrode 208.
The storage capacitor 204 is also provided here. However, it is difficult to obtain a predetermined capacitance value (for example, 200 fF) simply by providing the auxiliary capacitance in a plane. Therefore, the non-planar region 205 including the plurality of recesses 209 is previously formed on the substrate. In this non-planar region, the first electrode 206 made of the first polysilicon, the dielectric film (not shown), and the second electrode 208 made of the second polysilicon are formed so as to overlap with each other to increase the capacitance value. As described above, at this time, the thin film transistor 203 serving as a pixel switch is also formed at the same time. Since the surface area of the auxiliary capacitance is substantially increased by utilizing the non-planar region 205, the area occupied by the auxiliary capacitance 204 can be reduced and the aperture ratio is increased. In the illustrated example, the aperture ratio of the pixel electrode 202 is 47.7%. As a result,
The brightness of the liquid crystal pixels is increased and the contrast ratio is improved.

FIG. 16 shows a planar shape of a conventional active matrix substrate for comparison. To make it easier to understand
Portions corresponding to the structure shown in FIG. 15 are designated by corresponding reference numerals. In this conventional example, in order to make the capacitance value of the auxiliary capacitance 204 satisfy a target value (for example, 200 fF),
The occupied area is large, and the second electrode 208 extends beyond the gate line. For this amount, the pixel electrode 202
The area allocated to is reduced. Therefore, in the conventional example, the pixel aperture ratio is about 38%, which is inferior to the present invention by 9.7%.

FIG. 17 is a schematic diagram showing a specific example of the structure of the non-planar area 205. In this example, the quartz substrate 201
A spherical recess 209 formed by isotropic etching is provided on the main surface of the.

FIG. 18 is a schematic view showing another configuration example of the aspherical surface area. In this example, the plurality of spherical convex portions 219 are provided by utilizing the abnormal crystal grain growth of the first polysilicon forming the first electrode layer 206. This abnormal growth can be realized by selectively introducing the impurity phosphorus. After the abnormal growth is performed, the spherical projections 219 are obtained by shaping by etching.

FIG. 19 is a schematic view showing another example of the structure of the non-planar area. In this example, isotropic etching is used to form semi-cylindrical recesses 229 in a stripe shape. Since the stripes are orthogonal to each other in a matrix, the plane area of the non-planar region can be further increased.

Finally, a method of manufacturing the active matrix substrate shown in FIG. 14 will be described in detail with reference to FIGS. First, in step A of FIG. 20, a quartz substrate 301 is prepared. Next, in step B, the quartz substrate 30
A non-planar region 302 is formed at a predetermined portion of 1. In this embodiment, wet etching is positively used to provide the plurality of recesses 303. Recess 3 due to isotropic etching
03 is a four-sided surface, which is different from the vertical shape or taper shape obtained when dry etching is performed. Since isotropic etching has a simple processing apparatus and good controllability, a large margin can be obtained in terms of process conditions. Next, in step C, a first polysilicon film 304 is formed on the surface of the quartz substrate 301. Further, in step D, the first polysilicon film 304 is patterned into a predetermined shape. As a result, the first electrode layer 305 for forming the auxiliary capacitance is provided in the non-planar region 302. On the other hand, a thin film transistor is formed in a region adjacent to the non-planar region 302 in a post process.

In step E of FIG. 21, the gate insulating film 30 is formed.
6 is deposited. In this example, the gate insulating film 30
6 has a three-layer structure of SiO ₂ / Si ₃ N ₄ / SiO ₂ . Subsequently, in step F, As ⁺ ions are implanted to reduce the resistance of the first electrode layer 305 provided in the non-planar region 302. Next, in step G, second polysilicon 307 is deposited on the entire surface of the quartz substrate 301 by the LPCVD method. Further, in step H, the second polysilicon is patterned into a predetermined shape to form the gate electrode 308 and the second electrode layer 30.
9 is formed at the same time. This means that the auxiliary capacitance is formed in the non-planar region 302 by the second electrode layer 309, the first electrode layer 305, and the dielectric film sandwiched therebetween.

In step I of FIG. 22, the gate electrode 308
Is used as a mask to implant impurity ions to form an LDD region in the first polysilicon layer 304. Further, in step J, after covering the periphery of the gate electrode 308 with a resist 309, impurity ions are implanted at a high concentration to form N-type source and drain regions in the first polysilicon layer 304. In this way, an N-channel thin film transistor is provided. Subsequently, in step K, a first interlayer insulating film 310 made of PSG is formed on the entire surface of the quartz substrate 301.

In step L of FIG. 23, the first interlayer insulating film 3
A contact hole 311 is opened at 10 to expose the source region of the thin film transistor. In step M, metallic aluminum is sputtered to entirely deposit a metal wiring film 312 on the first interlayer insulating film 310. In step N, the metal wiring film 312 is patterned into a predetermined shape and the wiring electrode 31
Get 3. Then, in step O, a second interlayer insulating film 314 made of PSG is deposited on the entire surface of the quartz substrate 301 by the CVD method.

In step P of FIG. 24, the second interlayer insulating film 3
A second contact hole 315 is opened at 14 to expose the drain region of the thin film transistor. Next, in step Q, a transparent conductive film 316 made of ITO is formed on the entire surface of the quartz substrate 301 by a sputtering method. Next, in step R, the transparent conductive film is patterned to obtain the pixel electrode 317.
Finally, in step S, P-Si is formed by the plasma CVD method.
An N film 318 is formed and a hydrogenation process is performed.

[0037]

As described above, according to the present invention, a non-planar region having a plurality of protrusions or recesses is formed on the main surface of an active matrix substrate, and an auxiliary capacitance is provided in this non-planar region. The first electrode layer is formed, the dielectric film is formed on the first electrode layer, and the second electrode layer is formed on the dielectric film. With such a configuration, the capacitance value can be increased without depending on the surface area occupied by the auxiliary capacitance element. Therefore, there is an effect that the image signal holding capacity can be remarkably improved as compared with the conventional one, the reduction of the pixel holding potential due to leakage can be suppressed, and uniform image quality without unevenness in brightness can be obtained over the entire display screen. Further, since the auxiliary capacitance value per unit area can be increased, the area occupied by the auxiliary capacitance element can be reduced by that much, so that the aperture ratio is increased and the image contrast can be improved.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing a configuration of a trench type auxiliary capacitance element formed on an active matrix substrate according to the present invention.

FIG. 2 is a schematic view showing a planar shape of a trench type auxiliary capacitance element.

FIG. 3 is a process drawing showing the manufacturing method of the active matrix substrate according to the present invention.

FIG. 4 is a process drawing showing the same manufacturing method.

FIG. 5 is a process drawing showing the same manufacturing method.

FIG. 6 is a process drawing showing the same manufacturing method.

FIG. 7 is a process drawing showing the same manufacturing method.

FIG. 8 is a process drawing showing the same manufacturing method.

FIG. 9 is a process drawing showing the same manufacturing method.

FIG. 10 is an equivalent circuit diagram of a conventional active matrix liquid crystal display device.

FIG. 11 is a cross-sectional view of a conventional active matrix substrate.

FIG. 12 is a perspective view of a conventional trench type auxiliary capacitance element.

FIG. 13 is a graph showing the relationship between the capacitance value of the trench type auxiliary capacitance element and the number of trench cells according to the present invention.

FIG. 14 is a schematic partial cross-sectional view showing another embodiment of the active matrix substrate according to the present invention.

15 is a schematic diagram showing a planar shape of the active matrix substrate shown in FIG.

FIG. 16 is a schematic view showing a planar shape of a conventional active matrix substrate.

FIG. 17 is a schematic diagram showing a specific configuration example of a non-planar region in which an auxiliary capacitance element is formed.

FIG. 18 is a schematic diagram showing another configuration example of the non-planar region.

FIG. 19 is a schematic diagram showing another configuration example of the non-planar region.

FIG. 20 is a process drawing showing the manufacturing method of the active matrix substrate shown in FIG.

FIG. 21 is a process drawing showing the same manufacturing method.

FIG. 22 is a process drawing showing the same manufacturing method.

FIG. 23 is a process drawing showing the same manufacturing method.

FIG. 24 is a process drawing showing the same manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Trench auxiliary capacitance element 2 Trench cell 3 Partition wall 4 First electrode layer 5 Main surface 6 Second electrode layer 201 Active matrix substrate 202 Pixel electrode 203 Thin film transistor 204 Auxiliary capacitance 205 Non-planar region 206 First electrode layer 207 Dielectric film 208 second electrode layer 209 concave portion 219 convex portion 229 concave portion

Claims (8)

[Claims] 1. An active matrix substrate comprising pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors, wherein a plurality of convex portions or A non-planar region having a recess is formed on the main surface of the substrate, and the auxiliary capacitor has a first electrode layer formed in the non-planar region, and a dielectric film formed on the first electrode layer, An active matrix substrate comprising a second electrode layer formed on the dielectric film. 2. The active matrix substrate according to claim 1, wherein the non-planar region has a plurality of trench recesses formed by anisotropic etching. 3. The active matrix substrate according to claim 2, wherein the plurality of trench recesses are an aggregate of trench cells subdivided by partition walls. 4. The active matrix substrate according to claim 1, wherein the non-planar region has a plurality of spherical recesses formed by isotropic etching. 5. The active matrix substrate according to claim 1, wherein the non-planar region has a plurality of convex portions formed by abnormal crystal grain growth of the first electrode layer. 6. One substrate having pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors, and a counter electrode. In a liquid crystal display device including the other substrate arranged to face the one substrate and a liquid crystal layer held between the two substrates, a main surface of the one substrate has a plurality of convex portions or concave portions. A non-planar region is formed, and the auxiliary capacitance is formed on the first electrode layer formed on the non-planar region, a dielectric film formed on the first electrode layer, and the dielectric film. And a second electrode layer. 7. The liquid crystal display device according to claim 6, wherein the non-planar region has a plurality of trench recesses. 8. The thin film transistor is provided along the inner wall of another trench recess formed in the main surface of one substrate at the same time as the trench recess, and the first thin film transistor is provided.
A semiconductor layer formed of the same material as the electrode layer of
8. The liquid crystal display device according to claim 7, wherein the liquid crystal display device comprises a gate electrode formed of the same material as that of the electrode layer, and a gate insulating film sandwiched between the gate electrode and the semiconductor layer.