JP2002072248A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device provided with a satisfactory auxiliary capacitance without reducing the aperture ratio. SOLUTION: A pixel electrode 23 is formed on one of a pair of substrates 1 and 2. An another electrode forming a liquid crystal capacitance between the another electrode and the pixel electrode is provided. An auxiliary capacitance is connected in parallel with the liquid crystal capacitance. The liquid crystal display device having a liquid crystal 3 interposed between the pair of substrates 1 and 2 is provided. An insulating film is formed on a semiconductor layer 20 for the auxiliary capacitance and an auxiliary capacitance line 21 is formed on the insulating film to form the auxiliary capacitance. Ruggedness is formed on the surface of the semiconductor layer 20 for the auxiliary capacitance. The height of the ruggedness is suppressed to the height equal to the thickness of a gate insulating film 15 or below. The liquid crystal display device provided with the large auxiliary capacitance is obtained, wherein a leakage defect between the semiconductor layer 20 for the auxiliary capacitance and the auxiliary capacitance line 21 is not generated and the aperture ratio is not reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a structure of a semiconductor layer for an auxiliary capacitor.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, an auxiliary capacitor connected in parallel with a liquid crystal capacitor is formed in order to hold a liquid crystal capacitor formed between a pixel electrode and a counter electrode. In order to maintain the liquid crystal capacitance, the larger the auxiliary capacitance is, the more preferable it is. However, since the electrodes forming the auxiliary capacitance are light-shielding, the aperture ratio is reduced in order to increase the auxiliary capacitance. Therefore, a decrease in the aperture ratio is inevitable to obtain a sufficient auxiliary capacitance, and a sufficient auxiliary capacitance cannot be obtained to increase the aperture ratio.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a liquid crystal display device having a sufficient auxiliary capacitance without lowering the aperture ratio.

[0004]

According to the present invention, there is provided a liquid crystal display device having a pair of substrates and a liquid crystal interposed between the pair of substrates, wherein a pixel electrode formed on one of the pair of substrates and a pixel are provided. Having another electrode forming a liquid crystal capacitor between the electrode and an auxiliary capacitor connected in parallel to the liquid crystal capacitor,
The storage capacitor includes a storage capacitor semiconductor layer, an insulating film formed on the storage capacitor semiconductor layer, and a storage capacitor line formed on the insulating film, and the surface of the storage capacitor semiconductor layer has undulations. A liquid crystal display device having an undulation height equal to or less than the thickness of the insulating film.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of one embodiment of the liquid crystal display device of the present invention will be described below with reference to FIGS.

FIG. 1A is a schematic cross-sectional view showing one pixel of the liquid crystal display device according to the present embodiment, and a liquid crystal 3 is sandwiched in a gap between an array substrate 1 and a counter substrate 2.

The structure of the array substrate 1 is a transparent glass substrate.
A thin film transistor, that is, a thin film transistor T
An FT (Thin Film Transistor) 13 is provided. TFT
13, a gate electrode 16 is formed on a semiconductor layer 14 made of polysilicon via a gate insulating film 15 made of silicon oxide or the like, and an interlayer insulating film 17 made of silicon oxide or the like is formed so as to cover the gate electrode 16. The configuration is such that the source electrode 18 and the drain electrode 19 are connected to the semiconductor layer 14 via through holes formed in the interlayer insulating film 17.

Further, an auxiliary capacitance semiconductor layer 20 made of polysilicon or the like is formed on the array substrate 1 to form an auxiliary capacitance, and a gate insulating film 15 is formed on the auxiliary capacitance semiconductor layer 20. An auxiliary capacitance line 21 is formed through the intermediary. The auxiliary capacitance semiconductor layer 20 is connected to the source electrode 18. Then, an auxiliary capacitance is formed by the auxiliary capacitance semiconductor layer 20, the auxiliary capacitance line 21, and the gate insulating film 15.

Further, a color filter 22 made of a photosensitive resist or the like in which a pigment is dispersed is formed so as to cover the TFT 13, and a pixel electrode 23 made of indium-tin oxide or the like is formed on the color filter 22. . This pixel electrode 23
Is connected to the source electrode 18 of the TFT 13 via a through hole formed in the color filter 22.

Further, a spacer 24 made of a transparent or colored photosensitive resist or the like is formed on the TFT 13 in order to maintain a gap with the counter substrate 2.
An alignment film 25 made of polyimide or the like is formed on the entire surface so as to cover 24.

Next, the counter substrate 2 has a counter electrode 32 made of indium-tin oxide or the like formed on a transparent glass substrate 31, and an alignment film made of polyimide or the like thereon.
33 are formed.

The auxiliary capacitance semiconductor layer 20 has undulations on its surface, thereby increasing the effective area contributing to the formation of the auxiliary capacitance as compared with the area when viewed in plan. ing. The height of the undulation (the difference between the lowest part and the highest part) is formed to be equal to or less than the thickness of the gate insulating film 15. This is to suppress a leak failure between the auxiliary capacitance semiconductor layer 20 and the auxiliary capacitance line 21. That is, FIG.
As can be seen from the graph, when the height of the undulations / the thickness of the gate insulating film 15 is plotted on the horizontal axis, the leak failure rate becomes 3% when the value is close to 1, and the leak failure rate starts from this value. It can be seen that has increased. Therefore, it is important to suppress the height of the undulation to be equal to or less than the thickness of the gate insulating film 15 in order to suppress the leak failure. It is more preferable that the height of the undulation be equal to or less than half the thickness of the gate insulating film 15, that is, the leak failure rate be equal to or less than 1%. Note that the thickness of the gate insulating film 15 slightly varies under the influence of the undulation, but the thickness of the gate insulating film 15 referred to here is the thickness of the gate insulating film 15 formed on the portion with the lowest undulation. Thickness.

Next, a method of manufacturing the liquid crystal display device according to the embodiment will be described.

First, as the array substrate 1, a glass substrate 11
Silicon nitride is plasma CVD (Chemical Vapor D
An undercoat film 12 is formed with a thickness of 50 nm using an eposition method. Then, amorphous silicon is continuously formed to a thickness of 50 nm.

Next, the surface of the amorphous silicon is washed with hydrofluoric acid to remove the natural oxide film almost completely, and then annealed with a XeCl excimer laser to obtain polysilicon. At this time, the height of the undulation formed on the polysilicon surface can be adjusted by various parameters, and the height of the undulation is controlled in consideration of the relationship with the thickness of the gate insulating film 15 later.

In this embodiment, the height of the undulations is controlled by the oxygen concentration in the atmosphere at the time of excimer laser annealing, and the annealing is performed by setting the oxygen concentration in the range of 1 to 3%. Thus, polysilicon having an undulation height of at most 40 nm was used.

The polysilicon is patterned to form the semiconductor layer 14 and the auxiliary capacitance semiconductor layer 20 at the same time. Here, in this embodiment, the natural oxide film is almost completely removed with hydrofluoric acid, and the oxygen concentration at the time of annealing is set to 1 to 3%. It may be appropriately changed depending on the size and the like. Further, the height of the undulation may be controlled not only by the oxygen concentration but also by other parameters.

Next, a silicon oxide film is formed to a thickness of 130 n by a plasma CVD method using tetraethoxysilane as a source gas.
Then, a gate insulating film 15 is formed. Here, the thickness of the gate insulating film 15 needs to be not more than 30 nm in height of undulations.

Next, a molybdenum-tungsten alloy is formed by sputtering and patterned to form a gate electrode 16 and an auxiliary capacitance line 21.

Then, the gate electrode 16 and the auxiliary capacitance line 21
The semiconductor layer 14 and the auxiliary capacitance semiconductor layer 20 are doped with ions such as phosphorus ions from above.

Then, a silicon oxide film is formed by a plasma CVD method so as to cover the gate electrode 16 and the auxiliary capacitance line 21, and an interlayer insulating film 17 is formed.
Drill a through hole at 17.

Next, a metal mainly composed of Al is deposited by a sputtering method, and is patterned to form a source electrode 18 and a drain electrode 19.

On top of this, a pigment-dispersed photosensitive resist is applied, and this is exposed and developed to form through holes, thereby forming a color filter 22.

Then, a film of indium-tin oxide is formed on the color filter 22 by a sputtering method, and is patterned to form a pixel electrode 23.

Next, a transparent or colored photosensitive resist is applied and patterned to form spacers 24, polyimide is further formed on the entire surface, and a rubbing process is performed to form an alignment film 25.

The counter substrate 2 is formed by depositing indium-tin oxide on a glass substrate 31 by sputtering, forming a counter electrode 32, forming polyimide thereon, performing a rubbing process, and forming an alignment film 33. Form.

Then, the array substrate 1 and the opposing substrate 2 are bonded together with a sealing material (not shown), and a liquid crystal 3 is injected into a gap between the array substrate 1 and the opposing substrate 2, and the injection port is sealed. Obtain a display device.

[0028]

According to the present invention, undulations are formed on the surface of the auxiliary capacitance semiconductor layer, and the height of the undulations is suppressed to the thickness of the gate insulating film or less. It is possible to obtain a liquid crystal display device having a large auxiliary capacitance without causing a leak failure with the auxiliary capacitance line and without decreasing the aperture ratio.

[Brief description of the drawings]

FIG. 1A is a partial cross-sectional view of a liquid crystal display device according to an embodiment of the present invention. (B) is a cross-sectional view showing the height of the undulation and the thickness of the gate insulating film.

FIG. 2 is a graph showing a leak failure rate with respect to a ratio between a relief height of a semiconductor for an auxiliary capacitor and a thickness of a gate insulating film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Array substrate 2 Counter substrate 3 Liquid crystal 13 TFT as a thin film transistor 14 Semiconductor layer 15 Gate insulating film 16 Gate electrode 20 Semiconductor layer for auxiliary capacitance 21 Auxiliary capacitance line 23 Pixel electrode

Continued on the front page F-term (reference) 2H092 HA28 JA24 JA33 JA35 JB69 KA04 KA12 KA18 KA19 KA22 KB12 KB25 MA05 MA08 MA30 MA41 NA07 NA22 PA08 5C094 AA10 AA15 AA43 BA03 BA43 CA19 DA13 DA15 DB01 DB04 EA04 EA10 FB02 FA01 FB02 FA01 AA30 CC02 DD02 DD14 EE06 EE44 FF02 FF12 FF30 GG02 GG13 GG22 GG25 GG45 HJ01 HJ12 HL03 HL23 NN02 NN23 NN35 NN73 PP03 PP31 QQ09 QQ11

Claims (3)

[Claims] 1. A liquid crystal display device comprising: a pair of substrates; and a liquid crystal sandwiched between the pair of substrates. A liquid crystal display device comprising: a pixel electrode formed on one of the pair of substrates; And a storage capacitor connected in parallel with the liquid crystal capacitor. The storage capacitor is formed on the storage capacitor semiconductor layer and the storage capacitor semiconductor layer. An insulating film and an auxiliary capacitance line formed on the insulating film, wherein the surface of the auxiliary capacitance semiconductor layer has undulations, and the height of the undulations is equal to or less than the thickness of the insulating film. A liquid crystal display device characterized by the above-mentioned. 2. The liquid crystal display device according to claim 1, wherein the auxiliary capacitance semiconductor layer is made of polysilicon. 3. One of the substrates has a thin film transistor connected to a pixel electrode, wherein a semiconductor layer forming the thin film transistor and a semiconductor layer for an auxiliary capacitor are made of the same material, and a gate electrode forming the thin film transistor is formed. 2. The liquid crystal display device according to claim 1, wherein the auxiliary capacitance line is made of the same material, and a gate insulating film forming the thin film transistor is made of the same material as the insulating film.