TW201327643A - A method for manufacturing a liquid crystal display panel array substrate - Google Patents

Abstract

A method of raising the transmission of the array panel of the liquid crystal display, including the following steps, first providing a substrate, forming a gate electrode, a gate insulate layer, a semiconductor layer, a first transparent electrode, a source electrode and a drain electrode on the substrate in sequence, and then forming a passivation layer to cover the source electrode, the drain electrode, the semiconductor layer and the gate insulating layer, and then forming a second passivation layer covering the first passivation layer, afterward, forming a second transparent electrode layer on the second passivation layer, wherein the power for depositing the first passivation layer is less than 5500 W, while the power for depositing the first passivation layer is more than 5000 W.

Description

Liquid crystal display panel array substrate manufacturing method

The present invention relates to a method for fabricating a liquid crystal display panel array substrate, and more particularly to a method for fabricating a transmittance of a liquid crystal display panel array substrate.

In recent years, liquid crystal displays (LCDs) have been widely used and widely recognized for their superior characteristics. LCD is a display that changes its light transmittance by applying an electric field to liquid crystals having both liquid fluidity and optical properties. As a new type of display that can replace cathode ray tube (CRT) displays, it is thin and light. Low power consumption and low radiation are highly regarded.

LCD devices come in many types depending on the properties of their liquid crystals and pattern structures. More specifically, the LCD device is classified into a twisted nematic (TN) type, which controls the liquid crystal torsion by applying a voltage; a multi-domain type, which obtains a wide viewing angle by dividing one primitive into a plurality of domains; and optically compensated birefringence (OCB) Type: compensates for the phase change of light according to the direction of travel of the light by forming a compensation film on the outer surface of the substrate; in-plane switching (IPS) type, forming parallel parallelism by forming two electrodes on either substrate An electric field; and a vertical alignment (VA) type, by using a negative liquid crystal and a vertical alignment layer, the vertical axis of the liquid crystal molecules is perpendicular to the plane of the alignment layer.

Among these types, the IPS type LCD device includes a color filter (CF) substrate, an Array substrate, and a liquid crystal layer. Wherein the color filter substrate and the array substrate face each other, and a liquid crystal layer is formed between the two substrates. The color filter substrate includes a black matrix layer for preventing light leakage, and R, G, and B filter layers for realizing various colors. In addition, the array substrate includes: a plurality of scanning lines and a plurality of data lines are criss-crossed, and a plurality of pixels are located between the scanning and data lines, and each pixel includes a pixel electrode and a common electrode. For the effect of light penetration, the influence of the color filter (CF) substrate is relatively stable. After the material and structure of the film layer are determined, the influence of the process parameters on the transmittance is determined by the color filter substrate. Since the substrate is much smaller, it is usually focused on how to improve the film layers of the array substrate in terms of improving the transmittance. As shown in FIG. 1, a thin film transistor region and a display region are included in a pixel region, wherein the thin film transistor region is an opaque region, and the display region is a light penetrating region, but In the array substrate of the IPS type liquid crystal display panel, the display region includes an overlapping structure of a plurality of films, such as a gate insulating layer 201, a pixel electrode 501, a passivation layer 701, and a common electrode 801 on the substrate 100, and the entire array In the process of the substrate, the single layer transmittance of the pixel electrode 501 is critical to the entire array substrate, mainly because the pixel electrode 501 is caused when the passivation layer 701 overlying the pixel electrode layer 501 is formed. Damage, especially when depositing the passivation layer 701, reduces the oxygen content in the pixel electrode, while the material of the pixel electrode is usually indium oxide selenium, and a decrease in the oxygen content causes a decrease in the transmittance. The IPS type liquid crystal display panel is based on the lamination relationship between the pixel electrodes and the passivation layer and the influence relationship of the process, resulting in a low transmittance of the array substrate of the IPS type liquid crystal display panel.

In order to solve the above problems, many solutions have been proposed in the prior art, for example, by changing the width of the pixel electrode or the common electrode, or by changing the material of the insulating layer, but the desired effect is not achieved. Therefore, increasing the transmittance of the IPS type LCD has become an urgent problem to be solved.

The invention provides a method for fabricating a panel array substrate of an IPS display technology, which improves the transmittance of an IPS liquid crystal display panel array substrate by changing a formation mode of the passivation layer.

The invention provides a method for fabricating an IPS type liquid crystal display panel array substrate, firstly providing a substrate, sequentially forming a gate electrode, a gate insulating layer, a semiconductor layer, a first transparent electrode, a source and a drain on the substrate, and then forming a first passivation layer covers the source, the drain, the semiconductor layer and the gate insulating layer, and then a second passivation layer is formed to cover the first passivation layer, and finally a second transparent electrode is formed on the second passivation layer, wherein The deposition power of the first passivation layer is less than 5,500 watts, and the deposition power of the second passivation layer is greater than 5,000 watts.

In one embodiment of the present invention, the method for fabricating a liquid crystal display panel array substrate, wherein the deposition reaction gas of the first passivation layer is decane and ammonia.

In one embodiment of the invention, the deposition reaction gases used in the first passivation layer are decane and ammonia.

In one embodiment of the invention, the gas flow rate of the deposited reaction gas is less than 6500 standard milliliters per minute.

In one embodiment of the invention, the first passivation layer formed is deposited to a thickness of 50 to 250 angstroms.

In an embodiment of the invention, the second passivation layer is a single layer structure or a multilayer structure.

In one embodiment of the present invention, the second passivation layer may be two layers, or may be three or more layers, but is not limited thereto. And the deposition pressure of the second passivation layer is 1500 MPa or more. The gases forming the deposition reaction of this second passivation layer are decane and ammonia.

In the above method for fabricating a liquid crystal display panel array substrate, the first transparent electrode layer is a pixel electrode, and the second transparent electrode layer is a common electrode. The material of the pixel electrode is indium oxide selenium.

In order to make the invention more apparent, the preferred embodiments are described in detail below. The preferred embodiments of the invention are provided with corresponding reference numerals.

For the first embodiment, please refer to FIG. 2A to FIG. 2G. FIG. 2A to FIG. 2G are diagrams showing the manufacturing process of the IPS type display panel array substrate. As shown in FIG. 2A, a substrate 100 is provided. The substrate can be a glass substrate or a plastic. Substrate, substrate of other suitable materials. A metal film is then formed by sputtering. The metal film may be made of aluminum, molybdenum, tungsten or an alloy thereof, and has a thickness of 2100 angstroms to 3,300 angstroms, preferably 2,500 angstroms to 3,000 angstroms. Then, a developing etching process is performed by wet etching or dry etching to form a patterned gate electrode 10 and a gate line (not shown).

As shown in FIG. 2B, a gate insulating layer 20 is formed on the substrate 100 and the gate electrode 10 by chemical vapor deposition, the gate insulating layer has a thickness of 3300 angstroms to 4000 angstroms, and the gate insulating layer may be yttrium oxide. , bismuth nitride or bismuth oxynitride, but is not limited thereto.

Next, as shown in FIG. 2C, a semiconductor layer is deposited, wherein the semiconductor has a thickness of 1600 angstroms to 2000 angstroms, wherein the semiconductor layer can be divided into a bottom layer channel layer 30 and an upper layer impurity layer 40, wherein the channel layer 30 is made of a material Amorphous germanium, while the doped layer is formed by the doping of phosphorus ions in the amorphous germanium. To form a more electrically conductive thin film transistor, the channel layer 30 can be formed by two different deposition rates, with the bottom layer of the channel layer 30 being deposited in a low velocity deposition and the upper layer of the channel layer 30 being deposited by high speed. The etching process is also performed by a development etching method to form an island-shaped semiconductor.

Next, as shown in FIG. 2D, a first electrode is formed by sputtering, wherein the first electrode has a thickness of 300 angstroms to 500 angstroms, and the first electrode is a pixel electrode 50, and the material of the pixel electrode can be It is indium oxide selenide or indium zinc oxide, and is subjected to a development etching process to form a predetermined pattern.

After the pixel electrode 50 is formed, as shown in FIG. 2E, the source and drain electrodes are to be formed next, first by sputtering or otherwise forming a metal layer, and then etching the metal layer into a predetermined shape source by development etching. 61, the drain 62 and the data line (not shown), when etching the source drain electrode, it should be noted that the exposed impurity layer 40 in the middle of the source and drain must be completely etched and over-etched until the channel layer is exposed. 40.

Next, a passivation layer is formed, as shown in FIG. 2F. First, a first passivation layer 71 is formed. The first passivation layer 71 has a thickness of 50 angstroms to 250 angstroms, and the deposition reaction gas is decane and ammonia gas, wherein the reaction gas is The gas flow is less than 6500 standards and the deposited power is less than 5000 watts. Next, a second passivation layer 72 is formed, and the reaction gas is also deposited as decane and ammonia. To maintain the deposition rate, the deposition pressure of the second passivation layer is 1500 MPa or more. In order to maintain excellent insulation and protection properties, the whole The passivation layer comprises first and second passivation layers having a total thickness of from 2000 angstroms to 6500 angstroms. It is particularly noted that the deposition power when depositing the first passivation layer is less than 5500 watts. Please refer to FIG. 4. FIG. 4 is a schematic diagram showing the relationship between deposition power and transmittance, wherein the horizontal axis represents the deposition power, and the vertical axis represents The transmittance of the array substrate is such that when the deposition power exceeds 5,500 watts, the penetration rate will decrease significantly due to the damage to the pixel electrode 50 during the deposition process, and the penetration rate remains at about 5,500 watts. The highest level, therefore, the deposition power is less than 5500 watts when depositing the first passivation layer 71. It is also worth noting that in order to maintain the transmittance of the passivation layer itself, the deposition power of the deposited second passivation layer should be greater than 5000 watts, please refer to FIG. 5, which is the relationship between the deposition power and the transmittance of the second passivation layer. Schematic diagram, wherein the horizontal axis represents the power of deposition, and the vertical axis represents the transmittance of the array substrate. When the deposition power exceeds 5000 watts, the transmittance will increase significantly, so the deposition power needs to be greater than that in the deposition of the second passivation layer. 5000 watts. The formation of the passivation layer is critical to the effect of the transmittance, which is mainly due to the damage to the underlying pixel electrode 50 when depositing the passivation layer, such as the precipitation of oxygen in the pixel electrode, or excessive hydrogen ions. Entering the pixel electrode will cause the transmittance of the pixel electrode to decrease, thereby reducing the transmittance of the entire array substrate. Therefore, the present invention proposes a manufacturing method in which the passivation layer is formed in a plurality of layers of a common laminated structure, thereby avoiding damage to the pixel electrode and reducing the transmittance when the passivation layer is formed.

In order to further reduce the influence of the deposition process of the passivation layer on the pixel electrode 50, a gas heat treatment process may be performed on the pixel electrode before depositing the first passivation layer. The heat treatment gas of nitrogen, wherein the heat treatment power is less than 1000 watts, please refer to Figure 6. When the heat treatment power exceeds 1000 watts, the entire array substrate transmittance will decrease with the increase of power, therefore, the heat treatment power must be less than 1000 watts.

Finally, the common electrode is fabricated. As shown in FIG. 2G, a transparent electrode layer is formed on the second passivation layer 72 by sputtering to a thickness of 300 angstroms to 500 angstroms, and then the transparent electrode layer is formed by a development etching process. The second electrode layer 80, the second electrode layer is a comb-shaped electrode layer, and the second electrode is a common electrode layer, and the material is selected from the group consisting of indium zinc oxide and indium oxide selenium. After the formation of the common electrode layer, the process of the array substrate is substantially completed, and then the alignment film coating, liquid crystal dropping and bonding processes are formed to form the final liquid crystal display panel.

In the second embodiment of the present invention, referring to FIG. 3, the passivation layer in the present invention may be a multi-layered stacked structure. First, a substrate 100 may be provided. The substrate may be a glass substrate, a plastic substrate, or a substrate of other suitable materials. The patterned gate 10 and gate lines (not shown) are then formed by sputtering and photo-developing etching processes. Then, a gate insulating layer 20 is formed on the substrate 100 and the gate electrode 10 by chemical vapor deposition, and the gate insulating layer may be tantalum oxide, tantalum nitride or hafnium oxynitride, but is not limited thereto. Next, a semiconductor layer is deposited, wherein the semiconductor layer can be divided into a bottom channel layer 30 and an upper layer impurity layer 40. The channel layer 30 can be formed by two different deposition speeds, wherein the bottom layer of the channel layer 30 is deposited at a low speed. The deposition is performed while the upper layer of the channel layer 30 is deposited by high speed. The etching process is also performed by a development etching method to form an island-shaped semiconductor. Next, a first electrode is formed by sputtering, and the first electrode is a pixel electrode 50. The material of the pixel electrode may be indium oxide or indium zinc oxide, and a predetermined pattern is formed through a development etching process. After the pixel electrode 50 is formed, the source and drain electrodes are to be formed next. Immediately after the formation of the passivation layer, the formation of the passivation layer is critical to the effect of the transmittance, mainly because the damage to the underlying pixel electrode 50 is easily caused when depositing the passivation layer, for example, in the pixel electrode. The precipitation of oxygen, or excessive hydrogen ions entering the pixel electrode, causes the transmittance of the pixel electrode to decrease, thereby reducing the transmittance of the entire array substrate. Therefore, the present invention proposes a manufacturing method in which the passivation layer is formed in a plurality of layers of a common laminated structure, thereby avoiding damage to the pixel electrode and reducing the transmittance when the passivation layer is formed. Similarly, in order to further reduce the damage to the pixel electrode in the subsequent process, thereby reducing the transmittance, the process of heat treatment of the pixel electrode before depositing the first passivation layer, and at the same time, the heat treatment power is less than 1000 during the heat treatment process. watt. The gas to be treated with ruthenium is nitrogen, and then the passivation layer is produced. First, a first passivation layer 71 is formed. The first passivation layer 71 has a thickness of 50 angstroms to 250 angstroms, and the deposition reaction gas is decane and ammonia gas, wherein the gas flow rate of the reaction gas is less than 6500 standards, and particularly attention is paid to deposition. The deposition power of a passivation layer is less than 5,500 watts. Next, a second passivation layer 72 is formed, and the reaction gas is also deposited as decane and ammonia. To maintain the deposition rate, the deposition pressure of the second passivation layer is 1500 MPa or more. In order to maintain excellent insulation and protection properties, the whole The passivation layer includes first and second passivation layers having a total thickness of from 2000 angstroms to 6500 angstroms, and the second passivation layer comprises two layers, a second passivation layer underlayer 72 and a second passivation layer upper layer 73. Finally, the common electrode is formed, and a transparent electrode layer is formed on the second passivation layer 72 by sputtering to a thickness of 30 angstroms to 500 angstroms, and then the transparent electrode layer is formed into the second electrode layer 80 by a development etching process. The second electrode layer is a comb-shaped electrode layer, and the second electrode is a common electrode layer, and the material is selected from the group consisting of indium zinc oxide and indium oxide selenium. After the formation of the common electrode layer, the process of the array substrate is substantially completed, and then the alignment film coating, liquid crystal dropping and bonding processes are formed to form the final liquid crystal display panel.

It should be understood by those skilled in the art that the technical solutions described in the foregoing embodiments may be modified, or some of the technical features may be equivalently replaced; and the modifications or replacements do not deviate from the essence of the corresponding technical solutions. The spirit and scope of the technical solutions of the various embodiments of the present invention.

100. . . Substrate

10. . . Gate

20. . . Insulation

30. . . Channel layer

40. . . Miscellaneous layer

50. . . Pixel electrode

61, 62. . . Source and drain electrode

71, 72, 73. . . Passivation layer

80. . . Second electrode layer

1 is a schematic cross-sectional view of a prior art IPS type array substrate.

2A-2G are flow charts showing the fabrication of the array substrate of the present invention.

3 is a schematic view of another embodiment of the present invention.

Figure 4 is a graph showing the relationship between the power and transmittance of the first passivation layer deposited.

Figure 5 is a graph showing the relationship between the power and the transmittance of the second passivation layer deposited.

Figure 6 is a graph of power versus penetration for heat treatment of a pixel electrode prior to deposition of the first passivation layer.

100. . . Substrate

20. . . Gate insulating layer

30. . . Channel layer

40. . . Miscellaneous layer

50. . . Pixel electrode

61. . . Source

62. . . Drain

71. . . First passivation layer

72. . . Second passivation layer

80. . . Second electrode layer

Claims (11)

A method for fabricating a liquid crystal display panel array substrate, comprising the steps of: providing a substrate; sequentially forming a gate, a gate insulating layer, a semiconductor layer, a first transparent electrode, a source and a drain on the substrate; and forming a first The passivation layer covers the source, the drain, the semiconductor layer and the gate insulating layer, wherein the first passivation layer has a deposition power of less than 5500 watts; and then a second passivation layer is formed to cover the first passivation layer, wherein the first passivation layer The deposition power of the second passivation layer is greater than 5000 watts; then a second transparent electrode is formed on the passivation layer. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the deposition reaction gas of the first passivation layer is decane and ammonia. The method for fabricating a liquid crystal display panel array substrate according to claim 2, wherein the first passivation layer uses a gas flow rate of a deposition reaction gas of decane and ammonia of less than 6,500 standard milliliters per minute. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the first passivation layer is deposited to a thickness of 50 to 250 angstroms. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the second passivation layer has a multilayer structure. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the second passivation layer has a two-layer structure. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the second passivation layer has a deposition pressure of 1500 MPa or more. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the second passivation layer deposits a reaction gas of decane and ammonia. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the first transparent electrode layer is a pixel electrode. The method for fabricating a liquid crystal display panel array substrate according to claim 10, wherein the material of the pixel electrode is indium selenide. The method for fabricating a liquid crystal display panel array substrate according to claim 1, wherein the second transparent electrode layer is a common electrode.