CN109742150A - A kind of array substrate and its manufacturing method and display panel - Google Patents
A kind of array substrate and its manufacturing method and display panel Download PDFInfo
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- CN109742150A CN109742150A CN201811587014.2A CN201811587014A CN109742150A CN 109742150 A CN109742150 A CN 109742150A CN 201811587014 A CN201811587014 A CN 201811587014A CN 109742150 A CN109742150 A CN 109742150A
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Abstract
The invention discloses a kind of array substrate and its manufacturing method and display panels.The array substrate includes: substrate, and the grid electrode layer of the substrate surface is arranged in, and the gate insulating layer of the gate electrode layer surface is arranged in, and the active layer of the gate insulator layer surface is arranged in, the ohmic contact layer of the active layer surface is arranged in；The active layer includes the different sub- active layer of at least two layers of density, and the sub- active layer is arranged by the way of stacked on top.By the way that active layer to be layered, keeps the active layer overall processing time shorter than the process time of the active layer using single layer structure, save the active layer overall process time.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and its manufacturing method and display panels.
Background technique
As liquid crystal display panel, have a structure that array substrate including separating small interval provided opposite and
Colored filter, and it is filled with liquid crystal between them.On a side surface of array substrate, according to the sequence lamination of regulation
Mode be formed with the film layers such as conductor layer, active layer, ohmic contact layer, amorphous silicon, the insulating layer of predetermined pattern.It is led by these
Body layer, semiconductor layer, insulating layer etc. are formed for applying alive thin film transistor (TFT) (TFT:Thin Film to pixel electrode
Transistor).In addition, to the scan signal line (grid signal of the gate electrode of thin film transistor (TFT) transmission scanning signal
Line), formed by conductor layer to data signal line (source signal line) etc. of source electrode transmission data-signal, and by insulating layer
Mutually insulated.Ohmic contact layer has been easy residual in etching, it will usually increase etching period to guarantee that ohmic contact layer etches
Completely, it will increase the array substrate overall process time in this way, battle array can be balanced by reducing the other processing times of array substrate
The overall process time of column substrate.
In array substrate, since active layer needs to keep the characteristic of active switch, the processing time mistake of active layer
It is long, influence the array substrate overall process time.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of array substrate and its manufacturing method and display panels, with solution
The certainly too long problem of active layer processing time.
The invention discloses a kind of array substrate, the array substrate includes: substrate, and the grid of the substrate surface are arranged in
The gate insulating layer of the gate electrode layer surface is arranged in pole electrode layer, and the active of the gate insulator layer surface is arranged in
Layer, is arranged in the ohmic contact layer of the active layer surface；Wherein, the active layer includes that the son that at least two layers of density is different has
Active layer, the sub- active layer are arranged by the way of stacked on top.
Optionally, the active layer includes: the first sub- active layer that the gate insulator layer surface is arranged in, and is arranged in institute
The sub- active layer of third of the described second sub- active layer surface is arranged in the second sub- active layer for stating the first sub- active layer surface.
Optionally, the density of the described first sub- active layer is greater than the density of the described second sub- active layer and third and has
The density of active layer.
Optionally, the density of the described second sub- active layer is greater than the density of the sub- active layer of the third.
Optionally, the thickness of the described first sub- active layer, the second sub- active layer and the sub- active layer of the third is equal.
The invention also discloses a kind of manufacturing methods of array substrate, comprising steps of
Form substrate；
Grid electrode layer is formed over the substrate；
Gate insulating layer is formed on the grid electrode layer；
Active layer is formed on the gate insulating layer；And
Ohmic contact layer is formed on the active layer；
Wherein, the active layer includes the different sub- active layer of at least two layers of density, and the sub- active layer uses upper and lower heap
Folded mode arranges.
Optionally, described in the step of forming active layer on gate insulating layer, comprising steps of
The first sub- active layer is formed on the gate insulating layer；
The second sub- active layer is formed on the described first sub- active layer；And
The sub- active layer of third is formed on the described second sub- active layer；
Wherein, described in the step of forming the first sub- active layer on gate insulating layer, the first sub- active layer is logical
It crosses chemical vapor deposition method to be formed, and the sedimentation time of the first sub- active layer is between 60 seconds to 70 seconds.
Optionally, described in the step of forming the second sub- active layer on the first sub- active layer, the second sub- active layer
It is to be formed by chemical vapor deposition method, and the sedimentation time of the second sub- active layer is between 40 seconds to 50 seconds.
Optionally, described in the step of forming the sub- active layer of third on the second sub- active layer, the sub- active layer of third
It is to be formed by chemical vapor deposition method, and the sedimentation time of the sub- active layer of the third is between 30 seconds to 40 seconds.
The invention also discloses a kind of display panel, the display panel includes above-mentioned array substrate.
For the scheme that active layer only has one layer, active layer is divided into the structure of multilayer stacked on top by the application,
Since active layer is attached to the surface of the gate insulating layer, and electric action is had, it is active in order to keep the characteristic of active switch
Formation time of layer during processing procedure can be long；If active layer uses single layer structure, the overall structure of active layer
Relatively uniform, active layer will integrally keep the characteristic of active switch at the time of molding, improve manufacture difficulty, this undoubtedly makes active layer
Molding time extend；Active layer is layered by the application, forms active layer by multiple working procedure, but in addition to bottom
Sub- active layer need to keep the characteristic of active switch to need long period molding outer, other sub- active layers can be arbitrarily laid with
On undermost sub- active layer, the shorter time is only needed, using active layer overall processing time ratio layered using single
The process time of the active layer of layer structure is short；Additionally, due to undermost sub- active layer is located at because plated film time is longer, cause
Its film quality is more preferable, and ducting capacity more preferably, even if working as and increasing etching period causes the sub- active layer being located above in active layer to etch
The turn-on effect of active layer will not completely be influenced.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is the schematic diagram after a kind of illustrative array substrate etching；
Fig. 2 is a kind of illustrative schematic diagram increased after etching period after array substrate etching；
Fig. 3 is a kind of schematic diagram of illustrative array substrate；
Fig. 4 is a kind of schematic diagram of array substrate part-structure of one embodiment of the invention；
Fig. 5 is a kind of schematic diagram of array substrate part-structure of another embodiment of the present invention；
Fig. 6 is a kind of schematic diagram of array substrate part-structure of another embodiment of the present invention；
Fig. 7 is a kind of schematic diagram of array substrate part-structure of another embodiment of the present invention；
Fig. 8 is a kind of flow chart of manufacturing method of array base plate of one embodiment of the invention；
Fig. 9 is a kind of flow chart of manufacturing method of array base plate of another embodiment of the present invention；
Figure 10 is a kind of schematic diagram of display panel of another embodiment of the present invention.
Wherein, 100, display panel；200 array substrates；210, substrate；220, grid electrode layer；230, gate insulating layer；
240, active layer；250, ohmic contact layer；260, source-drain electrode layer；241, the first sub- active layer；242, the second sub- active layer；
243, the sub- active layer of third；244, the 4th sub- active layer；245, the 5th sub- active layer.
Specific embodiment
It is to be appreciated that term used herein above, disclosed specific structure and function details, it is only for description
Specific embodiment is representative, but the application can be implemented by many alternative forms, be not construed as only
It is limited to the embodiments set forth herein.
In the description of the present application, term " first ", " second " are used for description purposes only, and it is opposite to should not be understood as instruction
Importance, or implicitly indicate the quantity of indicated technical characteristic.As a result, unless otherwise indicated, " first ", " are defined
Two " feature can explicitly or implicitly include one or more of the features；The meaning of " plurality " is two or two
More than.Term " includes " and its any deformation, mean and non-exclusive include, it is understood that there may be or addition is one or more that other are special
Sign, integer, step, operation, unit, component and/or combination thereof.
In addition, "center", " transverse direction ", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner",
The term of the orientation or positional relationship of the instructions such as "outside" is that orientation or relative positional relationship based on the figure describe, only
Be that the application simplifies description for ease of description, rather than indicate signified device or element must have a particular orientation,
It is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.
Furthermore unless specifically defined or limited otherwise, term " installation ", " connected ", " connection " shall be understood in a broad sense, example
Such as it may be fixed connection or may be dismantle connection, or integral connection；It can be mechanical connection, be also possible to be electrically connected
It connects；It can be directly connected, it can also indirectly connected through an intermediary or the connection inside two elements.For ability
For the those of ordinary skill in domain, the concrete meaning of above-mentioned term in this application can be understood as the case may be.
As shown in Figure 1, this is ohm in a kind of array substrate 200 between active layer 240 and source-drain electrode layer 260
Schematic diagram of the contact layer 250 after generally etch, wherein N indicates 250 residue of ohmic contact layer；As shown in Fig. 2, increasing
After the etching period for adding ohmic contact layer 250, residue can be etched completely, and gate insulating layer 230 can be etched a part,
Stair-stepping pattern is formed, wherein dotted line indicates state when gate insulating layer 230 is not etched, and solid line indicates gate insulating layer
State after 230 etchings；It may determine that the degree for increasing etching period by this stair-stepping pattern, judge ohmic contact layer
Whether the residue in 250 is etched completely.
As shown in figure 3, array substrate 200 includes: substrate 210 in the array substrate 200 that inventor understands；Gate electrode
Layer 220, is arranged in the surface of substrate 210；The surface of grid electrode layer 220 is arranged in gate insulating layer 230；Active layer 240,
The surface of gate insulating layer 230 is set；The surface of active layer 240 is arranged in ohmic contact layer 250；Wherein, active layer 240
For single layer structure.In order to keep the characteristic of active switch, precision requirement is higher during fabrication, and active layer 240 is in processing procedure process
In whole homogeneity should be kept to keep the characteristic of active switch again, forming the time can be long.
Below with reference to the accompanying drawings the invention will be further described with optional embodiment.
As shown in Figures 4 to 7, the embodiment of the present invention discloses a kind of array substrate 200, and array substrate 200 includes actively
Switch, active switch includes: substrate 210, and the grid electrode layer 220 on 210 surface of substrate is arranged in, and is arranged in grid electrode layer
The active layer 240 on 230 surface of gate insulating layer is arranged in the gate insulating layer 230 on 220 surfaces, is arranged on 240 surface of active layer
Ohmic contact layer 250；Wherein, active layer 240 includes the different sub- active layer of at least two layers of density, and sub- active layer is using up and down
The mode of stacking arranges.
Above-mentioned active switch is thin film transistor (TFT), and substrate 210 is the outermost structure of array substrate 200, generally glass
Material, grid electrode layer 220 and source, drain electrode layer generally use copper and aluminum material, and gate insulating layer 230 generally uses silicon nitride
Material and silica material, active layer 240 and ohmic contact layer 250 are typically all hydrogenated amorphous silicon material.In the present solution, due to
Active layer 240 is attached to the surface of gate insulating layer 230, and has electric action, in order to keep the characteristic of active switch, active layer
240 formation time during processing procedure can be long；If active layer 240 use single layer structure, active layer 240 it is whole
Body structure is relatively uniform, and the whole characteristic that will keep active switch of active layer 240, improves manufacture difficulty, this nothing at the time of molding
Doubting extends the molding time of active layer 240；Active layer 240 is layered by the application, and active layer 240 is made to pass through multiple working procedure
It is formed, but in addition to the sub- active layer of bottom needs to keep the characteristic of active switch to need long period molding outer, others
Sub- active layer can be arbitrarily laid on undermost sub- active layer, the shorter time only be needed, using active layer layered
The overall processing time is shorter than the process time of the active layer using single layer structure；Additionally, due to be located at undermost sub- active layer because
It is longer for plated film time, cause its film quality more preferable, ducting capacity more preferably, even if working as and increasing etching period causes to be located in active layer
The sub- active layer etching of top will not completely influence the turn-on effect of active layer.
In one embodiment, as shown in figure 4, active layer 240 includes the first sub- active layer 241, the second sub- 242 and of active layer
The surface of gate insulating layer 230 is arranged in the sub- active layer 243 of third, the first sub- active layer 241, and the second sub- active layer 242 is arranged
On the surface of the first sub- active layer 241, the surface of the second sub- active layer 242 is arranged in the sub- active layer 243 of third.By active layer
240 are divided into three layers, i.e., the first sub- active layer 241, the second sub- active layer 242 and the sub- active layer 243 of third, three layers of structure are adding
There are more regulation spaces between working hour, it can be according to the shape for requiring regulation the second sub- active layer 242 and the sub- active layer 243 of third
At the time, the forming process of entire active layer 240 is made to keep stablizing；If active layer 240 is divided into four layers or more, that
The forming process of active layer is just more complicated, needs the molding of four or more process completion active layer 240, and will be active
The number of plies of layer point is more, and thickness is smaller, the more bad control in processing.
In one embodiment, the density of the first sub- active layer 241 is greater than the density and third of the second sub- active layer 242
The density of active layer 243.Active layer 240 is divided into three layers by different by density, and the will be bonded with gate insulating layer 230
The density of one sub- active layer 241 accomplishes maximum, because the first sub- active layer 241 needs to keep the characteristic of active switch, when processing
Between longest, processing the sub- active layer 241 of density biggish first in the process will not influence process time of its script, and due to
First sub- active layer 241 undertakes the main electrical conduction function of active layer 240, so needing better protecting effect, Yi Mianzeng
Add and etches active layer 240 completely when the etching period of ohmic contact layer 250, the ratio that the density of the first sub- active layer 241 is done
The density of second sub- active layer 242 and the density of the sub- active layer 243 of third are big, in this way when etching the first sub- active layer 241,
The sub- active layer 241 of the first of greater density can be such that etching period slows down.
In one embodiment, the density of the second sub- active layer 242 is greater than the density of the sub- active layer 243 of third.Density is smaller
Process time is shorter, and it is exactly the processing time in order to reduce active layer 240 that active layer 240, which is layered most important purpose, and son has
More up its requirement is lower in active layer, and the density of the sub- active layer 243 of third is further decreased, active layer can be further reduced
240 overall process time.
In one embodiment, as shown in figure 5, the thickness of the thickness L1 of the first sub- active layer 241, the second sub- active layer 242
The thickness L3 of L2 and the sub- active layer 243 of third is equal.By the thickness of the thickness L1 of the first sub- active layer 241, the second sub- active layer 242
The thickness L3 of degree L2 and the sub- active layer 243 of third is consistent, relatively uniform in this way on conducting effect；Secondly in processing
Three layers of thickness control is consistent so that it is convenient to process, do not need the thickness parameter for separating each sub- active layer of regulation.
In one embodiment, as shown in fig. 6, active layer 240 includes the 4th sub- active layer 244 and the 5th sub- active layer 245,
The surface of gate insulating layer 230 is arranged in 4th sub- active layer 244, and the table of the 4th insulating layer is arranged in the 5th sub- active layer 245
It face and is affixed with ohmic contact layer 250.Active layer 240 is divided into double-layer structure, such active layer 240 only needs two procedures just
It can complete, can achieve the effect that reduce 240 processing time of active layer, also not need excessive procedure of processing.
In one embodiment, the density of the 4th sub- active layer 244 is greater than the density of the 5th sub- active layer 245.Density is bigger
Process time is longer, but since the plated film time of the 4th sub- active layer 244 itself is longer, processing precise degree is more demanding, increases
Large effect is not had to its process time if big density, and the density for increasing by the 4th sub- active layer 244 can also be one
Determine to reduce rate when being etched in degree, it is not high as the processing request of the 5th sub- active layer 245, when in order to reduce processing procedure
Between the density of the 5th sub- active layer 245 can be done it is a little bit smaller.
In one embodiment, as shown in fig. 7, the thickness L4 of the 4th sub- active layer 244 less than the 5th sub- active layer 245 thickness
Spend L5.Because the 4th sub- active layer 244 needs to keep the characteristic of active switch, processing request is higher, and when increasing, the 4th son is active
When the thickness L4 of layer 244, process time also be will increase, and the thickness of the 4th sub- active layer 244, which is done, a little bit smaller can reduce it
Process time, and the 5th sub- active layer 245 is since manufacture requires relatively low, manufacturing time is short, done it is thick a little increased plus
It is smaller between working hour, so the thickness L4 of the 4th sub- active layer 244 is enable to reduce less than the thickness L5 of the 5th sub- active layer 245
The whole process time of active layer 240.
As another embodiment of the present invention, a kind of array substrate 200 is disclosed, array substrate 200 includes: substrate 210；
The surface of substrate 210 is arranged in grid electrode layer 220；The surface of grid electrode layer 220 is arranged in gate insulating layer 230；The
One active layer 241, is arranged in the surface of gate insulating layer 230；The table of the first active layer 241 is arranged in second active layer 242
Face；The surface of the second active layer 242 is arranged in third active layer 243；Ohmic contact layer 250 is arranged in third active layer 243
Surface.
As another embodiment of the present invention, as shown in figure 8, a kind of manufacturing method of array substrate 200 is disclosed, including
Step:
S81: substrate is formed；
S82: grid electrode layer is formed on the substrate；
S83: gate insulating layer is formed on grid electrode layer；
S84: active layer is formed on gate insulating layer；
S85: ohmic contact layer is formed on active layer；
Wherein, active layer 240 includes the different sub- active layer of at least two layers of density, and the sub- active layer uses stacked on top
Mode arrange.
In one embodiment, as shown in figure 9, in S84 step, comprising steps of
S91: the first sub- active layer is formed on gate insulating layer；
S92: the second sub- active layer is formed on the first sub- active layer；
S93: the sub- active layer of third is formed on the second sub- active layer；
Wherein, the first sub- active layer 241, the second sub- active layer 242 and the sub- active layer 243 of third are all to pass through chemical gaseous phase
Deposition method is formed；In S91 step, the sedimentation time of the first sub- active layer 241 is between 60 seconds to 70 seconds；In S92 step
In, the sedimentation time of the second sub- active layer 242 is between 40 seconds to 50 seconds；In S93 step, the sub- active layer 243 of third sinks
The product time is between 30 seconds to 40 seconds.And the first sub- active layer 241, the second sub- active layer 242 and the sub- active layer 243 of third exist
It requires to be heated in forming process, the temperature of three sub- active layers in particular during a heating process is all identical, at 340 degree
To between 360 degree.
As shown in Figure 10, as another embodiment of the present invention, a kind of display panel 100, including above-mentioned array are disclosed
Substrate 200.
Technical solution of the present invention can be widely applied to various display panels, such as twisted nematic (Twisted
Nematic, TN) display panel, plane conversion type (In-Plane Switching, IPS) display panel, vertical orientation type
(Vertical Alignment, VA) display panel, more quadrant vertical orientation type (Multi-Domain Vertical
Alignment, MVA) display panel, it is of course also possible to be other kinds of display panel, such as Organic Light Emitting Diode
(Organic Light-Emitting Diode, OLED) display panel, applicable above scheme.
The above content is specific optional embodiment is combined, further detailed description of the invention, cannot recognize
Fixed specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs,
Without departing from the inventive concept of the premise, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention
Protection scope.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Substrate；
The surface of the substrate is arranged in grid electrode layer；
The surface of the grid electrode layer is arranged in gate insulating layer；
The surface of the gate insulating layer is arranged in active layer；And
The surface of the active layer is arranged in ohmic contact layer；
Wherein, the active layer includes the different sub- active layer of at least two layers of density, and the sub- active layer is using stacked on top
Mode arranges.
2. a kind of array substrate as described in claim 1, which is characterized in that the active layer includes:
First sub- active layer, is arranged in the surface of the gate insulating layer；
The surface of the described first sub- active layer is arranged in second sub- active layer；And
Third has edge layer, and the surface of the described second sub- active layer is arranged in.
3. a kind of array substrate as claimed in claim 2, which is characterized in that the density of the first sub- active layer is greater than described
The density of second sub- active layer and the density of the sub- active layer of the third.
4. a kind of array substrate as claimed in claim 3, which is characterized in that the density of the second sub- active layer is greater than described
The density of the sub- active layer of third.
5. a kind of array substrate as claimed in claim 2, which is characterized in that the first sub- active layer, second son have
The thickness of active layer and the sub- active layer of the third is equal.
6. a kind of manufacturing method of array substrate, which is characterized in that comprising steps of
Form substrate；
Grid electrode layer is formed over the substrate；
Gate insulating layer is formed on the grid electrode layer；
Active layer is formed on the gate insulating layer；And
Ohmic contact layer is formed on the active layer；
Wherein, the active layer includes the different sub- active layer of at least two layers of density, and the sub- active layer is using stacked on top
Mode arranges.
7. a kind of manufacturing method of array substrate as claimed in claim 6, which is characterized in that the shape on gate insulating layer
In the step of active layer, comprising steps of
The first sub- active layer is formed on the gate insulating layer；
The second sub- active layer is formed on the described first sub- active layer；And
The sub- active layer of third is formed on the described second sub- active layer；
Wherein, described in the step of forming the first sub- active layer on gate insulating layer, the first sub- active layer is passing through
It learns vapor deposition method to be formed, and the sedimentation time of the first sub- active layer is between 60 seconds to 70 seconds.
8. a kind of manufacturing method of array substrate as claimed in claim 7, which is characterized in that described on the first sub- active layer
In the step of forming the second sub- active layer, the second sub- active layer is formed by chemical vapor deposition method, and described
The sedimentation time of two sub- active layers is between 40 seconds to 50 seconds.
9. a kind of manufacturing method of array substrate as claimed in claim 7, which is characterized in that described on the second sub- active layer
In the step of forming third sub- active layer, the sub- active layer of third is formed by chemical vapor deposition method, and described the
The sedimentation time of three sub- active layers is between 30 seconds to 40 seconds.
10. a kind of display panel, which is characterized in that including the array substrate as described in claim 1 to 5 any one.
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Application publication date: 20190510 |
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