CN106158882B - A kind of display device, display panel, array substrate and preparation method thereof - Google Patents
A kind of display device, display panel, array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN106158882B CN106158882B CN201610854258.7A CN201610854258A CN106158882B CN 106158882 B CN106158882 B CN 106158882B CN 201610854258 A CN201610854258 A CN 201610854258A CN 106158882 B CN106158882 B CN 106158882B
- Authority
- CN
- China
- Prior art keywords
- layer
- via hole
- electrode
- source electrode
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 103
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 78
- 239000010409 thin film Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 295
- 238000002161 passivation Methods 0.000 claims description 53
- 238000005530 etching Methods 0.000 claims description 27
- 239000010408 film Substances 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000009413 insulation Methods 0.000 claims description 11
- 239000002344 surface layer Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 8
- 239000007772 electrode material Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003447 ipsilateral effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention provides a kind of display devices, display panel, array substrate and preparation method thereof, including substrate and the multiple thin film transistor (TFT)s being disposed on the substrate；Thin film transistor (TFT) includes semiconductor layer, grid, source electrode and drain electrode, and semiconductor layer is arranged on the surface of the substrate, and source electrode and drain electrode is successively set on the surface of semiconductor layer, and has insulating layer between source electrode and semiconductor layer, has planarization layer between drain electrode and source electrode；Source electrode is connect by the first via hole through insulating layer with semiconductor layer, and drain electrode through the second via hole of planarization layer and insulating layer with semiconductor layer by connecting.Since drain electrode and source electrode are located at different layers, and there is planarization layer between source electrode and drain electrode, therefore, even if the size for increasing via hole between drain electrode and pixel electrode will not cause source electrode and drain electrode to be shorted, so as to by the size for increasing via hole between drain electrode and pixel electrode, to solve the problems, such as that drain electrode and contact resistance between pixel electrode are excessive and are easy to appear and contact exception.
Description
Technical field
The present invention relates to display equipment technical fields, more specifically to a kind of display device, display panel, array
Substrate and preparation method thereof.
Background technique
A kind of array substrate is disclosed in the prior art, which includes substrate, a plurality of grid being disposed on the substrate
Polar curve, multiple data lines and the multiple pixel units limited by a plurality of grid line and multiple data lines insulation intersection, it is each
A pixel unit all includes pixel electrode and thin film transistor (TFT).Certainly, which further includes providing to multiple pixel units
The public electrode etc. of common voltage.
With reference to Fig. 1, Fig. 1 is the schematic diagram of the section structure of above-mentioned array substrate, wherein thin film transistor (TFT) includes being arranged in base
Semiconductor layer 110, the grid 111 being arranged on semiconductor layer 110 on plate 10 and the source electrode 112 being arranged on grid 111
With drain electrode 113.Wherein, there is gate insulating layer 114, source electrode 112 and drain electrode 113 are located between semiconductor layer 110 and grid 111
Same layer has interlayer insulating film 115, has planarization layer between drain electrode 113 and public electrode 12 between the two and grid 111
13, there is passivation layer 15, pixel electrode 14 is by running through passivation layer 15, public electrode between public electrode 12 and pixel electrode 14
12 and the via hole 140 of planarization layer 13 113 be electrically connected with drain electrode.
Requirement with people to display device pixel is higher and higher, and the area of pixel unit is increasingly in array substrate
It is small, so that the size L of via hole 140 is smaller and smaller, it will lead to the contact electricity between pixel electrode 14 and drain electrode 113 in this way
It hinders larger.Also, the problems such as too small size L is easy to cause via hole 140 to break, and then lead to pixel electrode 14 and drain electrode
113 contacts are abnormal.Although the size L for increasing via hole 140 can solve problem of the contact resistance greatly with contact exception, increase
The size L of big via hole 140 is easy to cause source electrode 112 and drain electrode 113 to be shorted again, influences the performance of thin film transistor (TFT).
Summary of the invention
In view of this, the present invention provides a kind of display device, display panel, array substrate and preparation method thereof, with
While increasing via size between pixel electrode and drain electrode, the short circuit of source electrode and drain electrode is avoided.
To achieve the above object, the invention provides the following technical scheme:
A kind of array substrate, multiple thin film transistor (TFT)s including substrate and setting on the substrate；
The thin film transistor (TFT) includes semiconductor layer, grid, source electrode and drain electrode, and the semiconductor layer is arranged in the substrate
Surface, the source electrode and described drain are successively set on the surface of the semiconductor layer, and the source electrode and the semiconductor
There is insulating layer between layer, there is planarization layer between the drain electrode and the source electrode；
The source electrode is connect by the first via hole through the insulating layer with the semiconductor layer, and the drain electrode is by passing through
The second via hole for wearing the planarization layer and the insulating layer is connect with the semiconductor layer.
A kind of display panel, including array substrate and the opposite substrate being oppositely arranged with the array substrate, the battle array
Column substrate is array substrate as described above.
A kind of display device, including display panel as described above.
A kind of production method of array substrate, is applied to array substrate as described above, and the production method includes:
Substrate is provided；
Semiconductor layer, insulating layer, source electrode, planarization layer and drain electrode are sequentially formed in the substrate surface, the source electrode is logical
The first via hole crossed through the insulating layer is connect with the semiconductor layer, and the drain electrode is by running through the planarization layer and institute
The second via hole for stating insulating layer is connect with the semiconductor layer.
Compared with prior art, the technical scheme provided by the invention has the following advantages:
Display device provided by the present invention, display panel, array substrate and preparation method thereof, due to source electrode and drain electrode according to
The secondary surface that semiconductor layer is arranged in, i.e. drain electrode and source electrode are located at different layers, and have the flat of insulation between source electrode and drain electrode
Change layer, therefore, source electrode and drain electrode will not be caused to be shorted even if increasing the size of via hole between drain electrode and pixel electrode, so as to
With by increase drain electrode pixel electrode between via hole size, come solve drain electrode pixel electrode between contact resistance it is excessive with
And it is easy to appear the abnormal problem of contact.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of existing the schematic diagram of the section structure of array substrate；
Fig. 2 is the overlooking structure diagram of array substrate provided in an embodiment of the present invention；
Fig. 3 is a kind of the schematic diagram of the section structure of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 4 is the schematic diagram of the section structure of another thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of the section structure of another thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 6 is a kind of the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention；
Fig. 7 is the schematic diagram of the section structure of another array substrate provided in an embodiment of the present invention；
Fig. 8 is a kind of the schematic diagram of the section structure of display panel provided in an embodiment of the present invention；
Fig. 9 is the schematic diagram of the section structure of another display panel provided in an embodiment of the present invention；
Figure 10 is the flow chart of the production method of array substrate provided in an embodiment of the present invention；
Figure 11 is a kind of flow chart of the production method of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 12 is the flow chart of the production method of another thin film transistor (TFT) provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment provides a kind of array substrates, and with reference to Fig. 2, Fig. 2 is array provided in an embodiment of the present invention
The overlooking structure diagram of substrate, the array substrate include substrate 20, a plurality of grid line 21, a plurality of number of setting on the base plate 20
Intersect the multiple pixel units 23 limited and multiple pixels according to line 22, by a plurality of grid line 21 and the insulation of multiple data lines 22
Public electrode 24 that unit 23 is correspondingly arranged, the gate driving circuit 25 being connected with a plurality of grid line and with 22 phase of multiple data lines
Display driver chip even includes data drive circuit 26 etc. in display driver chip.
Wherein, each pixel unit 23 includes pixel electrode 230 and thin film transistor (TFT) 231 again.Gate driving circuit 25
Scanning signal is provided to corresponding thin film transistor (TFT) 231 by grid line 21, to control the unlatching of thin film transistor (TFT) 231.Film is brilliant
After body pipe 231 is opened, data drive circuit 26 is mentioned by data line 22 and thin film transistor (TFT) 231 to corresponding pixel electrode 230
For data-signal, so as to form the electricity that driving pixel unit 23 performs image display between pixel electrode 230 and public electrode 24
?.
With reference to Fig. 3, Fig. 3 is a kind of the schematic diagram of the section structure of thin film transistor (TFT) provided in an embodiment of the present invention, the film
Transistor 231 includes semiconductor layer 2310, grid 2311, source electrode 2312 and drain electrode 2313, wherein the setting of semiconductor layer 2310 exists
The surface that the surface of substrate 20, source electrode 2312 and drain electrode 2313 are successively set on semiconductor layer 2310, and source electrode 2312 and partly lead
There is insulating layer 2314 between body layer 2310, there is planarization layer 2315 between drain electrode 2313 and source electrode 2312.
Wherein, source electrode 2312 is connect by the first via hole A1 through insulating layer 2314 with semiconductor layer 2310, is drained
2313 through the second via hole A2 of planarization layer 2315 and insulating layer 2314 with semiconductor layer 2310 by connecting.Furthermore, it is desirable to
Illustrate, also there is light shield layer 201 between substrate 20 and semiconductor layer 2310 and the buffering on 201 surface of light shield layer is set
Layer 202, wherein the backlight that light shield layer 201 is used to that backlight module to be stopped to be emitted influences the performance of semiconductor layer 2310.
In structure shown in Fig. 3, grid 2311 is arranged between source electrode 2312 and semiconductor layer 2310, also, grid
There is gate insulating layer 2314a between 2311 and semiconductor layer 2310, there is layer insulation between grid 2311 and source electrode 2312
Layer 2314b, that is to say, that insulating layer 2314 includes gate insulating layer 2314a and interlayer insulating film 2314b.Based on this, source electrode
2312 are connect by the first via hole A1 through gate insulating layer 2314a and interlayer insulating film 2314b with semiconductor layer 2310, are leaked
Pole 2313 by through planarization layer 2315, gate insulating layer 2314a and interlayer insulating film 2314b the second via hole A2 with partly lead
Body layer 2310 connects.
Wherein, thin film transistor (TFT) shown in Fig. 3 is the thin film transistor (TFT) of top gate structure, due to its grid 2311, source electrode
2312 are located at the same side of semiconductor layer 2310 with drain electrode 2313, and therefore, which has cut-in voltage lower and work
Make the advantages that electric current is larger.Certainly, the present invention is not limited to this, and in other embodiments, thin film transistor (TFT) can also be bottom
The thin film transistor (TFT) of grid structure.
Thin film transistor (TFT) provided in this embodiment, due to forming drain electrode 2313, use and source electrode using new film layer
2312 different film layers overlap semiconductor layer 2310, and drain electrode 2313 forms staggered floor with source electrode 2312, can increase and source electrode
The width of the data line cabling of 2312 same layers reduces the broken string risk of source electrode, data wire metal layer at interlayer insulating film.Such as
Shown in Fig. 4, Fig. 4 is the schematic diagram of the section structure of another thin film transistor (TFT) provided in an embodiment of the present invention, wherein grid 2311
It is arranged between semiconductor layer 2310 and substrate 20, also, there is gate insulating layer between grid 2311 and semiconductor layer 2310
2314a.At this point, the insulating layer 2314 between source electrode 2312 and semiconductor layer 2310 is interlayer insulating film.Due to grid 2311, source
Pole 2312 and drain electrode 2313 are located at the not ipsilateral of semiconductor layer 2310, and therefore, grid 2311, source electrode 2312 and drain electrode 2313 are mutually
Between parasitic capacitance it is smaller, the performance of thin film transistor (TFT) is more stable.
In Fig. 3 and structure shown in Fig. 4, it can be existed after forming planarization layer 2315 by an etching technics
The corresponding region second via hole A2 performs etching to form the second via hole A2, and certainly, the present invention is not limited to this, in other implementations
In example, the second via hole A2 can be formed by twice etching technique.
It is illustrated for the thin film transistor (TFT) of the structure shown in Fig. 3, it is exhausted in the grid to the first corresponding region via hole A1
While edge layer 2314a and interlayer insulating film 2314b perform etching to form the first via hole A1, to the second corresponding region via hole A2
Gate insulating layer 2314a and interlayer insulating film 2314b performs etching to form the first sub- via hole A21, then in interlayer insulating film
The surface 2314b forms source electrode 2312, and during forming source electrode 2312, part source electrode material can be filled into the first sub- via hole
In A21.Planarization layer 2315 is formed on 2312 surface of source electrode later, to the planarization layer of the first corresponding region sub- via hole A21
2315 perform etching to form the second sub- via hole A22, which is connected to the first sub- via hole A21, are planarizing later
2315 surface of layer form drain electrode 2313, and in the process, drain material can be filled into the second sub- via hole A22.Due to source electrode material
Material and drain material are all conductive metal material, and therefore, drain electrode 2313 and semiconductor layer 2310 can pass through the first sub- via hole A21
With the second sub- via hole A22 electrical connection.
Based on this, with reference to Fig. 5, Fig. 5 is that the cross-section structure of another thin film transistor (TFT) provided in an embodiment of the present invention is illustrated
Figure.Second via hole A2 includes the first sub- sub- via hole A22 of via hole A21 and second, and the first sub- via hole A21 is grid through insulating layer 2314
Pole insulating layer 2314a and interlayer insulating film 2314b, the second sub- via hole A22 run through planarization layer 2315, and the first sub- via hole A21
It is interconnected with the second sub- via hole A22.When forming the second via hole A2 by twice etching technique, since the film layer etched every time is thick
Degree is all smaller, therefore, it is possible to reduce the thickness of photoresist layer when etching not only reduces the remaining risk of photoresist, and not
The problem of being easy to appear the second via hole A2 broken string, also, it is initially formed the first sub- via hole A21, can follow-up process half-and-half be led
The influence of body layer 2310 is smaller, further, since the second sub- via hole A22 is formed in above the first sub- via hole A21, also, drains
2313 thickness is adjustable, therefore, is less prone to the problem of film layers such as the pixel electrode 230 above the second sub- via hole A22 are broken.
The structure of array substrate is illustrated by taking thin film transistor (TFT) 231 shown in Fig. 3 as an example below, as shown in fig. 6, figure
6 be a kind of the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention, which further includes being successively set on
Drain first passivation layer 2301 and pixel electrode 230 on 2313 surfaces, and the second passivation layer of pixel electrode surface is arranged in
240 and public electrode 24.Wherein, pixel electrode 230 by through the first passivation layer 2301 third via hole A3 and drain electrode 2313
Connection.Based on this, when thin film transistor (TFT) 231 is opened, source electrode 2312 and drain electrode 2313 pass through the first via hole A1, semiconductor layer
2310 and the second via hole A2 conducting, source electrode 2312 and drain electrode 2313 and the of the data-signal that data line 22 inputs by conducting
Three via hole A3 are transmitted to pixel electrode 230.
In another embodiment of the invention, as shown in fig. 7, Fig. 7 is another array base provided in an embodiment of the present invention
The schematic diagram of the section structure of plate, the array substrate further include the second passivation layer 241, public for being successively set on 2313 surfaces of drain electrode
Electrode 24, the first passivation layer 2301 and pixel electrode 230.Wherein, pixel electrode 230 passes through through the second passivation layer 241, public
4th via hole A4 of electrode 24 and the first passivation layer 2301 is connect with drain electrode 2313, and pixel electrode 230 and 24 phase of public electrode
Mutually insulation.
In Fig. 6 and structure shown in Fig. 7, since source electrode 2312 and drain electrode 2313 are located at different layers, and 2312 He of source electrode
There is the planarization layer 2315 of insulation, therefore, even if increasing the between drain electrode 2313 and pixel electrode 230 between drain electrode 2313
The size L1 of three via hole A3 or the 4th via hole A4 will not cause source electrode 2312 and drain electrode 2313 to be shorted, so as to by appropriate
Increase the size L1 of third via hole A3 or the 4th via hole A4, to solve contact resistance mistake between drain electrode 2313 and pixel electrode 230
Problem that is big and being easy to appear contact exception.
It should be noted that the semiconductor layer 2310 in the present embodiment is polysilicon layer, gate insulating layer 2314a, interlayer
Insulating layer 2314b, planarization layer 2315, the first passivation layer 2301 and the second passivation layer 240 are made by insulating materials
, the specific material present invention does not limit.
Array substrate provided by the present invention drains since source electrode and drain electrode is successively set on the surface of semiconductor layer
With source electrode different layers, and between source electrode and drain electrode have insulation planarization layer, therefore, even if increase drain electrode with pixel electrode it
Between the size of via hole source electrode and drain electrode will not be caused to be shorted, so as to by suitably increasing mistake between drain electrode and pixel electrode
The size in hole, to solve the problems, such as that drain electrode and contact resistance between pixel electrode are excessive and are easy to appear and contact exception.
The embodiment of the invention also provides a kind of display panel, the display panel include array substrate and with the array base
The opposite substrate that plate is oppositely arranged, the array substrate are the array substrate that any of the above-described embodiment provides.Wherein, opposite substrate can
Think that color membrane substrates, display panel can be liquid crystal display panel, or (Light Emitting Diode's LED shines
Diode) or OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display panel etc..
It is illustrated so that display panel is liquid crystal display panel as an example, as shown in Figure 8 and Figure 9, Fig. 8 is the embodiment of the present invention
A kind of the schematic diagram of the section structure of the display panel provided, Fig. 9 are cuing open for another display panel provided in an embodiment of the present invention
Face structural schematic diagram, the display panel include array substrate 1, opposite substrate 2 and are arranged in array substrate 1 and opposite substrate 2
Between multiple supporters 3, the (not shown)s such as liquid crystal layer, one end which contacts with array substrate 1 is located at adjacent
Two the second via hole A2 between.
As shown in Figure 8 and Figure 9, pixel electrode 230 above the second via hole A2 and the second via hole A2 etc. forms protrusion B1,
And between two adjacent the second via hole A2, due to drain electrode formed protrusion, it is corresponding, can two neighboring via hole A2 it
Between formed recess B2.And protrusion B1 can be adjusted by drain metal thickness, and drain metal thickness is thicker, and what is formed accordingly is prominent
It is higher to play B1.The B2 that is recessed is located between two protrusion B1, and corresponding recess B2 will be deeper.As shown in figure 8, supporter 3 with
One end that array substrate 1 contacts can be entrenched between the corresponding two protrusions B1 of two adjacent the second via hole A2, that is, be limited
Within recess B2, is slided, avoided due to support with limiting supporter 3 by the corresponding two protrusion B1 of two the second via hole A2
Object 3 slides caused leakage problem.Alternatively, as shown in figure 9, one end that supporter 3 is contacted with array substrate 1 can be with adjacent two
A protrusion B1 contact, i.e. supporter 3 and array substrate tool are there are two supporting point, the table contacted due to array substrate 1 with supporter 3
The not smooth surface in face has ups and downs surface, accordingly it is also possible to play the role of limiting the sliding of supporter 3.
Also, as shown in Figure 8 and Figure 9, compared to the display panel of the prior art in Fig. 1, pixel electrode 230 passes through passivation layer
It can be electrically connected with the drain electrode 2313 being located on planarization layer 2315, be different from pixel electrode in the prior art and need across passivation
Layer and planarization layer are just electrically connected with drain electrode.Since passivation layer thickness is significantly smaller than planarization layer thickness, via hole company is improved
The reliability connect.
Display panel provided by the present invention, not only can be by suitably increasing the ruler of via hole between drain electrode and pixel electrode
It is very little, to solve the problems, such as that drain electrode and contact resistance between pixel electrode are excessive and are easy to appear and contact exception, moreover, it is also possible to
Size between thickness and two neighboring second via hole or one end for being contacted with array substrate of supporter by the way that film layer is arranged
Size so that one end that supporter is contacted with array substrate is entrenched between two adjacent the second via holes, and then can limit
Supporter sliding processed, avoids leakage problem caused by sliding due to supporter.
The embodiment of the invention also provides a kind of display devices, including display panel provided by the above embodiment.
The embodiment of the invention also provides a kind of production methods of array substrate, provide applied to any of the above-described embodiment
Array substrate, as shown in Figure 10, Figure 10 are the flow chart of the production method of array substrate provided in an embodiment of the present invention, the production
Method includes:
S101: substrate is provided；
S102: semiconductor layer, insulating layer, source electrode, planarization layer and drain electrode are sequentially formed in the substrate surface, source electrode is logical
The first via hole crossed through insulating layer is connect with semiconductor layer, drain electrode by the second via hole through planarization layer and insulating layer with
Semiconductor layer connection.
Wherein, thin film transistor (TFT) includes semiconductor layer, grid, source electrode and drain electrode etc., that is to say, that substrate surface successively
Forming semiconductor layer, insulating layer, source electrode, planarization layer and the process of drain electrode is exactly to form the mistake of thin film transistor (TFT) in substrate surface
Journey, in one embodiment of the invention, as shown in figure 11, Figure 11 is a kind of thin film transistor (TFT) provided in an embodiment of the present invention
The flow chart of production method sequentially forms semiconductor layer, insulating layer, source electrode, planarization layer and the process of drain electrode in substrate surface
Include:
S110: semiconductor layer and insulating layer are sequentially formed in the substrate surface；
S111: performing etching the insulating layer, forms the first via hole for running through the insulating layer；
S112: source electrode is formed in the surface of insulating layer, so that the source electrode is partly led by first via hole with described
The connection of body layer；
S113: planarization layer is formed on the source electrode surface；
S114: performing etching the planarization layer and the insulating layer, formed through the planarization layer and it is described absolutely
Second via hole of edge layer；
S115: forming on the planarization layer surface and drain, so that the drain electrode passes through second via hole and described half
Conductor layer connection.
With reference to Fig. 3, it is exhausted that light shield layer 201, buffer layer 202, semiconductor layer 2310, grid first are sequentially formed on 20 surface of substrate
Then edge layer 2314a, grid 2311 and interlayer insulating film 2314b are that gate insulating layer 2314a and interlayer are exhausted to insulating layer 2314
Edge layer 2314b is performed etching, and forms the first via hole A1 for running through insulating layer 2314, forms source on the surface interlayer insulating film 2314b
Pole 2312 forms on 2312 surface of source electrode and planarizes so that source electrode 2312 is connect by the first via hole A1 with semiconductor layer 2310
Layer 2315, performs etching the planarization layer 2315 and insulating layer 2314 of the second corresponding region via hole A2, is formed through planarization
Second via hole A2 of layer 2315 and insulating layer 2314 forms drain electrode 2313 on 2315 surface of planarization layer, so that drain electrode 2313 is logical
The second via hole A2 is crossed to connect with semiconductor layer 2310.
In another embodiment of the invention, as shown in figure 12, Figure 12 is another film provided in an embodiment of the present invention
The flow chart of the production method of transistor sequentially forms semiconductor layer, insulating layer, source electrode, planarization layer in the substrate surface
Include: with drain electrode
S120: semiconductor layer and insulating layer are sequentially formed in the substrate surface；
S121: performing etching the insulating layer, forms the first via hole and the second sub- via hole for running through the insulating layer；
S122: source electrode is formed in the surface of insulating layer, so that the source electrode is partly led by first via hole with described
The connection of body layer；
S123: planarization layer is formed on the source electrode surface；
S124: performing etching the planarization layer of the described first sub- via hole corresponding region, is formed and runs through the planarization layer
And the second sub- via hole being connect with the described first sub- via hole；
S125: forming on the planarization layer surface and drain, so that the drain electrode passes through the described second sub- via hole and described
First sub- via hole is connect with the semiconductor layer.
With reference to Fig. 5, light shield layer 201, buffer layer 202, semiconductor layer 2310, gate insulator are sequentially formed on 20 surface of substrate
Then layer 2314a, grid 2311 and interlayer insulating film 2314b are gate insulating layer 2314a and layer insulation to insulating layer 2314
Layer 2314b is performed etching, and the sub- via hole A21 of the first via hole A1 and first for running through insulating layer 2314 is formed, in 2314 table of insulating layer
Face forms source electrode 2312, so that source electrode 2312 is connect by the first via hole A1 with semiconductor layer 2310, is forming source electrode 2312
In the process, part source electrode material can be filled into the first sub- via hole A21.Planarization layer is formed on 2312 surface of source electrode later
2315, the planarization layer 2315 of the first corresponding region sub- via hole A21 is performed etching, is formed through planarization layer 2315 and with the
Second sub- via hole A22 of one sub- via hole A21 connection forms drain electrode 2313 on 2315 surface of planarization layer later, in the process,
Part drain material can be filled into the second sub- via hole A22.Since source electrode material and drain material are all conductive metal material,
Therefore, drain electrode 2313 and semiconductor layer 2310 can be electrically connected by the first sub- sub- via hole A22 of via hole A21 and second.
In a kind of production method of array substrate provided in this embodiment, substrate surface sequentially form semiconductor layer,
After insulating layer, source electrode, planarization layer and drain electrode, further includes:
The first passivation layer is formed in the drain surface；
First passivation layer is performed etching, the third via hole for running through first passivation layer is formed；
Pixel electrode is formed in first passivation layer surface, so that the pixel electrode passes through the third via hole and institute
State drain electrode connection.
With reference to Fig. 6, draining, 2313 surfaces form the first passivation layer 2301, perform etching to the first passivation layer 2301, shape
At the third via hole A3 for running through the first passivation layer 2301, pixel electrode 230 is formed on 2301 surface of the first passivation layer, so that pixel
Electrode 230 is connect by third via hole A3 with drain electrode 2313.
In the production method of another array substrate provided in this embodiment, semiconductor is sequentially formed in substrate surface
After layer, insulating layer, source electrode, planarization layer and drain electrode, further includes:
The second passivation layer, public electrode and the first passivation layer are sequentially formed in the drain surface；
First passivation layer, public electrode and the second passivation layer are performed etching, formed through first passivation layer,
4th via hole of the public electrode and second passivation layer；
Pixel electrode is formed in first passivation layer surface, so that the pixel electrode passes through the 4th via hole and institute
Drain electrode connection is stated, the pixel electrode and the public electrode insulate.
With reference to Fig. 7, draining, 2313 surfaces sequentially form the second passivation layer 241, public electrode 24 and the first passivation layer
2301, the first passivation layer 2301, public electrode 24 and the second passivation layer 241 are performed etching, is formed and runs through the first passivation layer
2301, the 4th via hole A4 of public electrode 24 and the second passivation layer 241 forms pixel electrode on 2301 surface of the first passivation layer
230, so that pixel electrode 230 is connect by the 4th via hole A4 with drain electrode 2313.
Wherein, pixel electrode 230 and public electrode 24 insulate, optionally, can be after forming public electrode 24, to public
The region corresponding with the 4th via hole A4 of electrode 24 performs etching, and passes through the conduction material in the 4th via hole A4 to avoid public electrode 24
Material is connect with pixel electrode 230.
The production method of array substrate provided by the present invention sequentially forms source electrode and drain electrode on the surface of semiconductor layer,
So that drain electrode and source electrode different layers, and the planarization layer due to having insulation between source electrode and drain electrode, even if increasing drain electrode
The size of via hole will not cause source electrode and drain electrode to be shorted between pixel electrode, so as to by suitably increasing drain electrode and picture
The size of via hole between plain electrode, come solve drain electrode with contact resistance between pixel electrode it is excessive and be easy to appear contact extremely
The problem of.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (13)
1. a kind of array substrate, which is characterized in that including the multiple thin film transistor (TFT)s of substrate and setting on the substrate；
The thin film transistor (TFT) includes semiconductor layer, grid, source electrode and drain electrode, and the table of the substrate is arranged in the semiconductor layer
Face, the source electrode and described drain are successively set on the surface of the semiconductor layer, and the source electrode and the semiconductor layer it
Between have insulating layer, it is described drain electrode the source electrode between have planarization layer；
The source electrode is connect by the first via hole through the insulating layer with the semiconductor layer, and the drain electrode is by running through institute
The second via hole for stating planarization layer and the insulating layer is connect with the semiconductor layer；
It further include pixel electrode, the pixel electrode is arranged and is electrically connected to each other with the different layer of drain electrode.
2. array substrate according to claim 1, which is characterized in that the array substrate further include be successively set on it is described
The first passivation layer and pixel electrode of the drain surface of thin film transistor (TFT)；
The pixel electrode is connect by the third via hole through first passivation layer with the drain electrode of the thin film transistor (TFT).
3. array substrate according to claim 1, which is characterized in that the array substrate further include be successively set on it is described
The second passivation layer, public electrode, the first passivation layer and the pixel electrode of thin film transistor (TFT) drain surface；
The pixel electrode passes through the 4th via hole through first passivation layer, the public electrode and second passivation layer
It is connect with the drain electrode of the thin film transistor (TFT), and the pixel electrode and the public electrode insulate.
4. array substrate according to claim 1, which is characterized in that grid setting is in the source electrode and described partly leads
Between body layer, there is gate insulating layer between the grid and the semiconductor layer, have between the grid and the source electrode
Interlayer insulating film, the insulating layer include the gate insulating layer and the interlayer insulating film；
Alternatively, the grid is arranged between the semiconductor layer and the substrate, between the grid and the semiconductor layer
With gate insulating layer.
5. array substrate according to claim 1, which is characterized in that second via hole includes the first sub- via hole and second
Sub- via hole, the first sub- via hole run through the insulating layer, and the second sub- via hole runs through the planarization layer, and described first
Sub- via hole and the second sub- via hole are interconnected.
6. a kind of display panel, which is characterized in that including array substrate and the opposite base being oppositely arranged with the array substrate
Plate, the array substrate are array substrate described in any one of claim 1 to 5.
7. display panel according to claim 6, which is characterized in that further include setting in the array substrate and described right
To multiple supporters between substrate；
One end that above support is contacted with the array substrate is between two adjacent second via holes.
8. a kind of display device, which is characterized in that including display panel described in claim 6 or 7.
9. a kind of production method of array substrate, which is characterized in that be applied to array base described in any one of claim 1 to 5
Plate, the production method include:
Substrate is provided；
Semiconductor layer, insulating layer, source electrode, planarization layer and drain electrode are sequentially formed in the substrate surface, the source electrode is by passing through
The first via hole for wearing the insulating layer is connect with the semiconductor layer, it is described drain electrode by through the planarization layer and it is described absolutely
Second via hole of edge layer is connect with the semiconductor layer；
Pixel electrode is formed in the drain surface, the pixel electrode is arranged and is electrically connected to each other with the different layer of drain electrode.
10. according to the method described in claim 9, it is characterized in that, sequentially forming semiconductor layer, insulation in the substrate surface
Layer, source electrode, planarization layer and drain electrode include:
Semiconductor layer and insulating layer are sequentially formed in the substrate surface；
The insulating layer is performed etching, the first via hole for running through the insulating layer is formed；
Source electrode is formed in the surface of insulating layer, so that the source electrode is connect by first via hole with the semiconductor layer；
Planarization layer is formed on the source electrode surface；
The planarization layer and the insulating layer are performed etching, second through the planarization layer and the insulating layer is formed
Via hole；
It is formed and is drained on the planarization layer surface, so that the drain electrode is connected by second via hole and the semiconductor layer
It connects.
11. according to the method described in claim 9, it is characterized in that, sequentially forming semiconductor layer, insulation in the substrate surface
Layer, source electrode, planarization layer and drain electrode include:
Semiconductor layer and insulating layer are sequentially formed in the substrate surface；
The insulating layer is performed etching, the first via hole and the first sub- via hole for running through the insulating layer are formed；
Source electrode is formed in the surface of insulating layer, so that the source electrode is connect by first via hole with the semiconductor layer；
Planarization layer is formed on the source electrode surface；
The planarization layer of described first sub- via hole corresponding region is performed etching, is formed through the planarization layer and with described the
Second sub- via hole of one sub- via hole connection；
It is formed and is drained on the planarization layer surface, so that the drain electrode passes through the described second sub- via hole and the first sub- via hole
It is connect with the semiconductor layer.
12. according to the method described in claim 9, it is characterized in that, forming pixel electrode in the drain surface, comprising:
The first passivation layer is formed in the drain surface；
First passivation layer is performed etching, the third via hole for running through first passivation layer is formed；
Pixel electrode is formed in first passivation layer surface, so that the pixel electrode passes through the third via hole and the leakage
Pole connection.
13. according to the method described in claim 9, it is characterized in that, forming pixel electrode in the drain surface, comprising:
The second passivation layer, public electrode and the first passivation layer are sequentially formed in the drain surface；
First passivation layer, public electrode and the second passivation layer are performed etching, formed through first passivation layer, described
4th via hole of public electrode and second passivation layer；
Pixel electrode is formed in first passivation layer surface, so that the pixel electrode passes through the 4th via hole and the leakage
Pole connection, the pixel electrode and the public electrode insulate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610854258.7A CN106158882B (en) | 2016-09-27 | 2016-09-27 | A kind of display device, display panel, array substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610854258.7A CN106158882B (en) | 2016-09-27 | 2016-09-27 | A kind of display device, display panel, array substrate and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106158882A CN106158882A (en) | 2016-11-23 |
| CN106158882B true CN106158882B (en) | 2019-02-26 |
Family
ID=57340964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610854258.7A Active CN106158882B (en) | 2016-09-27 | 2016-09-27 | A kind of display device, display panel, array substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106158882B (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531692A (en) * | 2016-12-01 | 2017-03-22 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, and display apparatus |
| KR102618350B1 (en) * | 2016-12-14 | 2023-12-28 | 삼성디스플레이 주식회사 | Display device |
| CN108346620A (en) | 2017-01-23 | 2018-07-31 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN106920804B (en) | 2017-04-28 | 2020-03-24 | 厦门天马微电子有限公司 | Array substrate, driving method thereof, display panel and display device |
| CN107167972A (en) * | 2017-06-12 | 2017-09-15 | 昆山龙腾光电有限公司 | Array base palte and preparation method thereof and display device |
| CN107180598A (en) * | 2017-07-21 | 2017-09-19 | 武汉华星光电技术有限公司 | A kind of array base palte and display panel |
| CN107240590B (en) * | 2017-07-24 | 2020-01-17 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN107490917A (en) | 2017-09-27 | 2017-12-19 | 武汉华星光电技术有限公司 | A kind of thin-film transistor array base-plate and display device |
| CN107706224B (en) * | 2017-09-30 | 2020-09-04 | 武汉华星光电技术有限公司 | Display panel and manufacturing method thereof |
| CN107611181A (en) * | 2017-10-26 | 2018-01-19 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and its manufacture method, display device |
| CN107799538B (en) * | 2017-10-26 | 2020-06-19 | 上海天马微电子有限公司 | Display panel and display device |
| CN108008582A (en) * | 2017-11-22 | 2018-05-08 | 深圳市华星光电半导体显示技术有限公司 | A kind of tft array substrate, production method and liquid crystal display panel |
| CN108010945B (en) * | 2017-11-28 | 2021-08-10 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110085601A (en) * | 2018-01-26 | 2019-08-02 | 华为技术有限公司 | A kind of array substrate and preparation method thereof, display panel, terminal device |
| CN108550612B (en) * | 2018-05-29 | 2020-11-13 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN109410751B (en) * | 2018-10-30 | 2021-04-27 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, display panel and display device |
| CN111244128A (en) * | 2018-11-29 | 2020-06-05 | 上海和辉光电有限公司 | Display panel and display device |
| CN110649043B (en) * | 2019-09-30 | 2021-11-19 | 厦门天马微电子有限公司 | Array substrate, display panel, display device and preparation method of array substrate |
| CN111863842B (en) * | 2020-07-31 | 2022-08-05 | Oppo广东移动通信有限公司 | Electronic equipment, display module and display panel thereof |
| CN112802878B (en) * | 2020-12-30 | 2024-01-30 | 天马微电子股份有限公司 | Display panel and display device |
| CN113514991B (en) * | 2021-04-06 | 2023-10-17 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN113238418B (en) * | 2021-04-14 | 2022-09-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113325636B (en) * | 2021-05-28 | 2023-07-11 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN113433724B (en) * | 2021-07-05 | 2022-09-09 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN115032842B (en) * | 2022-07-01 | 2023-11-28 | 武汉华星光电技术有限公司 | Display panel and display terminal |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196668A (en) * | 2006-12-07 | 2008-06-11 | 三菱电机株式会社 | Display device and method of producing the same |
| CN101527307A (en) * | 2008-03-07 | 2009-09-09 | 三星电子株式会社 | Thin film transistor panel and manufacturing method of the same |
| CN102683338A (en) * | 2011-09-13 | 2012-09-19 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof |
| CN103943649A (en) * | 2013-02-15 | 2014-07-23 | 上海天马微电子有限公司 | OLED (Organic Light-Emitting Display) display panel and driving method thereof |
| CN104538421A (en) * | 2014-12-16 | 2015-04-22 | 深圳市华星光电技术有限公司 | OLED display substrate and manufacturing method of OLED display substrate |
| CN104576705A (en) * | 2015-01-27 | 2015-04-29 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| CN105470266A (en) * | 2016-01-04 | 2016-04-06 | 武汉华星光电技术有限公司 | FFS (fringe field switching) type array substrate and manufacturing method therefor |
| CN105679765A (en) * | 2016-01-12 | 2016-06-15 | 武汉华星光电技术有限公司 | TFT array substrate structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100611148B1 (en) * | 2003-11-25 | 2006-08-09 | 삼성에스디아이 주식회사 | Thin Film Transistors, method of manufacturing thereof and an Electroluminescent display device |
-
2016
- 2016-09-27 CN CN201610854258.7A patent/CN106158882B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196668A (en) * | 2006-12-07 | 2008-06-11 | 三菱电机株式会社 | Display device and method of producing the same |
| CN101527307A (en) * | 2008-03-07 | 2009-09-09 | 三星电子株式会社 | Thin film transistor panel and manufacturing method of the same |
| CN102683338A (en) * | 2011-09-13 | 2012-09-19 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof |
| CN103943649A (en) * | 2013-02-15 | 2014-07-23 | 上海天马微电子有限公司 | OLED (Organic Light-Emitting Display) display panel and driving method thereof |
| CN104538421A (en) * | 2014-12-16 | 2015-04-22 | 深圳市华星光电技术有限公司 | OLED display substrate and manufacturing method of OLED display substrate |
| CN104576705A (en) * | 2015-01-27 | 2015-04-29 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| CN105470266A (en) * | 2016-01-04 | 2016-04-06 | 武汉华星光电技术有限公司 | FFS (fringe field switching) type array substrate and manufacturing method therefor |
| CN105679765A (en) * | 2016-01-12 | 2016-06-15 | 武汉华星光电技术有限公司 | TFT array substrate structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106158882A (en) | 2016-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106158882B (en) | A kind of display device, display panel, array substrate and preparation method thereof | |
| US9711541B2 (en) | Display panel and method for forming an array substrate of a display panel | |
| US20240096910A1 (en) | Method of fabricating array substrate, array substrate and display device | |
| CN104699321B (en) | Touch display substrate and touch control display apparatus | |
| CN103296030B (en) | TFT-LCD array substrate | |
| CN109585462A (en) | A kind of array substrate and preparation method thereof, flexible display panels, mosaic screen | |
| CN207216226U (en) | Display device | |
| CN102315165B (en) | Edge electric field type liquid crystal display array substrate and manufacture method thereof | |
| CN104699356B (en) | Array base palte, touch-control display panel and touch control display apparatus | |
| CN204179080U (en) | Display device | |
| CN104716147B (en) | A kind of tft array substrate and preparation method thereof, display device | |
| CN103811499A (en) | Thin film transistor array panel and manufacturing method thereof | |
| US20160187752A1 (en) | Display panel and displaying device | |
| CN105655380A (en) | Organic light emission display panel | |
| CN109300995B (en) | Thin film transistor, manufacturing method thereof, array substrate and display panel | |
| CN106229310B (en) | Array substrate and preparation method thereof | |
| CN104090401A (en) | Array substrate, preparation method thereof and display device | |
| CN105572927A (en) | Array substrate and liquid crystal display panel | |
| EP3163617B1 (en) | Flexible substrate, flexible display panel and flexible display device | |
| CN204315573U (en) | A kind of array base palte, display floater and display unit | |
| US9429804B2 (en) | Display device and manufacturing method thereof | |
| CN104201178B (en) | Array base palte and preparation method thereof, display device | |
| CN103278989A (en) | Display panel, manufacturing method thereof and liquid crystal display | |
| CN209119104U (en) | A kind of array substrate, flexible display panels, mosaic screen | |
| CN104733477A (en) | Array substrate, manufacturing method of array substrate, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |