CN102683338A - Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof - Google Patents

Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof Download PDF

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CN102683338A
CN102683338A CN2011102700298A CN201110270029A CN102683338A CN 102683338 A CN102683338 A CN 102683338A CN 2011102700298 A CN2011102700298 A CN 2011102700298A CN 201110270029 A CN201110270029 A CN 201110270029A CN 102683338 A CN102683338 A CN 102683338A
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layer
drain
polysilicon
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photoresist
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CN102683338B (en
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马占洁
龙春平
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京东方科技集团股份有限公司
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Abstract

The embodiment of the invention provides a low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and a manufacturing method thereof, and relates to the field of manufacturing of liquid crystal displays and AMOLED (Active Matrix/Organic Light Emitting Diode) displays. The treatment frequency of a composition technology is reduced, so that the manufacturing flow is simplified and the manufacturing cost is reduced. The method provided by the invention comprises the following steps of: forming a buffer layer on a substrate; forming a polycrystalline silicon layer on the buffer layer; forming a first metal layer on the polycrystalline silicon layer; performing composition process treatment on the first metal layer and the polycrystalline silicon layer by using a gray tone mask plate or semitransparent mask plate; and obtaining patterns of a data line, a source electrode, a drain electrode and a polycrystalline silicon semiconductor part through one-time composition process. The embodiment of the invention is used for manufacturing the low-temperature polycrystalline silicon TFT array substrate.

Description

—种低温多晶硅TFT阵列基板及其制造方法 - Species LTPS TFT array substrate and manufacturing method

技术领域 FIELD

[0001] 本发明涉及液晶显示器及AMOLED显示器制造领域,尤其涉及一种低温多晶硅TFT (Thin Film Transistor,薄膜场效应晶体管)阵列基板及其制造方法。 [0001] The present invention relates to an AMOLED display and a liquid crystal display manufacturing, and more particularly, to a low temperature polysilicon TFT (Thin Film Transistor, thin film transistor) array substrate and a manufacturing method.

背景技术 Background technique

[0002] 由于非晶硅本身自有的缺陷问题,如缺陷太多导致的开态电流低、迁移率低、稳定性差,使使它在很多领域收到了限制,为了弥补非晶硅本身缺陷,扩大在相关领域的应用,LTPS(Low Temperature Poly-Silicon,低温多晶娃)技术应运而生。 [0002] Since the amorphous silicon itself its own defects, such as too many defects due to low on-state current, low mobility, poor stability, so that it received a limited number of areas, in order to compensate for deficiencies of amorphous silicon itself, applications in related fields expand, LTPS (Low Temperature Poly-Silicon, low-temperature polycrystalline doll) technology came into being.

[0003] 如图I、图2所示,现有技术中的低温多晶硅TFT阵列基板制造方法包括: [0003] FIG. I, as shown in FIG. 2, the low-temperature polysilicon TFT array substrate manufacturing method of the prior art comprises:

[0004] S101、在基板11上形成缓冲层12。 [0004] S101, the buffer layer 12 is formed on the substrate 11.

[0005] S102、通过第一次构图工艺处理,在缓冲层上形成多晶硅有源层图形。 [0005] S102, by a first patterning process, a polysilicon active layer pattern is formed on the buffer layer.

[0006] S103、将无机材料沉积在多晶娃有源层图形的整个表面,形成第一绝缘层14。 [0006] S103, the inorganic material is deposited over the entire surface of the polycrystalline active layer pattern of the baby, the first insulating layer 14 is formed.

[0007] S104、通过第二次构图工艺处理,在绝缘层上形成栅线、栅极15,之后对多晶硅进行掺杂、激活等处理形成多晶硅半导体有源层13。 [0007] S104, by a second patterning process, a gate line, a gate 15 is formed on the insulating layer, the polysilicon is then doped, forming a polysilicon activation treatment such active semiconductor layer 13.

[0008] S105、在栅线、栅极15上形成第二绝缘层16。 [0008] S105, a second insulating layer 16 is formed on the gate line, the gate electrode 15.

[0009] S106、通过第三次构图工艺处理,在第一绝缘层14和第二绝缘层16上形成源极过孔17a、漏极过孔17b,露出有源层13。 [0009] S106, through a third patterning process, a first insulating layer formed on the insulating layer 14 and the second through hole 16 of the source 17a, drain electrode 17b through the hole, the active layer 13 is exposed.

[0010] S107、通过第四次构图工艺处理,形成数据线、源极18a和漏极18b,其中,源极18a通过源极过孔17a与有源层13连接,漏极18b通过漏极过孔17b与有源层连接13。 [0010] S107, the fourth through the patterning process, a data line, a source electrode 18a and drain electrode 18b, wherein the source electrode 18a through the through hole 17a and the source electrode 13 is connected to the active layer, the drain electrode 18b through the drain through connector holes 17b and the active layer 13.

[0011] S108、在数据线、源极18a和漏极18b上形成保护层19,并通过第五次构图工艺处理在漏极18b上方形成过孔,露出漏极18b。 [0011] S108, the data line, the source electrode 18a and drain electrode 18b are formed on the protective layer 19, and processed through a fifth via hole patterning process is formed over the drain electrode 18b, exposing the drain 18b.

[0012] S109、通过第六次构图工艺处理形成ITO像素电极20,该ITO像素电极20通过过孔与漏极18b连接。 [0012] S109, 20 forming ITO pixel electrode patterning process through the sixth process, the ITO pixel electrode 20 and the drain electrode 18b through the via hole connection.

[0013] S110、通过第七次构图工艺处理,在基板上形成平坦化层21。 [0013] S110, the seventh through the patterning process, a planarization layer 21 is formed on the substrate.

[0014] 由上可以看出,现有技术中在低温多晶硅TFT阵列基板的制造过程中,需利用总计至少7次的构图工艺处理,制造工艺复杂,制造流程繁多,材料消耗多,增加了加工时间和加工成本。 [0014] As can be seen from the above, the prior art during manufacture of low-temperature polysilicon TFT array substrate, the need to use a total of at least 7 patterning process, the manufacturing process is complicated, many manufacturing processes, material consumption, increased processing time and processing costs.

发明内容 SUMMARY

[0015] 本发明的实施例提供一种低温多晶硅TFT阵列基板及其制造方法,减少了构图工艺处理次数,从而简化了制造流程,降低了制造成本。 Example [0015] The present invention provides a TFT array substrate and a low-temperature polycrystalline silicon manufacturing method reduces the number of patterning treatment process, thereby simplifying the manufacturing process, manufacturing costs are reduced.

[0016] 为达到上述目的,本发明的实施例采用如下技术方案: [0016] To achieve the above object, embodiments of the present invention adopts the following technical solutions:

[0017] —方面,提供一种低温多晶娃TFT阵列基板,包括: [0017] - aspect, there is provided a low-temperature polycrystalline baby TFT array substrate, comprising:

[0018]基板; [0018] a substrate;

[0019] 在缓冲层上形成有多晶硅半导体有源层; [0019] polycrystalline silicon semiconductor active layer formed on the buffer layer;

[0020] 所述多晶硅半导体有源层上形成有源极、漏极;所述源极、漏极与所述多晶硅半导体有源层构成TFT区域; [0020] The polysilicon is formed on the semiconductor active layer active electrode, the drain electrode; the source electrode, the drain of the TFT polycrystalline silicon semiconductor active layer region;

[0021] 所述源极、漏极上形成有栅绝缘层; [0021] The source electrode, gate insulating layer is formed on the drain;

[0022] 所述栅绝缘层上形成有栅极、栅线; [0022] A gate of the gate, a gate insulating layer on the line;

[0023] 所述栅极、栅线上形成有保护层; [0023] The gate electrode, gate line are formed with a protective layer;

[0024] 所述保护层上形成有像素电极层,所述像素电极层通过位于所述保护层、栅绝缘层上的过孔与所述漏极连接。 It is formed on [0024] the protective layer is a pixel electrode layer, the pixel electrode layer on the protective layer, a gate insulating layer on the via hole is connected to the drain electrode.

[0025] 还包括: [0025] further comprises:

[0026] 在形成有多晶硅半导体有源层之前,在所述基板上形成有缓冲层。 [0026] polycrystalline silicon is formed before the active semiconductor layer formed on the substrate with a buffer layer.

[0027] 另一方面,提供一种低温多晶硅TFT阵列基板的制造方法,包括: [0027] On the other hand, there is provided a method of manufacturing a low-temperature polysilicon TFT array substrate, comprising:

[0028] 在基板上形成多晶硅层; [0028] forming a polysilicon layer on a substrate;

[0029] 在所述多晶硅层上形成第一金属层,利用灰色调掩摸板或半透式掩摸板对所述第一金属层、多晶硅层进行构图工艺处理,通过第一次构图工艺得到数据线、源极、漏极和多晶娃半导体部分的图案; [0029] forming a first metal layer on said polysilicon layer, said first metal layer, a polysilicon layer patterning process using a gray-tone mask or a transflective formwork cover formwork, obtained by first patterning process data line, a source, a drain and a pattern of the polycrystalline semiconductor portion of the baby;

[0030] 通过第二次构图工艺在所述栅绝缘层上形成栅线、栅极; [0030] forming a gate line, a gate electrode on the gate insulating layer by a second patterning process;

[0031] 在所述源极、漏极和多晶硅半导体部分的图案上形成栅绝缘层; [0031] forming a gate insulating layer on the electrode, the drain electrode and patterning the polysilicon semiconductor source;

[0032] 对所述多晶硅层的源、漏极之间的部分进行掺杂处理,以便与所述源、漏极形成沟道区; [0032] The portion between the source of the polysilicon layer, drain doping process, so as to form a channel region and the source and drain;

[0033] 在所述栅线、栅极上形成保护层,通过第三次构图工艺在所述漏极处形成过孔,露出所述漏极; [0033] In the gate line, a gate is formed on the protective layer, forming a via through the drain of the third patterning process, to expose the drain electrode;

[0034] 在所述保护层上形成像素电极层,所述像素电极层通过所述过孔与所述漏极连接; [0034] The pixel electrode layer is formed on the protective layer, the pixel electrode layer through the via hole and the drain is connected;

[0035] 通过第四次构图工艺形成像素电极图形; [0035] The fourth pixel electrode pattern is formed by patterning process;

[0036] 在像素电极上通过第五次构图工艺形成平坦化层图形。 [0036] The planarization layer is formed by a fifth pattern on the pixel electrode patterning process.

[0037] 本发明实施例提供的低温多晶硅TFT阵列基板及其制造方法,在基板上形成缓冲层、涂布多晶硅层和金属层之后,通过HTM或GTM对金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到包括数据线、源极、漏极、多晶硅半导体部分的图案。 [0037] an embodiment of the low-temperature polysilicon TFT array substrate of the present invention and a manufacturing method for forming a buffer layer on a substrate, a polysilicon layer and after coating the metal layer, a metal layer patterning process, the polysilicon layer by HTM or GTM, obtained through one patterning process including a data line, a source, a drain, polysilicon semiconductor pattern. 较现有技术中先进行一次构图工艺处理得到多晶硅有源层图案,接着进行一次构图工艺处理得到源漏极与有源层的连接部分,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,从而降低了工序复杂度,减少了一层保护层,从而降低了工序复杂度,节省了材料,在缩短了加工时间的同时降低了加工成本。 Compared to the prior art, a patterning process is performed to obtain a polysilicon active layer pattern, followed by a connecting portion patterning process to obtain the source and drain of the active layer, and then patterning process to obtain a source, a drain, the process of reducing the exposure, thereby reducing the complexity of the process, a protective layer is reduced, thereby reducing the complexity of the process, the material is saved in reducing the processing time while reducing processing costs.

附图说明 BRIEF DESCRIPTION

[0038] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0038] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments the drawings are only some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0039] 图I为现有的低温多晶硅TFT阵列基板的制造方法的流程示意图; [0039] Figure I is a schematic flow of the method for producing the conventional low-temperature polysilicon TFT array substrate;

[0040] 图2为现有的低温多晶娃TFT阵列基板的结构不意图; [0040] FIG 2 is a conventional low-temperature polycrystalline structure of the baby is not intended TFT array substrate;

[0041] 图3a为利用灰色调掩模板进行光刻胶曝光的示意图;[0042] 图3b为利用半透调掩模板进行光刻胶曝光的示意图; [0041] Figure 3a is a schematic view of the exposure of the photoresist is performed using a gray-tone mask; [0042] FIG 3b of exposure of the photoresist is a schematic semipermeable tone mask;

[0043] 图4为本发明实施例一提供的多晶硅TFT阵列基板的制造方法的流程示意图; [0043] FIG. 4 is a schematic flow of the method for producing polycrystalline silicon TFT array substrate according to a first embodiment of the present invention;

[0044] 图5A为本发明实施例提供的制作多晶硅TFT阵列基板的第一示意图; [0044] FIG 5A is a first schematic produce polysilicon TFT array substrate according to an embodiment of the present invention;

[0045] 图5B为本发明实施例提供的制作多晶硅TFT阵列基板的第二示意图; [0045] FIG. 5B a schematic view of the second polycrystalline silicon TFT array substrate produced according to an embodiment of the present invention;

[0046] 图5C为本发明实施例提供的制作多晶硅TFT阵列基板的第三示意图; [0046] FIG. 5C present schematic produce a third polycrystalline silicon TFT array substrate according to an embodiment of the invention;

[0047] 图为本发明实施例提供的制作多晶硅TFT阵列基板的第四示意图; [0047] The picture shows a schematic view of a fourth production of polycrystalline silicon TFT array substrate according to an embodiment of the present invention;

[0048] 图5E为本发明实施例提供的制作多晶硅TFT阵列基板的第五示意图; [0048] FIG. 5E produced a fifth schematic view of a polysilicon TFT array substrate according to an embodiment of the present invention;

[0049] 图5F为本发明实施例提供的制作多晶硅TFT阵列基板的第六示意图; [0049] FIG. 5F present sixth production schematic polysilicon TFT array substrate to an embodiment of the invention;

[0050] 图5G为本发明实施例提供的制作多晶硅TFT阵列基板的第七示意图; [0050] FIG. 5G making a seventh schematic view of a polysilicon TFT array substrate according to an embodiment of the present invention;

[0051] 图5H为本发明实施例提供的制作多晶硅TFT阵列基板的第八示意图; [0051] FIG. 5H schematic present eighth production polysilicon TFT array substrate to an embodiment of the invention;

[0052] 图51为本发明实施例提供的制作多晶硅TFT阵列基板的第九示意图; [0052] FIG 51 a schematic view of making the present ninth polycrystalline silicon TFT array substrate according to an embodiment of the invention;

[0053] 图5G为本发明实施例提供的制作多晶硅TFT阵列基板的第十示意图; [0053] FIG. 5G production tenth schematic polysilicon TFT array substrate according to an embodiment of the present invention;

[0054] 图5K为本发明实施例提供的制作多晶硅TFT阵列基板的第十一示意图; [0054] FIG. 5K present eleventh schematic polysilicon TFT array substrate produced according to an embodiment of the invention;

[0055] 图5L为本发明实施例提供的制作多晶硅TFT阵列基板的第十二示意图; A schematic view of a twelfth making a polysilicon TFT array substrate according to an [0055] FIG. 5L present invention;

[0056] 图5M为本发明实施例提供的制作多晶硅TFT阵列基板的第十三示意图; A schematic view of a thirteenth making polycrystalline silicon TFT array substrate according to an embodiment [0056] FIG. 5M present invention;

[0057] 图5N为本发明实施例提供的制作多晶硅TFT阵列基板的第十四示意图; [0057] FIG. 5N fourteenth production schematic polysilicon TFT array substrate according to an embodiment of the present invention;

[0058] 图50为本发明实施例提供的制作多晶硅TFT阵列基板的第十五示意图; [0058] FIG 50 a schematic view of a fifteenth making polycrystalline silicon TFT array substrate according to an embodiment of the present invention;

[0059] 图5P为本发明实施例提供的制作多晶硅TFT阵列基板的第十六示意图; [0059] Production sixteenth schematic polysilicon TFT array substrate according to an embodiment of the present invention, FIG. 5P;

[0060] 图5Q为本发明实施例提供的制作多晶硅TFT阵列基板的第十七示意图; [0060] FIG. 5Q present invention produced seventeenth schematic polysilicon TFT array substrate according to an embodiment;

[0061] 图6为本发明实施例二提供的多晶硅TFT阵列基板的制造方法的流程示意图; [0061] FIG. 6 is a schematic flow of the method for producing polycrystalline silicon TFT array substrate according to a second embodiment of the present invention;

[0062] 图7为本发明实施例四提供的多晶硅TFT阵列基板的制造方法的流程示意图。 [0062] FIG 7 showing the method of manufacturing a polycrystalline silicon TFT array substrate according to a fourth embodiment of the present invention.

具体实施方式 Detailed ways

[0063] 下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0063] below in conjunction with the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described embodiments are merely part of embodiments of the present invention, but not all embodiments example. 基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of ordinary skill in the art without any creative effort shall fall within the scope of the present invention.

[0064] 实施例一 [0064] Example a

[0065] 本发明实施例一提供的低温多晶硅TFT阵列基板的制造方法,以利用灰色调掩模板(GTM)制造低温多晶硅TFT阵列基板为例进行说明。 According to a first embodiment of the low-temperature [0065] The present invention is a method for producing polycrystalline silicon TFT array substrate, to utilize gray tone mask (GTM) for producing a low temperature poly-silicon TFT array substrate will be described as an example.

[0066] 首先,参照图3a对GTM工艺的主要原理进行说明。 [0066] First, referring to FIG. 3a GTM main principle of the process will be described. GTM掩膜板是通过光栅效应,使曝光在不同区域透过光的强度不同,而使光刻胶进行选择性曝光、显影。 GTM plate through the grating effect, the exposure intensity of the transmitted light is different in different regions, the photoresist is selectively exposed and developed. 图3a表示利用GTM掩膜板21对光刻胶进行曝光处理的过程。 Figure 3a shows the use of the GTM plate 21 during the photoresist exposure process. 在GTM掩膜板21中,包括透明区域211、不透明区域212和半透明区域213。 In GTM plate 21, it comprises a transparent region 211, the opaque region 212 and the translucent area 213. 光刻胶22为曝光后的状态,其中,区域221对应GTM掩膜板21的透明区域211,区域222对应GTM掩膜板21的不透明区域212,区域223对应GTM掩膜板21的半透明区域213。 The photoresist 22 is exposed state, wherein the transparent region 221 corresponding to the region 21 of the GTM plate 211, region 222 corresponding to the opaque regions 21 of GTM plate 212, region 223 corresponding to the translucent area GTM plate 21 213. 光刻胶23为显影后的状态,其中,区域231对应GTM掩膜板21的透明区域211,区域232对应GTM掩膜板21的不透明区域212,区域233对应GTM掩膜板21的半透明区域213。 The photoresist 23 after development state, wherein the transparent region 231 corresponding to the region 21 of the GTM plate 211, region 232 corresponding to the opaque region 21 GTM plate 212, region 233 corresponding to the translucent area GTM plate 21 213.

[0067] 下面参照图4、图5A〜5Q对本发明实施例一提供的利用GTM的低温多晶硅TFT阵列基板的制造方法进行说明。 [0067] Referring to FIG 4, FIG 5A~5Q low temperature using a GTM embodiment provides a method of manufacturing a polycrystalline silicon TFT array substrate will be described embodiments of the present invention.

[0068] S401、在基板上形成缓冲层。 [0068] S401, forming a buffer layer on the substrate.

[0069] 为了防止玻璃基板中有害物质,如碱金属离子对多晶硅层性能的影响,在沉积缓冲层前要进行预清洗(Pre-clean)。 [0069] In order to prevent the glass substrate of harmful substances, such as alkali metal ions affect the performance of the polysilicon layer, prior to deposition of the buffer layer to pre-cleaned (Pre-clean). 具体的,首先通过初始清洁(Initial clean)工艺实现对玻璃基板的清洗,清洁度要符合粒子< 300ea(粒径> Ium)。 Specifically, the first to achieve cleaning of the glass substrate by initial cleaning (Initial clean) process, to meet cleanliness of particles <300ea (particle size> Ium). 而后,如图5A所示,采用PECVD法在玻璃基板51上沉积形成缓冲层52。 Then, as shown in FIG. 5A, a buffer layer 52 using a PECVD method is deposited on the glass substrate 51 is formed.

[0070] S402、在缓冲层上形成多晶硅层。 [0070] S402, a polysilicon layer is formed on the buffer layer.

[0071] 如图5B所示,采用PECVD法在缓冲层52上沉积一层非晶硅层,采用高温烤箱对非晶硅层进行脱氢工艺处理,以防止在晶化过程中出现氢爆现象以及降低晶化后薄膜内部的缺陷态密度作用。 [0071] shown in Figure 5B, a layer deposited by a PECVD amorphous silicon layer on the buffer layer 52, the amorphous silicon layer using a high temperature oven dehydrogenation process, to prevent the explosion of hydrogen during crystallization phenomenon and reducing the effect of internal defect density of the film after crystallization. 脱氢工艺完成后,进行LTPS工艺过程,采用激光退火工艺(ELA)、金属诱导结晶工艺(MIC)、固相结晶工艺(SPC)等结晶化手段对非晶硅层进行结晶化处理,在缓冲层52上形成多晶娃层53。 After completion of the dehydrogenation process, for LTPS process, a laser annealing (ELA), metal induced crystallization process (the MIC), a solid phase crystallization process (SPC) and other means of crystallization of amorphous silicon layer crystallization treatment, in a buffer layer 52 is formed on the polycrystalline layer 53 the baby.

[0072] S403、在多晶硅层上形成数据线、源极、漏极所用的第一金属层。 [0072] S403, the data line is formed on the polysilicon layer, the source electrode, the drain of the first metal layer is used.

[0073] 如图5C所不,利用派射工艺在多晶娃层上沉积第一金属层54。 [0073] FIG 5C do not use radio technology to send a first metal layer 54 is deposited on the polycrystalline layer baby.

[0074] S404、利用灰色调掩摸板,对第一金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到数据线、源极、漏极和多晶硅半导体部分图案。 [0074] S404, the gray-tone mask formwork, the first metal layer, a polysilicon layer patterning process is performed to obtain the data lines through one patterning process, the source, drain and polysilicon semiconductor pattern.

[0075] 如图所示,在上述结构的基板上涂覆一层光刻胶55,之后用GTM工艺对光刻胶55进行曝光处理。 [0075] As shown in the above-described structure is coated on a substrate a layer of photoresist 55, followed by 55 GTM in the photoresist exposure process. 该GTM掩膜板70上针对TFT区域,对应数据线(图中未表示)、源极、漏极区域的部分为不透明区域702,对应源、漏极区域之间的区域部分为半透明区域703。 The GTM plate 70 for a TFT region, the corresponding data line (not shown), the source electrode, the drain region is partially opaque area 702, corresponding to the source, the drain region portion of the region between the semi-transparent region 703 .

[0076] 如图5F所示为上述曝光后的光刻胶55的状态示意图,其中,光刻胶55的区域551对应GTM掩膜板70的不透明区域702,光刻胶55的区域552对应GTM掩膜板70的半透明区域703。 [0076] Figure 5F shows a state after the resist 55 is a schematic view of the exposure, wherein the region 551 of the photoresist 55 corresponding to the opaque region 702 GTM plate 70, the photoresist 55 corresponding to the region 552 GTM translucent mask area 703 70.

[0077] 如图5G所述为显影后的光刻胶55的状态示意图,其中,光刻胶55的区域551为光刻胶完全保留区域,光刻胶55的区域552为光刻胶半保留区域,其他区域为光刻胶完全去除区域。 [0077] FIG 5G is a state of the photoresist 55 after development diagram in which a region 551 of the photoresist 55 is completely retained photoresist region 55 of the photoresist region 552 is photoresist half-retained region, other regions as photoresist completely removed region.

[0078] 然后,如图5H所示,采用湿法刻蚀(Wet Etch)工艺对光刻胶完全去除区域的第一金属层54进行刻蚀,然后采用干法刻蚀(Dry Etch)工艺对多晶硅层53进行刻蚀。 [0078] Then, as shown in FIG. 5H, wet etching (Wet Etch) process on the first metal layer the photoresist is completely removed region 54 is etched, and then dry etching (Dry Etch) process on polysilicon layer 53 is etched.

[0079] 然后,如图51所示,经等离子体灰化处理,将光刻胶55的光刻胶半保留区域552的光刻胶刻蚀掉,余下光刻胶完全保留区域551的光刻胶,该光刻胶完全保留区域551对应源极、漏极区域。 [0079] Then, as shown in FIG. 51, the plasma ashing process, the photoresist half-retained region 552 of the photoresist 55, the photoresist is etched away, the remaining photoresist completely-retained region 551 of lithography glue, the photoresist completely-retained region 551 corresponding to the source and drain regions.

[0080] 然后,如图5J所示,再经过湿法刻蚀工艺对光刻胶半保留区域552的第一金属层54进行二次刻蚀。 [0080] Then, as shown in FIG. 5J, and then through a wet etching process the photoresist half-retained region 552 of the first metal layer 54 is etched secondary.

[0081] 然后,如图5K所示,剥离掉光刻胶完全保留区域551的光刻胶之后,得到源极542、漏极541。 After [0081] Then, as shown in FIG. 5K, the photoresist is peeled off completely-retained regions of the photoresist 551 to obtain the source 542, drain 541.

[0082] 至此,本实施例中,通过一次GTM构图工艺处理,得到了包括数据线、源极、漏极、多晶硅有源层的图案。 [0082] Thus, in this embodiment, by a patterning process GTM obtained including a data line, a source electrode, the drain electrode, the active layer of polysilicon pattern. 较现有技术中,采用的先进行一次构图工艺处理得到多晶硅有源层图案,然后进行一次构图工艺处理得到源、漏极与有源层的连接部分层,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,从而降低了工序复杂度,在缩短了加工时间的同时降低了加工成本。 Compared with the prior art, using a first patterning process is performed to obtain a polysilicon active layer pattern, followed by a patterning process to obtain a source, a drain layer and the active layer of the connecting portion, and then a patterning process to obtain the source, a drain, the process reduces the exposure process, thereby reducing the complexity of the process, shortening the processing time while reducing processing costs. [0083] S405、在源极、漏极和多晶硅半导体部分的图案上形成栅绝缘层,之后进行沟道区掺杂处理,以便与源、漏极形成沟道区。 [0083] S405, electrode, the drain electrode is formed on the gate insulating layer and a patterned polysilicon semiconductor in the source, channel region is doped After treatment, the source to drain channel region is formed.

[0084] 如图5L所示,在源极541和漏极层542上,采用PECVD法沉积栅绝缘层56,然后通过自对准工艺(Self Align)方法,采用离子浴或者离子注入的方式,进行沟道区531的掺杂处理,以便使沟道区531与源极、漏极区域形成PN结,使TFT构成MOS开关结构。 [0084] As shown in FIG 5L, 541 on the source and drain layer 542, is deposited using the PECVD method gate insulating layer 56, and then by self-alignment process (Self Align) method using ion implantation or ion bath manner, for the channel doping process 531, so that the channel region 531 and the source and drain regions form a PN junction, constituting the TFT switch MOS structure.

[0085] S406、在栅绝缘层上形成栅线、栅极。 [0085] S406, forming a gate line, a gate electrode on the gate insulating layer.

[0086] 如图5M所示,在栅绝缘层56之上,采用溅射工艺形成栅极的第二金属层,然后通过第二次构图工艺处理,形成栅线(图中未表示)、栅极57。 [0086] As shown in FIG. 5M, over the gate insulating layer 56, a sputtering process to form the gate of the second metal layer, and then through the second patterning process, to form a gate line (not shown), the gate pole 57.

[0087] S407、在栅线、栅极上形成保护层(PVX)。 [0087] S407, the gate line, forming a protective layer (PVX) on the gate.

[0088] 如图5N所示,在栅极57上,采用PECVD法沉积一层保护层58,来保护栅极。 [0088] As shown in FIG. 5N, on the gate 57, by a PECVD deposited a protective layer 58 to protect the gate.

[0089] S408、在栅绝缘层和保护层上形成连接过孔。 [0089] S408, is formed on the gate insulating layer and the protective layer connecting vias.

[0090] 如图50所示,通过第三次构图工艺处理,在栅绝缘层56和保护层58上形成一个贯穿栅绝缘层56和保护层58的连接过孔59',露出漏极542,用于使漏极和和像素电极相连接。 [0090] shown in Figure 50, through a third patterning process, is formed on the gate insulating layer 56 and the protective layer 58 through a gate insulating layer 56 and the protective layer 58 is connected through holes 59 ', the drain electrode 542 is exposed, and for the drain and the pixel electrode is connected.

[0091 ] S409、在保护层上形成像素电极层,像素电极层通过过孔与漏极连接。 [0091] S409, the pixel electrode layer is formed on the protective layer, a pixel electrode layer and a drain connected through the via hole.

[0092] 如图5P所示,采用PECVD法在保护层58上沉积一层ITO (Indium Tin Oxide,铟锡氧化物半导体),然后采用第四次构图工艺处理,得到像素电极59,像素电极59通过连接过孔59'与漏极542相连接。 59, the pixel electrode 59 [0092] As shown in FIG 5P, deposited by a PECVD layer of ITO (Indium Tin Oxide, Indium Tin Oxide Semiconductor) on the protective layer 58, and a patterning process using the fourth, the pixel electrode to give 'connected with the drain 542 through the connection through-hole 59.

[0093] S410、在像素电极上形成平坦化层。 [0093] S410, the planarization layer is formed on the pixel electrode.

[0094] 如图5Q所示,在像素电极59上沉积一层起到平坦化和保护ITO像素电极边缘的保护层90,可以采用合成树脂(Resin)或绝缘层等材料,然后采用第五次构图工艺来形成相应图形。 [0094] As shown in FIG. 5Q, the pixel electrode 59 is deposited on the protective layer functions as a planarizing layer 90 and the pixel electrode edge protection ITO, a synthetic resin material (Resin) or the insulating layer or the like may be employed, then use of the fifth patterning process to form the corresponding pattern.

[0095] 本发明实施例提供的低温多晶硅TFT阵列基板的制造方法,在基板上形成缓冲层、涂布多晶硅层和金属层之后,通过GTM对金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到包括数据线、源极、漏极、多晶硅半导体部分的图案。 [0095] The low an embodiment of the present invention is a method for producing polycrystalline silicon TFT array substrate, forming a buffer layer on a substrate, a polysilicon layer and after coating the metal layer, a metal layer patterning process, the polysilicon layer by GTM, through one patterning process results including a data line, a source, a drain, polysilicon semiconductor pattern. 较现有技术中先进行一次构图工艺处理得到多晶硅有源层图案,接着进行一次构图工艺处理得到源漏极与有源层的连接部分,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,减少了一层保护层,从而降低了工序复杂度,节省了材料,在缩短了加工时间的同时降低了加工成本。 Compared to the prior art, a patterning process is performed to obtain a polysilicon active layer pattern, followed by a connecting portion patterning process to obtain the source and drain of the active layer, and then patterning process to obtain a source, a drain, the process for reducing the exposure, a protective layer is reduced, thereby reducing the complexity of the process, the material is saved in reducing the processing time while reducing processing costs.

[0096] 实施例二 [0096] Second Embodiment

[0097] 本发明实施例二提供的低温多晶硅TFT阵列基板的制造方法,以利用半透式掩模板(HTM)制造低温多晶硅TFT阵列基板为例进行说明。 The method of manufacturing a low-temperature polysilicon TFT array substrate according to a second embodiment [0097] of the present invention, the semipermeable mask formula (HTM) for producing a low temperature poly-silicon TFT array substrate will be described as an example.

[0098] 首先,参照图3b对HTM工艺的主要原理进行说明。 [0098] First, referring to FIG. 3b HTM main principle of the process will be described. HTM掩膜板是通过在不同区域透过光的强度不同,而使光刻胶进行选择性曝光、显影。 HTM plate is intensity of light transmitted through different in different regions, the photoresist is selectively exposed and developed. 图3b表示利用HTM掩膜板31对光刻胶进行曝光处理的过程。 Figure 3b shows the use of the HTM plate 31 during the photoresist exposure process. 在HTM掩膜板31中,包括透明区域311、不透明区域312和半透明区域313。 In HTM plate 31, it comprises a transparent region 311, the opaque region 312 and the semi-transparent region 313. 光刻胶32为曝光后的状态,其中,区域321对应HTM掩膜板31的透明区域311,区域322对应HTM掩膜板31的不透明区域312,区域323对应HTM掩膜板31的半透明区域313。 The photoresist 32 is exposed state, wherein the region 321 corresponding to the HTM mask transparent region 311, region 322 corresponding to the opaque regions 31 of the mask 31 HTM 312, region 323 corresponding to the translucent area of ​​the HTM plate 31 313. 光刻胶33为显影后的状态,其中,区域331对应HTM掩膜板31的透明区域311,区域332对应HTM掩膜板31的不透明区域312,区域333对应HTM掩膜板31的半透明区域313。 The photoresist 33 after development state, wherein the region 331 corresponding to the HTM mask transparent region 311, region 332 corresponding to the opaque region 31 of the plate 31 of the HTM 312, region 333 corresponding to the HTM plate 31 translucent area 313.

[0099] 如图6所示,本实施例二与实施例一相比,除使用HTM进行构图工艺的步骤(S604)与实施例一使用GTM进行构图工艺的步骤(S604)有所不同之外,其余步骤与实施例一完全相同。 [0099] shown in Figure 6, the present embodiment as compared with the outside twenty-one embodiment, the step (S604) a patterning process using GTM addition step (S604) for using HTM patterning process different from Example Embodiment the rest is the same as the first embodiment.

[0100]包括: [0100] comprising:

[0101] S601、在基板上形成缓冲层。 [0101] S601, forming a buffer layer on the substrate.

[0102] S602、在缓冲层上形成多晶硅层。 [0102] S602, a polysilicon layer is formed on the buffer layer.

[0103] S603、在多晶娃有源层上形成源、漏极所用的第一金属层。 [0103] S603, the source is formed on the polycrystalline baby active layer, a first metal layer used for the drain.

[0104] S604、利用半透式掩模板,对第一金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到数据线、源极、漏极和多晶硅半导体部分图案。 [0104] S604, using the transflective mask, the first metal layer, a polysilicon layer patterning process is performed to obtain the data lines through one patterning process, the source, drain and polysilicon semiconductor pattern.

[0105] 如图5E所不(由于与实施例一的图5E相同,参照实施例一的相关附图即可),在上述结构的基板上涂覆一层光刻胶55,之后用HTM工艺对光刻胶55进行曝光处理。 [0105] FIG. 5E do not (the same as those of the first embodiment in FIG. 5E, an embodiment with reference to the accompanying drawings related to embodiments), a layer of photoresist 55 is coated on the substrate in the above-described structure, the process followed by HTM 55 photoresist exposure process. 该HTM掩膜板80上针对TFT区域,对应源极、漏极区域的部分为不透明区域802,对应栅极区域的部分为半透明区域803。 The HTM mask for the TFT region 80, corresponding to the source electrode, the drain region portion is opaque region 802, a portion corresponding to the gate region is semi-transparent region 803.

[0106] 如图5F所不(由于与实施例一的图5F相同,参见实施例一的相关附图即可),为上述曝光后的光刻胶55的状态示意图,其中,光刻胶55的区域551对应HTM掩膜板80的不透明区域802,光刻胶55的区域552对应HTM掩膜板80的半透明区域803。 [0106] FIG. 5F are not (due to the same embodiment of a FIG. 5F, a related embodiment Referring to the drawings embodiments), a schematic view of a state after the exposure of the photoresist 55, wherein the photoresist 55 the region 551 corresponding to the HTM plate 80 of the opaque region 802, region 552 of the photoresist 55 corresponding to the HTM translucent area 803 of the plate 80.

[0107] 如图5G所不(由于与实施例一的图5G相同,参照实施例一的相关附图即可),为显影后的光刻胶55的状态示意图,其中,光刻胶55的区域551为光刻胶完全保留区域,光刻胶55的区域552为光刻胶半保留区域,其他区域为光刻胶完全去除区域。 [0107] FIG. 5G do not (the same as those of the first embodiment in FIG. 5G, an embodiment with reference to the accompanying drawings related to embodiments), a schematic view of a state of a developed resist 55, wherein the photoresist 55 regional photoresist completely retained region 551, the photoresist region 55255 is photoresist half-retained region, other regions as photoresist completely removed region.

[0108] 然后,如图5H所不(由于与实施例一的图5H相同,参照实施例一的相关附图即可),采用湿法刻蚀(Wet Etch)工艺对光刻胶完全去除区域的源漏极金属层进行刻蚀,然后采用干法刻蚀(Dry Etch)工艺对多晶硅层进行刻蚀,得到多晶硅有源层53。 [0108] Then, as shown in FIG 5H is not (FIG. Because a same as in Example 5H, an embodiment with reference to the related drawings embodiments), wet etching (Wet Etch) region in the photoresist is completely removed the source drain metal layer is etched, and then dry etching (dry etch) process on the polycrystalline silicon layer is etched to obtain the polysilicon active layer 53.

[0109] 然后,如图51所不(由于与实施例一的图51相同,参照实施例一的相关附图即可),经等离子体灰化处理,将光刻胶55的光刻胶半保留区域552的光刻胶刻蚀掉,余下光刻胶完全保留区域551的光刻胶,该光刻胶完全保留区域551对应源极、漏极区域。 [0109] Then, as does (since the same one as in Example 51, an embodiment with reference to the accompanying drawings related to embodiments) 51, the plasma ashing process, the photoresist 55 of photoresist half reserved area 552 is etched off the photoresist, the remaining photoresist completely-retained regions of the photoresist 551, the photoresist completely retained and drain regions 551 corresponding to the source region.

[0110] 然后,如图5J所不(由于与实施例一的图5J相同,参照实施例一的相关附图即可),再经过湿法刻蚀工艺对光刻胶半保留区域552的源漏极金属层进行二次刻蚀。 [0110] Then, as shown in FIG 5J are not (FIG. Because a same as in Example 5J, an embodiment with reference to the accompanying drawings related to embodiments), and then through a wet etching process of the source region 552 of the photoresist half-retained secondary drain metal layer is etched.

[0111] 最后,如图5K所不(由于与实施例一的图5K相同,参照实施例一的相关附图即可),剥离掉光刻胶完全保留区域551的光刻胶之后,得到源极、漏极54。 After [0111] Finally, FIG. 5K are not (since a 5K same embodiment of FIG embodiment, an embodiment with reference to the accompanying drawings related to embodiments), the photoresist is peeled off completely-retained regions of the photoresist 551, the source to obtain electrode, the drain electrode 54.

[0112] 至此,本实施例中,通过一次HTM构图工艺处理,得到了包括数据线、源极、漏极、多晶硅有源层的图案。 [0112] Thus, in the present embodiment, by one HTM patterning process, including data obtained line, the source electrode, the drain electrode, the active layer of polysilicon pattern. 较现有技术中,采用的先进行一次构图工艺处理得到多晶硅有源层图案,然后进行一次构图工艺处理得到源、漏极与有源层的连接部分层,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,从而降低了工序复杂度,在缩短了加工时间的同时降低了加工成本。 Compared with the prior art, using a first patterning process is performed to obtain a polysilicon active layer pattern, followed by a patterning process to obtain a source, a drain layer and the active layer of the connecting portion, and then a patterning process to obtain the source, a drain, the process reduces the exposure process, thereby reducing the complexity of the process, shortening the processing time while reducing processing costs.

[0113] S605、在源极、漏极和多晶硅半导体部分的图案上形成栅绝缘层,之后进行沟道区掺杂处理,以便与源、漏极形成沟道区。 [0113] S605, electrode, the drain electrode is formed on the gate insulating layer and a patterned polysilicon semiconductor in the source, channel region is doped After treatment, the source to drain channel region is formed.

[0114] S606、在栅绝缘层上形成栅线、栅极。 [0114] S606, forming a gate line, a gate electrode on the gate insulating layer.

[0115] S607、在栅极上形成保护层(PVX)。 [0115] S607, forming a protective layer (PVX) on the gate. [0116] S608、在栅绝缘层和保护层上形成连接过孔。 [0116] S608, is formed on the gate insulating layer and the protective layer connecting vias.

[0117] S609、在连接过孔上形成ITO像素电极。 [0117] S609, the pixel electrode ITO is formed on the connecting vias.

[0118] S610、在像素电极上形成平坦化层。 [0118] S610, the planarization layer is formed on the pixel electrode.

[0119] 本发明实施例提供的低温多晶硅TFT阵列基板的制造方法,在基板上形成缓冲层、涂布多晶硅层和金属层之后,通过HTM对金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到包括数据线、源极、漏极、多晶硅半导体部分的图案。 [0119] The low an embodiment of the present invention is a method for producing polycrystalline silicon TFT array substrate, forming a buffer layer on a substrate, a polysilicon layer and after coating the metal layer, a metal layer patterning process, the polysilicon layer by HTM, through one patterning process results including a data line, a source, a drain, polysilicon semiconductor pattern. 较现有技术中先进行一次构图工艺处理得到多晶硅有源层图案,接着进行一次构图工艺处理得到源漏极与有源层的连接部分,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,减少了一层保护层,从而降低了工序复杂度,节省了材料,在缩短了加工时间的同时降低了加工成本。 Compared to the prior art, a patterning process is performed to obtain a polysilicon active layer pattern, followed by a connecting portion patterning process to obtain the source and drain of the active layer, and then patterning process to obtain a source, a drain, the process for reducing the exposure, a protective layer is reduced, thereby reducing the complexity of the process, the material is saved in reducing the processing time while reducing processing costs.

[0120] 实施例三 [0120] Example three

[0121] 本发明实施例提供的低温多晶硅TFT阵列基板,如图5Q所示,包括: [0121] an embodiment of the low-temperature polysilicon TFT array substrate of the present invention, as shown in FIG. 5Q, comprising:

[0122]基板 51; [0122] substrate 51;

[0123] 基板51上形成有缓冲层52 ; It is formed on the [0123] substrate 51 with a buffer layer 52;

[0124] 缓冲层52上形成有多晶硅半导体有源层53 ; [0124] The buffer layer 52 is formed on the polycrystalline silicon active semiconductor layer 53;

[0125] 多晶硅半导体有源层53上形成有源极541、漏极542 ;源极541、漏极542与多晶硅半导体有源层53构成TFT区域; Is formed [0125] The semiconductor active layer 53 of polysilicon active electrode 541, a drain 542; source electrode 541, drain electrode 542 and the semiconductor active layer 53 composed of a polysilicon TFT region;

[0126] 源极541、漏极542上形成有栅绝缘层56 ; [0126] The source 541, gate insulating layer 56 is formed on the drain 542;

[0127] 栅绝缘层56上形成有栅极57、栅线(图中未表示); [0127] 56 is formed on the gate insulating layer, a gate 57, a gate line (not shown);

[0128] 栅极57、栅线上形成有保护层58 ; [0128] gate electrode 57, the gate line 58 is formed with a protective layer;

[0129] 保护层58上形成有像素电极层59,像素电极层59通过位于保护层58、栅绝缘层56上的过孔59'与漏极542连接。 [0129] A pixel electrode layer 59 is formed, the pixel electrode layer 59 through the protective layer 58, a gate insulating layer on the via hole 5659 'is connected to the drain electrode 542 on the protective layer 58.

[0130] 本发明实施例提供的低温多晶硅TFT阵列基板,在基板上形成缓冲层、涂布多晶硅层和金属层之后,通过HTM或GTM对金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到包括数据线、源极、漏极、多晶硅半导体部分的图案。 [0130] LTPS TFT array substrate according to an embodiment of the present invention, forming a buffer layer on a substrate, a polysilicon layer and after coating the metal layer, a metal layer patterning process, the polysilicon layer by HTM or GTM, through one patterning process obtained including a data line, a source, a drain, polysilicon semiconductor pattern. 较现有技术中先进行一次构图工艺处理得到多晶硅有源层图案,接着进行一次构图工艺处理得到源漏极与有源层的连接部分,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,减少了一层保护层,从而降低了工序复杂度,节省了材料,在缩短了加工时间的同时降低了加工成本。 Compared to the prior art, a patterning process is performed to obtain a polysilicon active layer pattern, followed by a connecting portion patterning process to obtain the source and drain of the active layer, and then patterning process to obtain a source, a drain, the process for reducing the exposure, a protective layer is reduced, thereby reducing the complexity of the process, the material is saved in reducing the processing time while reducing processing costs.

[0131] 实施例四 [0131] Fourth Embodiment

[0132] 本发明实施例提供的低温多晶硅TFT阵列基板的制造方法,如图7所示,包括: [0132] The low according to an embodiment of the present invention is a method for producing polycrystalline silicon TFT array substrate shown in Figure 7, comprising:

[0133] S701、在基板上形成缓冲层。 [0133] S701, forming a buffer layer on the substrate.

[0134] S702、在缓冲层上形成多晶硅层。 [0134] S702, a polysilicon layer is formed on the buffer layer.

[0135] S703、在多晶硅层进行低浓度掺杂。 [0135] S703, the low-doped polysilicon layer.

[0136] 多晶硅层形成后,对多晶硅层进行低浓度掺杂,掺杂类型与将要进行的沟道区掺杂类型相反,以便在沟道掺杂处理后在源、漏极与沟道间形成反向PN结,这样可以降低在源漏极处多晶硅层和源漏极间的接触电阻。 After [0136] forming a polysilicon layer, the polysilicon layer is doped with a low concentration, the doping type of the channel region to be subjected to a doping type opposite to the post-processing is formed in the channel doping between the source, drain and channel reverse PN junction, which can reduce the contact resistance between the source and drain of the polysilicon layer and the source and drain.

[0137] S704、在多晶娃有源层上形成源、漏极所用的第一金属层。 [0137] S704, a first metal layer forming the source, drain used in the active layer on the polycrystalline baby.

[0138] S705、利用灰色掩模板或半透式掩模板,对第一金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到数据线、源极、漏极和多晶硅半导体部分图案。 [0138] S705, the gray mask or transflective mask, the first metal layer, a polysilicon layer patterning process is performed to obtain the data lines through one patterning process, the source, drain and polysilicon semiconductor pattern. [0139] 本实施例除以上步骤外,其余步骤与实施例一或实施例二完全一样,具体可参考实施例一或实施例二。 [0139] In addition to the present embodiment, the above steps, the remaining steps of the first embodiment or the second embodiment exactly the same, a specific reference to the embodiment or the second embodiment.

[0140] 本发明实施例提供的低温多晶硅TFT阵列基板,在基板上形成缓冲层、涂布多晶硅层和金属层之后,通过HTM或GTM对金属层、多晶硅层进行构图工艺处理,通过一次构图工艺得到包括数据线、源极、漏极、多晶硅半导体部分的图案。 [0140] LTPS TFT array substrate according to an embodiment of the present invention, forming a buffer layer on a substrate, a polysilicon layer and after coating the metal layer, a metal layer patterning process, the polysilicon layer by HTM or GTM, through one patterning process obtained including a data line, a source, a drain, polysilicon semiconductor pattern. 较现有技术中先进行一次构图工艺处理得到多晶硅有源层图案,接着进行一次构图工艺处理得到源漏极与有源层的连接部分,再进行一次构图工艺处理得到源、漏极而言,减少了曝光的工艺处理,减少了一层保护层,从而降低了工序复杂度,节省了材料,在缩短了加工时间的同时降低了加工成本。 Compared to the prior art, a patterning process is performed to obtain a polysilicon active layer pattern, followed by a connecting portion patterning process to obtain the source and drain of the active layer, and then patterning process to obtain a source, a drain, the process for reducing the exposure, a protective layer is reduced, thereby reducing the complexity of the process, the material is saved in reducing the processing time while reducing processing costs.

[0141] 以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。 [0141] The above are only specific embodiments of the present invention, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the technical scope of the present invention is disclosed, variations may readily occur to or alternatively, shall fall within the protection scope of the present invention. 因此,本发明的保护范围应以所述权利要求的保护范围为准。 Accordingly, the scope of the present invention should be defined by the scope of the claims.

Claims (5)

1. ー种低温多晶硅TFT阵列基板,其特征在于,包括: 基板; 形成有多晶硅半导体有源层; 所述多晶硅半导体有源层上形成有源极、漏扱;所述源极、漏极与所述多晶硅半导体有源层构成TFT区域; 所述源极、漏极上形成有栅绝缘层; 所述栅绝缘层上形成有栅极、栅线; 所述栅极、栅线上形成有保护层; 所述保护层上形成有像素电极层,所述像素电极层通过位于所述保护层、栅绝缘层上的过孔与所述漏极连接。 1. ー species LTPS TFT array substrate comprising: a substrate; forming a polysilicon semiconductor active layer; forming an active layer on the polycrystalline silicon active semiconductor electrode, a drain Cha; the source, drain and the polysilicon layer constituting the TFT active semiconductor region; the source electrode, gate insulating layer is formed on the drain; forming a gate, a gate insulating layer on the gate line; the gate electrode, gate line are formed with a protective layer; the protective layer is formed on a pixel electrode layer, the pixel electrode layer on the protective layer, the vias on the gate insulating layer and connected to the drain.
2.根据权利要求4所述的低温多晶硅TFT阵列基板,其特征在于,还包括: 在形成有多晶硅半导体有源层之前,在所述基板上形成有缓冲层。 2. The low-temperature polysilicon TFT array substrate according to claim 4, characterized in that, further comprising: prior to forming polysilicon active semiconductor layer formed on the substrate with a buffer layer.
3. —种低温多晶硅TFT阵列基板的制造方法,其特征在于,包括: 在基板上形成多晶硅层; 在所述多晶硅层上形成第一金属层,利用灰色调掩摸板或半透式掩摸板对所述第一金属层、多晶硅层进行构图エ艺处理,通过第一次构图エ艺得到数据线、源极、漏极和多晶硅半导体部分的图案; 通过第二次构图エ艺在所述栅绝缘层上形成栅线、栅极; 在所述源极、漏极和多晶硅半导体部分的图案上形成栅绝缘层; 对所述多晶硅层的源、漏极之间的部分进行掺杂处理,以便与所述源、漏极形成沟道区; 在所述栅线、栅极上形成保护层,通过第三次构图エ艺在所述漏极处形成过孔,露出所述漏极; 在所述保护层上形成像素电极层,所述像素电极层通过所述过孔与所述漏极连接; 通过第四次构图エ艺形成像素电极图形; 在像素电极上通过第五次构图エ艺形成 3. The - method of manufacturing a low-temperature polysilicon TFT array substrate, comprising: forming a polysilicon layer on a substrate; forming a first metal layer on said polysilicon layer, using a gray-tone mask or a transflective masking formwork plate of said first metal layer, a polysilicon layer is patterned Ester processing arts, by patterning the first data line to give Ester arts, the source, drain and polysilicon semiconductor pattern; the second patterning in the arts Ester forming a gate insulating layer on the gate line, a gate; forming a gate insulating layer on the source, drain, and polysilicon semiconductor pattern; on the portion between the source and the drain doped polysilicon layer process, to the source, drain channel region is formed; forming a protective layer on the gate line, a gate, through holes are formed by the drain of the third patterning Ester arts, exposing the drain electrode; in the pixel electrode layer is formed on the protective layer, the pixel electrode layer through the via hole is connected to the drain; pixel electrode pattern is formed by patterning the fourth Ester arts; on the pixel electrode by patterning the fifth Ester Art form 坦化层图形。 Graphical layer of Tanzania.
4.根据权利要求3所述的低温多晶硅TFT阵列基板的制造方法,其特征在于,所述利用灰色调掩摸板或半透式掩摸板对所述第一金属层进行构图エ艺处理,通过一次构图エ艺得到数据线、源极、漏极和多晶硅半导体部分的图案,包括: 在所述第一金属层上涂布光刻胶; 利用灰色调掩摸板或半透式掩摸板对所述光刻胶进行曝光,显影后形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域;其中,所述光刻胶完全保留区域对应数据线区域、源极区域、漏极区域,所述光刻胶半保留区域对应源、漏极区域之间的区域; 利用刻蚀エ艺去除掉所述光刻胶完全去除区域的第一金属层、多晶硅层; 利用等离子体灰化工艺去除掉所述光刻胶半保留区域的光刻胶; 利用刻蚀エ艺去除掉所述光刻胶半保留区域的第一金属层; 剥离掉所述光刻胶完全保留区 The method for producing a low temperature polysilicon TFT array substrate according to claim 3, wherein the first metal layer is patterned using the process Ester arts formwork gray-tone mask or a transflective cover formwork, Ester Yi obtained through one patterning the data line, the source, drain and polysilicon semiconductor pattern, comprising: applying a photoresist on the first metal layer; using a gray-tone mask or a transflective mask formwork formwork exposing the photoresist to form a photoresist completely-retained region, photoresist half-retained region and a photoresist is completely removed after development region; wherein the photoresist region corresponding to the completely-retained region data line, a source region, a drain region, the photoresist corresponding to the source region, the drain region of the semiconductor region between the reserved; Ester arts removed by etching completely removing the photoresist layer, a first metal region, a polysilicon layer; using plasma ashing process to remove the photoresist in the photoresist half-retained region; Ester arts removed by etching the first metal layer is photoresist half of the reserved area; peeling off the photoresist completely-retained Area 的光刻胶。 Photoresist.
5.根据权利要求3所述的低温多晶硅TFT阵列基板的制造方法,其特征在于,所述在基板上形成多晶硅层包括:在基板上形成缓冲层,在所述缓冲层上形成多晶硅层。 The method for producing a low temperature polysilicon TFT array substrate according to claim 3, wherein said polysilicon layer is formed on a substrate comprising: forming a buffer layer on a substrate, forming a polysilicon layer on the buffer layer.
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856260A (en) * 2012-09-26 2013-01-02 京东方科技集团股份有限公司 CMOS (complementary metal-oxide-semiconductor transistor) transistor and manufacture method thereof
CN103022145A (en) * 2012-10-31 2013-04-03 京东方科技集团股份有限公司 Array substrate, display device and preparation method
CN103715207A (en) * 2013-12-31 2014-04-09 合肥京东方光电科技有限公司 Capacitor of TFT array substrate and manufacturing method and relevant device thereof
WO2014127575A1 (en) * 2013-02-20 2014-08-28 京东方科技集团股份有限公司 Method for manufacturing array substrate
WO2015180320A1 (en) * 2014-05-27 2015-12-03 京东方科技集团股份有限公司 Array substrate, manufacturing method therefor, display device, thin film transistor and manufacturing method therefor
WO2015180310A1 (en) * 2014-05-27 2015-12-03 京东方科技集团股份有限公司 Array substrate, manufacturing method therefor, display device, thin film transistor and manufacturing method therefor
WO2015180450A1 (en) * 2014-05-27 2015-12-03 京东方科技集团股份有限公司 Low-temperature poly-silicon thin film transistor and preparation method therefor, and display device
CN105428243A (en) * 2016-01-11 2016-03-23 京东方科技集团股份有限公司 Thin film transistor and manufacturing method thereof, array substrate and display apparatus
WO2016045254A1 (en) * 2014-09-23 2016-03-31 京东方科技集团股份有限公司 Method for manufacturing low-temperature polycrystalline silicon thin film, low-temperature polycrystalline silicon thin film and device using same
WO2016090689A1 (en) * 2014-12-12 2016-06-16 深圳市华星光电技术有限公司 Doping method and manufacturing equipment for array substrate
WO2016112564A1 (en) * 2015-01-13 2016-07-21 深圳市华星光电技术有限公司 Array substrate fabrication method, array substrate, and display panel
CN106158882A (en) * 2016-09-27 2016-11-23 厦门天马微电子有限公司 A kind of display device, display floater, array base palte and preparation method thereof
CN104078424B (en) * 2014-06-30 2017-02-15 京东方科技集团股份有限公司 Low-temperature poly-silicon TFT array substrate, manufacturing method thereof and display device
WO2018176829A1 (en) * 2017-03-29 2018-10-04 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
WO2018188152A1 (en) * 2017-04-14 2018-10-18 深圳市华星光电半导体显示技术有限公司 Method for manufacturing tft array substrate
US10546885B2 (en) 2017-03-29 2020-01-28 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030180990A1 (en) * 2001-12-29 2003-09-25 Hyun-Sik Seo Method of fabricating polysilicon thin film transistor
CN1536620A (en) * 2003-04-09 2004-10-13 友达光电股份有限公司 Low-temp. polycrystalline silicon film transistor and its polycrystalline silicon layer making method
CN101630098A (en) * 2008-07-18 2010-01-20 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030180990A1 (en) * 2001-12-29 2003-09-25 Hyun-Sik Seo Method of fabricating polysilicon thin film transistor
CN1536620A (en) * 2003-04-09 2004-10-13 友达光电股份有限公司 Low-temp. polycrystalline silicon film transistor and its polycrystalline silicon layer making method
CN101630098A (en) * 2008-07-18 2010-01-20 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US9252278B2 (en) 2012-10-31 2016-02-02 Boe Technology Group Co., Ltd. Array substrate, display device and manufacturing method thereof
CN103022145B (en) * 2012-10-31 2016-11-16 京东方科技集团股份有限公司 Array base palte, display device and preparation method
WO2014127575A1 (en) * 2013-02-20 2014-08-28 京东方科技集团股份有限公司 Method for manufacturing array substrate
US9634044B2 (en) 2013-02-20 2017-04-25 Boe Technology Group Co., Ltd. Method for fabricating array substrate
CN103715207B (en) * 2013-12-31 2017-11-10 合肥京东方光电科技有限公司 The electric capacity and its manufacture method and relevant device of tft array substrate
US9252166B2 (en) 2013-12-31 2016-02-02 Boe Technology Group Co., Ltd. Capacitor for TFT array substrate and method of manufacturing the same, and devices associated with the same
CN103715207A (en) * 2013-12-31 2014-04-09 合肥京东方光电科技有限公司 Capacitor of TFT array substrate and manufacturing method and relevant device thereof
WO2015180320A1 (en) * 2014-05-27 2015-12-03 京东方科技集团股份有限公司 Array substrate, manufacturing method therefor, display device, thin film transistor and manufacturing method therefor
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US9818775B2 (en) 2014-05-27 2017-11-14 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof
WO2015180310A1 (en) * 2014-05-27 2015-12-03 京东方科技集团股份有限公司 Array substrate, manufacturing method therefor, display device, thin film transistor and manufacturing method therefor
US9634043B2 (en) 2014-05-27 2017-04-25 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof
US9478562B2 (en) 2014-05-27 2016-10-25 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display device, thin film transistor and manufacturing method thereof
US9947697B2 (en) 2014-06-30 2018-04-17 Boe Technology Group Co., Ltd. Low temperature polycrystalline silicon TFT array substrate and method of producing the same, display apparatus
CN104078424B (en) * 2014-06-30 2017-02-15 京东方科技集团股份有限公司 Low-temperature poly-silicon TFT array substrate, manufacturing method thereof and display device
WO2016045254A1 (en) * 2014-09-23 2016-03-31 京东方科技集团股份有限公司 Method for manufacturing low-temperature polycrystalline silicon thin film, low-temperature polycrystalline silicon thin film and device using same
WO2016090689A1 (en) * 2014-12-12 2016-06-16 深圳市华星光电技术有限公司 Doping method and manufacturing equipment for array substrate
WO2016112564A1 (en) * 2015-01-13 2016-07-21 深圳市华星光电技术有限公司 Array substrate fabrication method, array substrate, and display panel
CN105428243A (en) * 2016-01-11 2016-03-23 京东方科技集团股份有限公司 Thin film transistor and manufacturing method thereof, array substrate and display apparatus
US10355022B2 (en) 2016-01-11 2019-07-16 Boe Technology Group Co., Ltd. Thin film transistor, method for fabricating the same, array substrate, and display device
CN106158882A (en) * 2016-09-27 2016-11-23 厦门天马微电子有限公司 A kind of display device, display floater, array base palte and preparation method thereof
CN106158882B (en) * 2016-09-27 2019-02-26 厦门天马微电子有限公司 A kind of display device, display panel, array substrate and preparation method thereof
WO2018176829A1 (en) * 2017-03-29 2018-10-04 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
CN108666218A (en) * 2017-03-29 2018-10-16 京东方科技集团股份有限公司 Thin film transistor (TFT) and display base plate and preparation method thereof, display device
US20190067340A1 (en) * 2017-03-29 2019-02-28 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
US10546885B2 (en) 2017-03-29 2020-01-28 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
WO2018188152A1 (en) * 2017-04-14 2018-10-18 深圳市华星光电半导体显示技术有限公司 Method for manufacturing tft array substrate

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