CN101127357B - Passivation layer structure, thin film transistor part and manufacturing method of passivation layer - Google Patents
Passivation layer structure, thin film transistor part and manufacturing method of passivation layer Download PDFInfo
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- CN101127357B CN101127357B CN2006101098657A CN200610109865A CN101127357B CN 101127357 B CN101127357 B CN 101127357B CN 2006101098657 A CN2006101098657 A CN 2006101098657A CN 200610109865 A CN200610109865 A CN 200610109865A CN 101127357 B CN101127357 B CN 101127357B
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Abstract
The utility model discloses a passivation layer structure, which comprises an underlayer insulating film and a top layer passivating film; wherein, the underlayer insulating film is covered by the top layer passivating film, the underlayer insulating film of the passivation layer is made of silicon oxynitride; the top layer passivating film of the passivation layer is made of silicon nitride (Si3N4), and the underlayer insulating film is thicker than the top layer passivating film; a through hole is arranged at the corresponding positions of the underlayer insulating film and the top layer passivating film, the size of the through hole of the underlayer insulating film is larger than that of the top layer passivating film; the underlayer insulating film is fully covered by the top layer passivating film in the lateral face of the through hole. The utility model discloses the manufacture method of thin film transistor (TFT) device adopting passivation layer structure and passivation layer simultaneously. The utility model has the advantages of optimizing the manufacture process of thin film transistor (TFT) and other display device passivation layer, thus raising the percent of pass, and effectively cutting down on the costs.
Description
Technical field
The present invention relates to passivation layer structure, film transistor device and manufacturing method of passivation layer, relate in particular to multilayer passivation layer structure, have the film transistor device of this structure and the manufacturing method of passivation layer of this structure.
Background technology
In Thin Film Transistor-LCD (TFT LCD) device, the film of passivation layer is utilized to protect the electronic device under it, prevents that they are subjected to the pollution of moisture moisture and impurity, and causes the physical property of device and electric property destroyed.Another effect of passivation layer is blocking-up pixel electrode and source-drain electrode, prevents to be short-circuited between them.The 3rd effect of passivation layer be, as the dielectric of storage capacitance, keeps the operating voltage of pixel region when being in off-state at thin-film transistor (TFT).Usually passivation layer is to be made of silicon nitride or silicon oxide film, and these materials can stop moving iron to enter device inside effectively and cause variations in threshold voltage.Silicon nitride film shows the superior performance of ratio silicon oxide film aspect prevention moisture and moving iron, and is extensively selected use in semiconductor device and TFT LCD.
Be a kind of TFT device architecture commonly used at present as shown in Figure 1.This device is made of substrate 1, gate electrode 2, gate insulator 3, active layer 4, source electrode 6, drain electrode 7 and passivation layer 8, and wherein source electrode 6 is connected with data wire, and drain electrode 7 is connected with pixel electrode 10 at passivation layer via hole 9 places.Its passivation layer 8 is made of one deck silicon nitride film (SiNx:H), generally is that the temperature about 300 ℃ is formed on the metal electrode by the method for plasma gas phase assistant depositing (PECVD).United States Patent (USP) 5455182,5656826,6462403 use the passivation layer of one deck silicon nitride film as TFT, the channel part and the metal electrode of protection TFT device.United States Patent (USP) 6869838 more proposes a kind of PECVD equipment and film plating process, deposits the passivation layer of the siliceous film of one deck as TFT.In above-mentioned device architecture, because density of film difference and thermal coefficient of expansion difference can produce bigger stress between silicon nitride and the metal.Now the glass substrate size of TFT LCD becomes increasing, and membrane stress can cause the fragment or the distortion of glass, and makes especially photoetching and take place bad to box of subsequent technique.In addition, silicon nitride film forms storage capacitance between pixel electrode and grid metallic film.Silicon nitride below the pixel electrode can reflect seeing through the visible light of pixel, refraction and absorption, causes the decline of transmitance and weakening of TFT LCD brightness.
At semiconductor device such as memory chip etc., the passivation layer that uses plural layers to constitute discharges stress.United States Patent (USP) 5549786,6261944,6656778 all propose the passivation layer of multi-layer film structure.They all use a kind of macromolecular material (Spin-On-Glass:SOG), as the interlayer between the inorganic insulation medium, as silicon nitride or silica.The passivation layer that these patents propose has comprised three to five layer films, causes manufacturing process to become complicated, and cost increases greatly.Because the macromolecular material that uses has stronger absorption for visible light, be unsuitable for using in TFT LCD device simultaneously.
United States Patent (USP) 6057890,6597415,6940566 also use the passivation layer of a kind of organic insulating material as TFT.This kind organic material has flowability, can reduce membrane stress and bad to box technology, improves the uniformity of substrate surface.But the resistance to elevated temperatures of organic insulation film is poor, in the last annealing operation of array processes, deforms easily and causes the bad of diaphragm.Another shortcoming of organic insulation film is that dielectric constant is low, and storage capacitance descends and causes the hold facility of pixel voltage to descend.Above-mentioned patent about semiconductor chip and TFT passivation layer is all used high-molecular organic material.Compare the inorganic insulating material silicon nitride, the transmitance of visible light descends to some extent, causes weakening of TFT LCD panel luminance.
Summary of the invention
In order to overcome the defective in the above-mentioned technology, one of purpose of the present invention provides a kind of film transistor device that comprises the passivation layer structure of two-layer or more multi-layered dielectric film and adopt this structure.It uses a kind of inactivating performance good insulation performance film, as the top film of passivation layer, can prevent effectively that aqueous vapor and foreign ion from diffusing into TFT device or other semiconductor device; Below this passivating insulation membrane, form the bottom insulation film that one or more layers different materials is formed simultaneously, can play other effect.Two of purpose of the present invention is by the selection to the underlayer insulating film constituent material, and to the control of top layer insulating film thickness, reduces the light reflection and the light absorption of passivation layer, to increase the light transmission rate of semiconductor device such as TFT LCD.Three of purpose of the present invention is by the selection to bottom insulation film constituent material, and respective handling technology and THICKNESS CONTROL, weakens the stress that glass substrate and film bear, thereby the defective in the semiconductor device such as minimizing TFT LCD improves rate of finished products.Four of purpose of the present invention provides a kind of manufacturing method of passivation layer, uses same mask to form pattern two-layer or multilayer passivation layer diaphragm.Five of purpose of the present invention provides a kind of structure of passivation layer diaphragm, makes the top layer insulation film cover the bottom insulation film fully.
To achieve these goals, the invention provides a kind of passivation layer structure, wherein this passivation layer is made up of bottom insulation film and top layer passivation film, and the top layer passivation film covers on the bottom insulation film.
In such scheme, the bottom insulation film of described passivation layer is made up of silicon oxynitride.The top layer passivation film of described passivation layer is made up of silicon nitride, and this silicon nitride is specifically as follows silicon nitride.Described bottom insulation film thickness is thick than the thickness of top layer passivation film.Described bottom insulation film and top layer passivation film same position are formed with via hole, and bottom insulation film via size is greater than top layer passivation film via size, and the sidewall of top layer passivation film via hole covers the bottom insulation film fully.
To achieve these goals, the present invention provides a kind of film transistor device that is used for LCD simultaneously, comprise, be formed at the film transistor device on the glass substrate, be formed at the passivation layer on the film transistor device, it is characterized in that: described passivation layer is made up of bottom insulation film and top layer passivation film, and the bottom insulation film covers on film transistor device and the whole glass substrate, and the top layer passivation film covers on the bottom insulation film; Be formed with via hole on the described passivation layer, pixel electrode is connected by the metal electrode of this via hole and thin-film transistor.
In such scheme, the bottom insulation film of described passivation layer is made up of silicon oxynitride.The top layer passivation film of described passivation layer is made up of silicon nitride, and described silicon nitride is specifically as follows silicon nitride.Described bottom insulation film thickness is thick than the thickness of top layer passivation film.Described via hole is formed on bottom insulation film and top layer passivation film same position, and bottom insulation film via size is greater than top layer passivation film via size, and the top layer passivation film covers the bottom insulation film fully in the side of via hole.
To achieve these goals, the present invention also provides a kind of manufacturing method of passivation layer simultaneously, comprising:
Using mask in described step 1 and the step 2 is same mask, the thickness of the top layer passivation film that the more described step 2 of the bottom insulation film thickness that described step 1 forms forms is thick, when using the pattern of mask definition photoresist in described step 1 and the step 2, the photoresist of bottom insulation film coating is thick than the photoresist that applies on the top layer passivation film; Bottom insulation film resist exposure amount and time for exposure are higher than top layer passivation film resist exposure amount and the respective value of time for exposure.
In the above-mentioned manufacture method, when forming the bottom insulation film in the described step 1, form the film that mates with base material stress by the control membrance casting condition.What the via hole of corrosion formation bottom insulation film used in the described step 1 is the method for plasma etching.What the via hole of corrosion formation top layer passivating insulation membrane used in the described step 2 is the method for reactive ion etching.In the described step 1 the base material that forms one deck bottom insulation film on the base material be semiconductor device and under substrate.Described semiconductor device and under substrate be specially thin-film transistor and under the transparent insulation substrate.
The present invention is with respect to prior art, because in passivation layer structure, increases silicon oxynitride thickness and reduces silicon nitride thickness, realized the raising of TFT LCD display part light characteristic, therefore improves the display brightness of TFT LCD.By optimization process, reach the adjusting of membrane stress and the lifting of product yield simultaneously to the silicon oxynitride depositing operation.
The present invention makes TFT device and other semiconductor device keep reliable aqueous vapor and impurity barrier properties because the side of the bottom insulation film in the passivation layer is also covered by the top layer insulation film.
Passivation layer structure provided by the invention and adopt the film transistor device of this structure to improve TFTLCD device and other performance of semiconductor device.And the present invention also provides a kind of manufacture method of using a via hole mask to finish the photoetching of two-layer insulation passivation film, is compared to previous passivating film technology, and the method keeps the mask number constant, and the rising of effectively controlling cost.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 is the cross-sectional view that traditional handicraft is finished TFT device after the passivation layer via hole etching;
Fig. 2 is the cross-sectional view of TFT device after the passivation layer via hole etching of the present invention;
Fig. 3 is the cross-sectional view that the present invention deposits the bottom insulation film;
Fig. 4 is the cross-sectional view of the photoresist on the bottom insulation film of the present invention;
Fig. 5 is the cross-sectional view of bottom insulation film via etch of the present invention;
Fig. 6 is the cross-sectional view of deposited top layer passivation film TFT of the present invention;
Fig. 7 is the cross-sectional view of the photoresist on the top layer passivation film of the present invention;
Fig. 8 is a kind of cross-sectional view that the passivation layer structure of two-layer insulation film is arranged of the present invention;
Fig. 9 is the conditions of exposure figure of critical size of the present invention and exposure relation;
Figure 10 is the vertical view of photoresist via hole during the present invention double exposes.
Mark among the figure: 1, substrate; 2, gate electrode; 3, gate insulator; 4, active layer; 6, source electrode; 7, drain electrode; 8, passivation layer; 9, passivation layer via hole; 10, pixel electrode; 11, bottom insulation film; 12, top layer passivation film; 13, TFT substrate; 14, metal electrode; 16, bottom insulation film photoresist; 17, the via hole of bottom insulation film; 18, top layer passivation film photoresist; 19, the via hole of top layer passivation film.
Embodiment
Passivation layer structure provided by the invention is made up of bottom insulation film and top layer passivation film, and the top layer passivation film covers the bottom insulation film.The bottom insulation film is made up of silicon oxynitride or the high material of other coefficient of transparency; The top layer passivating film is made up of materials such as silicon nitrides.For the passivation layer top is connected with the parts of passivation layer below, at the bottom insulation film and the top layer passivation film same position formation via hole of passivation layer; Guarantee bottom insulation film via size greater than top layer passivation film via size, the top layer passivation film covers the bottom insulation film fully in the side of via hole.This passivation layer structure can be applicable in Thin Film Transistor-LCD or the former device of its semiconductor.
Below in conjunction with Thin Film Transistor-LCD in detail passivation layer structure of the present invention is described in detail.
As shown in Figure 2, be the cross-sectional view that adopts a kind of Thin Film Transistor-LCD of passivation layer structure of the present invention.TFT device shown in Figure 2 is made of substrate 1, gate electrode 2, gate insulator 3, active layer 4, source electrode 6 and drain electrode 7, and wherein source electrode 6 is connected with data wire, and drain electrode 7 is connected with pixel electrode 10 at passivation layer via hole 9 places.The passivation layer of this TFT LCD device is made up of double-layer films, bottom insulation film 11 and top layer passivation film 12; And the passivation layer of TFT LCD device shown in Figure 1 is made up of thin film.The feature that the present invention is different from prior art as seen from Figure 2, top layer passivation film 12,9 places have covered bottom insulation film 11 fully at via hole.Bottom insulation film 11 is by visible absorption coefficient materials with smaller is constituted.What adopt in the present embodiment is that semiconductor device antireflection film commonly used is a silicon oxynitride.Top layer passivation film 12 adopts silicon nitride film commonly used to constitute in the present embodiment.The thickness of silicon nitride film is less than the thickness of silicon oxynitride film, and promptly silicon nitride only occupies sub-fraction at passivation layer.Bottom insulation film 11 and top layer insulation film 12 have identical pattern, in the open area that metal electrode form to connect, and the removal that all is etched of bottom insulation film and top layer passivation film.Because the bandwidth difference of silicon oxynitride and silicon nitride makes silicon oxynitride have the light transmission more superior than silicon nitride.In passivation layer structure, increase silicon oxynitride thickness and reduce silicon nitride thickness, realize the raising of TFT LCD display part light characteristic, therefore improve the display brightness of TFT LCD.By optimization process, can reach the adjusting of membrane stress and the lifting of product yield to the silicon oxynitride depositing operation.
A unique distinction of passivation layer structure of the present invention is that the bottom insulation film at via hole place is covered by the top layer insulation film fully, makes the passivation layer protective value not changed and deterioration by the material of bottom insulation film.The passivation layer that some other uses multi-layer insulation film to form, its top layer insulation film and bottom insulation film form pattern by a successive sedimentation and a photoetching, make the bottom insulation film expose its sidewall in external environment condition at the via hole place like this.The passivation protection character of bottom insulation film will be weaker than the top layer insulation film, makes the infiltration of TFT LCD device as easy as rolling off a log other material of generation in hot and humid environment, cause the TFT device failure and produce show bad.The side of the bottom insulation film in the passivation layer of the present invention is covered by the top layer insulation film, makes the TFT device keep reliable aqueous vapor and impurity barrier properties.
The concrete manufacture method of the passivating film of said structure is as follows:
Passivation layer preparation method to this structure on the Thin Film Transistor-LCD describes in detail below in conjunction with accompanying drawing, and is extremely shown in Figure 8 as Fig. 3.
At first, use chemical vapor deposited method, preparation one layer thickness is at 1000 to 6000 dielectric film on the glass substrate that forms the TFT device.This insulation film constitutes the bottom insulation film 11 of passivation layer, generally uses silicon oxynitride or the high material of other light-transmission coefficient.As shown in Figure 3, bottom insulation film 11 is formed at above the metal electrode 14 at TFT substrate 13 and top.In the technical process of thin film deposition, select the plasma power and the reaction pressure of proper range, the control plasma power is between 1000 watts to 10000 watts, and reaction pressure is between 1 holder is held in the palm to 3, with the insulation film of formation and TFT base plate stress coupling.By the photoetching process first time, on bottom insulation film 11, form the pattern of bottom insulation film photoresist 16.The photoresist thickness of photoetching process is between 1 micron to 3 microns for the first time, and the photolithographic exposure amount is by via size and the decision of photoresist thickness.Use the method for plasma etching, at the opening part erosion removal bottom insulation film of photoresist.Control etching air pressure is below 100 millitorrs, and plasma power is between 3000 watts to 5000 watts, and the flow-rate ratio of sulphur hexafluoride and oxygen is formed with the bottom insulation film via hole 17 near side, vertical bank angle greater than 1.Utilize chemical vapor deposited method subsequently, the top layer passivation film 12 of deposit one deck 200 to 1000 on substrate, the covering bottom insulation film 11 as shown in Figure 6 and the metal electrode 14 of via hole 17 exposures thereof.The passivation film material generally is a silicon nitride, its sedimentary condition be plasma power between 4000 watts to 8000 watts, reaction pressure 1 the holder to 2 the holder between.
As shown in Figure 7, use the mask of same passivation layer via hole, top layer passivation film 12 is carried out photoetching process, form the pattern of top layer passivation film photoresist 18.By the selection of photoresist thickness and conditions of exposure, can on passivating film, form photoresist opening less than bottom insulation film via hole 17 sizes.Generally about 1 micron, its exposure and time for exposure are lower than the respective value when forming bottom insulation film via hole to photoresist thickness above the top layer passivation film 12.As shown in Figure 9, the critical size of photoresist changes along with the different of exposure and time for exposure.Photoresist critical size shown in the figure is that photoresist line size and the passivation layer via hole size after developing is inverse relation.The critical size of photoresist is big more, and the size of passivation layer via hole is just more little.As can be seen, along with the increase of exposure and the prolongation of time for exposure, the passivation layer via hole size can increase.For bottom insulation film via hole and top layer passivation film via hole, when using same mask to carry out photoetching process, select different etching conditions, just can realize the via hole of different size as shown in figure 10 at same position.In order to accelerate pitch time as far as possible, general 85 millis burnt above exposure and the developing time more than 90 seconds of adopting, form the photoresist via hole on the bottom insulation film, adopt the burnt following exposures of 85 millis and 90 seconds, form the photoresist via hole on the top layer insulating film with interior developing time.Next utilize reactive ion etching process to finish as shown in Figure 8 top layer passivation film via hole 19.Method with reactive ion etching, control etching air pressure is more than 100 millitorrs, plasma power is between 2000 watts to 4000 watts, the flow-rate ratio of sulphur hexafluoride and oxygen is about 1, can form relatively gentle incline at passivating film via hole place, help being connected of later pixel electrode and metal electrode.
The foregoing description is to be applicable to display device, as the TFT LCD of amorphous silicon and the TFT LCD of polysilicon, forms the passivation protection film of switching device.Yet passivation layer structure of the present invention and manufacture method are not limited to display device.By selecting bottom insulating film material and top layer passivation film material, and appropriate change thin film deposition, etching and photoresist process condition, the present invention also is applicable to other semiconductor device, the electronic device of monocrystalline substrate such as memory body chip, logic chip, the electronic device of three or five family's Semiconductor substrate such as GaAs microwave device or the like.
Explanation is at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (9)
1. film transistor device that is used for LCD, comprise, be formed at the film transistor device on the glass substrate, be formed at the passivation layer on the film transistor device, it is characterized in that: described passivation layer is made up of bottom insulation film and top layer passivation film, the bottom insulation film covers on film transistor device and the whole glass substrate, and the top layer passivation film covers on the bottom insulation film; The bottom insulation film of described passivation layer is made up of silicon oxynitride, and the top layer passivation film of described passivation layer is made up of silicon nitride, and described bottom insulation film thickness is thick than the thickness of top layer passivation film; Be formed with via hole on the described passivation layer, pixel electrode is connected by the metal electrode of this via hole and thin-film transistor.
2. film transistor device according to claim 1 is characterized in that: described silicon nitride is specially silicon nitride.
3. film transistor device according to claim 1 and 2, it is characterized in that: described via hole is formed on bottom insulation film and top layer passivation film same position, bottom insulation film via size is greater than top layer passivation film via size, and the sidewall of top layer passivation film via hole covers the bottom insulation film fully.
4. a manufacturing method of passivation layer is characterized in that, comprising:
Step 1 forms one deck bottom insulation film on base material, described bottom insulation film covers on film transistor device and the whole glass substrate, uses the pattern of mask definition photoresist, is formed by etching the via hole of bottom insulation film;
Step 2 on the bottom insulation film, forms one deck top layer passivation film, uses the pattern of mask definition photoresist, is formed by etching the via hole of top layer passivating film;
Using mask in described step 1 and the step 2 is same mask, the thickness of the top layer passivation film that the more described step 2 of the bottom insulation film thickness that described step 1 forms forms is thick, when using the pattern of mask definition photoresist in described step 1 and the step 2, the photoresist of bottom insulation film coating is thick than the photoresist that applies on the top layer passivation film; Bottom insulation film resist exposure amount and time for exposure are higher than top layer passivation film resist exposure amount and the respective value of time for exposure.
5. manufacture method according to claim 4 is characterized in that: when forming the bottom insulation film in the described step 1, form the film with base material stress coupling.
6. manufacture method according to claim 4 is characterized in that: what the via hole of corrosion formation bottom insulation film used in the described step 1 is the method for plasma etching.
7. manufacture method according to claim 4 is characterized in that: what the via hole of corrosion formation top layer passivating insulation membrane used in the described step 2 is the method for reactive ion etching.
8. according to the described manufacture method of arbitrary claim in the claim 4 to 7, it is characterized in that: in the described step 1 the base material that forms one deck bottom insulation film on the base material be semiconductor device and under substrate.
9. manufacture method according to claim 8 is characterized in that: described semiconductor device and under substrate be specially thin-film transistor and under the transparent insulation substrate.
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| CN109216434A (en) * | 2017-06-30 | 2019-01-15 | 三垦电气株式会社 | The method of semiconductor devices and manufacturing semiconductor devices |
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| CN102420194B (en) * | 2011-04-29 | 2014-06-04 | 上海华力微电子有限公司 | Passivation layer of integrated circuit and manufacturing method of passivation layer |
| CN102593050B (en) * | 2012-03-09 | 2014-08-20 | 深超光电（深圳）有限公司 | Method for manufacturing liquid crystal display panel array substrate |
| CN102709241A (en) * | 2012-05-11 | 2012-10-03 | 北京京东方光电科技有限公司 | Thin film transistor array substrate and preparation method and display device |
| CN103928397B (en) * | 2013-10-08 | 2017-10-13 | 上海天马微电子有限公司 | A kind of tft array substrate and preparation method thereof and display device |
| CN103676354B (en) | 2013-12-06 | 2016-03-23 | 合肥京东方光电科技有限公司 | Electrode structure and preparation method, array base palte and preparation method and display device |
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| CN105742238A (en) * | 2016-03-02 | 2016-07-06 | 京东方科技集团股份有限公司 | Pore structure and array substrate, manufacturing methods of pore structure and array substrate, detection device and display device |
| CN107068612B (en) * | 2017-05-12 | 2021-04-13 | 京东方科技集团股份有限公司 | Manufacturing method of via hole, manufacturing method of display substrate and display substrate |
| CN109616418B (en) * | 2018-12-06 | 2021-11-09 | 合肥鑫晟光电科技有限公司 | Thin film transistor, display substrate, manufacturing method of display substrate and display device |
| CN109742158A (en) | 2019-01-31 | 2019-05-10 | 京东方科技集团股份有限公司 | Low-temperature polysilicon film transistor, array substrate and preparation method, display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1278660A (en) * | 1999-06-04 | 2001-01-03 | 株式会社半导体能源研究所 | Photoelectric apparatus and electronic apparatus |
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| CN1278660A (en) * | 1999-06-04 | 2001-01-03 | 株式会社半导体能源研究所 | Photoelectric apparatus and electronic apparatus |
Non-Patent Citations (4)
| Title |
|---|
| CN 1278660 A,说明书第3页第18行-第9页第30行、附图1. |
| JP昭63-299237A 1988.12.06 |
| JP特开2000-228503A 2000.08.15 |
| JP特开平5-166803A 1993.07.02 |
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| CN109216434A (en) * | 2017-06-30 | 2019-01-15 | 三垦电气株式会社 | The method of semiconductor devices and manufacturing semiconductor devices |
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