CN212113723U - Display substrate and display panel - Google Patents

Abstract

The embodiment of the present disclosure provides a display substrate, including: a substrate base plate; an active layer pattern on one side of the substrate base plate and having a semiconductor region for conduction; the photoresist pattern is positioned between the substrate base plate and the active layer pattern, the orthographic projection of the photoresist pattern on the substrate base plate at least completely covers the semiconductor area, the photoresist pattern comprises at least one side surface, an inclined angle is formed between the plane of the side surface and the plane of the substrate base plate, and the orthographic projection of the side surface on the substrate base plate and the orthographic projection of the active layer pattern on the substrate base plate are overlapped; a dielectric layer located between the active layer pattern and the photoresist pattern, configured such that a surface of the active layer facing the substrate is parallel to a plane of the substrate, the photoresist pattern has a maximum thickness d1, the dielectric layer has a maximum thickness d2, d1 and d2 satisfy: d1 < d 2.

Description

Display substrate and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display panel.

Background

Low Temperature Poly-Silicon (LTPS) Thin Film Transistors (TFTs) are widely used in the field of display technology due to their advantages of miniaturization, thinness, and Low power consumption. In LTPS type TFTs, the active layer pattern is the core layer of the entire device, and the quality of the polysilicon (also known as p-Si) film will directly determine the effect and quality of the final display product.

In the related art, in the process of crystallizing a monocrystalline silicon (also called a-Si) film by laser irradiation to prepare a p-Si film, the problem of cracking (Crack) of the p-Si film is easy to occur, thereby causing the problem of abnormal electrical characteristics of the finally formed TFT.

SUMMERY OF THE UTILITY MODEL

The present disclosure is directed to at least one of the technical problems in the prior art, and provides a display substrate and a display panel.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including:

a substrate base plate;

an active layer pattern on one side of the substrate base plate and having a semiconductor region for conduction;

the photoresist pattern is positioned between the substrate base plate and the active layer pattern, the orthographic projection of the photoresist pattern on the substrate base plate at least completely covers the semiconductor area, the photoresist pattern comprises at least one side surface, an inclined angle is formed between the plane of the side surface and the plane of the substrate base plate, and the orthographic projection of the side surface on the substrate base plate and the orthographic projection of the active layer pattern on the substrate base plate are overlapped;

the dielectric layer is positioned between the active layer pattern and the light resistance pattern and is configured to enable the surface, facing the substrate, of the active layer to be parallel to the plane of the substrate;

the maximum thickness of the photoresist pattern is d1, the maximum thickness of the dielectric layer is d2, and d1 and d2 satisfy the following conditions: d1 < d 2.

In some embodiments, the range of tilt angles includes: 50 to 90 degrees.

In some embodiments, the material of the dielectric layer comprises: an organic resin material;

the glass transition temperature of the organic resin material is greater than 250 ℃.

In some embodiments, the organic resin material includes: and (3) a polyimide.

In some embodiments, the polyimide cure level ranges include: 10 to 20 percent.

In some embodiments, the dielectric layer is disposed over the entire surface of the substrate and is transparent.

In some embodiments, the dielectric layer has a coefficient of thermal expansion less than or equal to 20 ppm/K.

In some embodiments, the maximum thickness d1 of the photoresist pattern satisfies:

the maximum thickness d2 of the dielectric layer satisfies the following conditions: d2 is less than or equal to 10 um.

In some embodiments, the display substrate further comprises:

and the buffer layer is positioned between the dielectric layer and the active layer pattern, and the surface of one side, away from the substrate base plate, of the buffer layer is parallel to the plane of the substrate base plate.

In some embodiments, the display substrate further comprises:

the grid insulating layer is positioned on one side of the active layer pattern, which is far away from the substrate;

the grid electrode is positioned on one side of the grid insulating layer, which is far away from the substrate base plate;

and the source and drain electrodes are positioned on one side of the active layer pattern, which is far away from the substrate base plate, and are connected with the active layer pattern.

In a second aspect, an embodiment of the present disclosure provides a display panel, including: the display substrate and the counter substrate disposed opposite to the display substrate are provided as in the first aspect.

Drawings

Fig. 1a is a schematic cross-sectional view of a display substrate according to an embodiment of the disclosure;

FIG. 1b is a schematic top view of a photoresist pattern, an active layer pattern and a gate line in an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of an intermediate product in forming a p-Si thin film during fabrication of the display substrate shown in FIG. 1 a;

FIG. 3 is a schematic view illustrating an a-Si thin film subjected to excimer laser annealing treatment in the absence of a dielectric layer between an active layer pattern and a photoresist pattern;

FIG. 4 is a graph showing the photoresist pattern of FIG. 3 having a thickness of

The schematic diagram of the V-I curves of the TFTs at different point positions on the substrate is displayed;

FIG. 5 is a graph showing the photoresist pattern of FIG. 3 having a thickness of

Time displaySchematic V-I curve diagrams of TFTs at different point positions on the substrate;

FIG. 6 is a schematic view of a V-I curve of a TFT at different points on a display substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another display substrate provided in the embodiment of the present disclosure;

FIG. 8 is a schematic cross-sectional view of an intermediate product in forming a p-Si thin film in the process of manufacturing the display substrate shown in FIG. 7;

fig. 9 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the disclosure.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, a display substrate and a display panel provided in the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1a is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure, fig. 1b is a schematic top view of a photoresist pattern, an active layer pattern, and a gate line according to an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional view of an intermediate product when a p-Si thin film is formed in a process of preparing the display substrate shown in fig. 1a, as shown in fig. 1a to 2, the display substrate includes: a substrate 1, a photoresist pattern 2, a dielectric layer 5 and an active layer pattern 4.

The active layer pattern 4 is located on one side of the base substrate 1, and has a semiconductor region 10 for conduction; here, the "semiconductor region 10" refers to a portion of the active layer pattern 4 where a conductive channel can be formed under the control of a gate voltage, and specifically, a region where the gate line 6a overlaps the active layer pattern 4 in fig. 1 b. It should be noted that fig. 1b schematically shows a case where one active layer pattern 4 has two semiconductor regions 10 in the double gate TFT.

The photoresist pattern 2 is located on one side between the substrate base plate 1 and the active layer pattern 4, the orthographic projection of the photoresist pattern 2 on the substrate base plate at least completely covers the semiconductor area 10, the photoresist pattern comprises at least one side surface, the side surface is located on a plane with an inclined angle B with the plane of the substrate base plate, and the orthographic projection of the side surface on the substrate base plate and the orthographic projection of the active layer pattern on the substrate base plate are overlapped.

The dielectric layer 5 is located between the active layer pattern 4 and the photoresist pattern 2, and is configured such that the surface of the active layer pattern 4 facing the base substrate 1 is parallel or approximately parallel to the plane of the base substrate 1. Specifically, the side of the dielectric layer facing the active layer pattern 4 is a planarized surface. In the embodiments of the present disclosure, the term "planarized surface" specifically means that the corresponding surface is planar or approximately planar, and the surface is parallel or approximately parallel to the plane of the substrate 1. The maximum thickness of the photoresist pattern 2 is d1, the maximum thickness of the dielectric layer 5 is d2, and d1 and d2 satisfy d1 < d2, so that the dielectric layer 5 can completely cover the photoresist pattern 2, and a flattened surface can be formed.

It should be noted that fig. 1a only illustrates one photoresist pattern 2 and one active layer pattern 4, which does not limit the technical solution of the present disclosure. In practical application, the plurality of photoresist patterns 2 and the plurality of TFTs on the display substrate are arranged in an array.

In the embodiment of the present disclosure, since the photoresist pattern 2 completely covers the semiconductor region 10, light emitted from a side of the substrate 1 away from the active layer pattern 4 can be effectively prevented from being emitted to the semiconductor region 10, so that the electrical characteristics of the semiconductor region 10 can be ensured to be stable; meanwhile, because the side portion (i.e. the edge portion) of the photoresist pattern 2 has a larger inclination angle B, the edge portion of the photoresist pattern 2 also has a thicker thickness, thereby ensuring the edge shading effect of the photoresist pattern 2; in addition, because the orthographic projection of the side part of the light resistance pattern 2 on the substrate and the orthographic projection of the active layer pattern on the substrate are overlapped, namely the size of the light resistance pattern 2 is just enough to shield light and is not too large, the influence on the aperture opening ratio can be reduced, and the phenomenon that the light of the external environment irradiates the light resistance pattern 2 and then reflects and irradiates the semiconductor region 10 is avoided.

In some embodiments, the range of the tilt angle B includes: 50 to 90 degrees.

Fig. 3 is a schematic view illustrating the case where the a-Si thin film is subjected to excimer laser annealing without a dielectric layer between the active layer pattern and the photoresist pattern, as shown in fig. 3, and the thickness of the side portion of the photoresist pattern 2 is rapidly changed due to the above-mentioned design of the photoresist pattern 2, and the side portion corresponds to the active layer pattern 4. When the a-Si thin film is processed by an Excimer Laser Annealing (ELA) process, the distance between the a-Si thin film and a Laser source (heat source) is not locally close due to a step difference on the a-Si thin film, so that uneven heating is caused, and the property difference of the formed p-Si thin film 4a at a distance inflection point (i.e., an area Q where the step difference is formed) from the heat source is easily caused to be large, so that fracture occurs. And because the broken region Q on the p-Si film corresponds to the side face of the light resistance pattern 2, and the active layer pattern 4 required to be prepared is overlapped with the side face of the light resistance pattern 2, the active layer pattern 4 obtained after the p-Si film is subjected to the patterning process is also broken, so that the TFT has poor electrical characteristics.

The light-shielding effect of the resist pattern 2 is generally evaluated by using an Optical Density (Optical sensitivity) value, and a larger OD value indicates a better light-shielding effect; generally speaking, when the OD is greater than or equal to 4, the photoresist pattern 2 is considered to have a better light-shielding effect; wherein the photoresist pattern 2 has a thickness of

The corresponding OD value is about 4, and the thickness of the photoresist pattern 2 is

The corresponding OD value is about 6.

FIG. 4 is a graph showing the photoresist pattern of FIG. 3 having a thickness of

A schematic view of a V-I curve of a TFT at different points on a display substrate, and FIG. 5 is a graph showing a photoresist pattern having a thickness of

The V-I curves of the TFTs at different points on the substrate are shown in FIG. 4 and FIG. 5, where the thickness of the photoresist pattern 2 is

When the source-drain voltage Vds of the TFTs at different points on the display substrate is 0.1V, the gate-source voltage Vgs-current I curves (also called V-I curves) of the TFTs at different points on the display substrate measured by a lighting test are converged to form a curve cluster A; under the condition that source-drain voltages Vds which are 10V are provided for the TFTs at different points on the display substrate, the V-I curves of the TFTs at different points on the display substrate are measured to be converged through a lighting test, and a curve cluster B is formed. At the moment, in an interval of 0-1V of gate-source voltage (Vgs is smaller than an interval of threshold voltage), the curve cluster A and the curve cluster B are obviously separated, namely under the condition of different source-drain voltages, the threshold voltage of the TFT has certain deviation, which indicates that the electrical characteristics of the TFT have certain abnormity. That is, the electrical characteristic abnormality of the TFT can be detected by the lighting test.

In the thickness of the resist pattern 2

In the process, under the condition that source-drain voltages Vds which are 0.1V are provided for the TFTs at different point positions on the display substrate, the V-I curve dispersion of the TFTs at different point positions on the display substrate is measured through a lighting test; under the condition that source-drain voltages Vds which are 10V are provided for the TFTs at different points on the display substrate, the V-I curves of the TFTs at different points on the display substrate measured through a lighting test are also dispersed; all the V-I curves measured under the condition that Vds is 0.1V and all the V-I curves measured under the condition that Vds is 10V are dispersed and distributed in a staggered mode in a gate source voltage range from 0V to 1V, and at the moment, the electrical characteristics of the TFT are seriously abnormal and even can not be measured.

In order to solve the above problems caused by the photoresist pattern 2, in the technical scheme of the present disclosure, the dielectric layer 5 is disposed between the active layer pattern 4 and the photoresist pattern 2, and the surface of the structural layer in the display substrate, which is in direct contact with the surface of the active layer pattern 4 on the side close to the substrate 1, is a planarized surface, so that there is no step difference on the a-Si film formed on the planarized surface of the structural layer, and the surface of the a-Si film on the side away from the substrate 1 is a planarized surface. When the a-Si film is processed by the ELA process, because the a-Si film has no segment difference, the distance between the a-Si film and a laser source is close everywhere, the a-Si film is uniformly heated, and the property difference of p-Si formed after crystallization at each position is small (the range of p-Si crystal grains is 0.3-0.5 um), so that the Crack existing on the formed p-Si film 4a can be effectively avoided. The surface of the active layer pattern 4 obtained by performing a patterning process on the p-Si thin film 4a is also a flattened surface and has no Crack, so that the electrical characteristics of the finally prepared TFT can be effectively ensured to be normal.

In some embodiments, the dielectric layer 5 is disposed over the entire surface of the substrate and is transparent.

In some embodiments, considering that the temperature of the surface of the a-Si thin film is high during the ELA process, the temperature of the structure under the Si thin film is also high (up to 200-250 ℃), and a certain heat resistance is required for the structure under the Si thin film to prevent the structure under the Si thin film from being deformed by heat to damage the planarized surface. For this reason, in the disclosed embodiment, the coefficient of thermal expansion of the dielectric layer 5 should be less than or equal to 20 ppm/K.

In some embodiments, the material of the dielectric layer 5 includes: the organic resin material is a material with good planarization and uniformity, and can effectively eliminate the step difference caused by the photoresist pattern 2. When preparing the dielectric layer 5 made of an organic resin material, it is necessary to coat an organic resin material paste having fluidity first, and then cure the organic resin material paste, so as to obtain the dielectric layer 5 having a planarized surface.

Since the organic resin material is a high polymer, it undergoes a glass transition from a glass state to a high elastic state (from a molecular structure, the organic resin material is a relaxation phenomenon from a frozen state to a thawed state), and at this time, the specific heat capacity, thermal expansion coefficient, viscosity, refractive index, free volume, elastic modulus, and the like of the organic resin material all undergo a sudden change. To prevent the glass transition of the organic resin material during the ELA process, in the disclosed embodiments, the glass transition temperature of the organic resin material is greater than 250 ℃.

In some casesIn an embodiment, the organic resin material includes: polyimide (abbreviated as PI). The performance parameters of the polyimide used in the embodiments of the present disclosure are as follows: the solid content is 10-20%, the viscosity is 1000-9000 mPa.S, the thermal expansion coefficient is 0-20 ppm/K at 50-450 ℃, the glass transition temperature is more than 470 ℃, and the viscosity is H₂O, CO2 has a gassing property parameter of less than 100 wtppb/s.

When the dielectric layer 5 is made of the polyimide, the viscosity, the thermal expansion coefficient, the glass transition temperature and the gas overflow characteristic of the dielectric layer 5 can adapt to the high-temperature environment in the ELA process. Specifically, the polyimide has higher viscosity, so that the PI film is favorably attached to the substrate base plate and the upper film layer; the polyimide has a small thermal expansion coefficient, so that the dielectric layer 5 can be prevented from being greatly deformed in the ELA process, and the flatness of the dielectric layer 5 is ensured; the glass transition temperature of the polyimide is higher than 470 ℃, so that the polyimide does not have glass transition in the ELA process; in addition, the gas overflowing characteristic of the polyimide can avoid bubbles in the polyimide in a high-temperature environment, and the flatness of the dielectric layer 5 can be guaranteed.

With continued reference to fig. 1a and 2, in some embodiments, a buffer layer 3 is formed between the base substrate 1 and the active layer pattern 4, and the buffer layer 3 may prevent metal ions and impurities (e.g., Si-H bonds) in the base substrate 1 from diffusing into the p-Si thin film 4a during the ELA process to ensure stable electrical characteristics of the p-Si thin film 4 a. At this time, the buffer layer 3 is a structural layer directly contacting the surface of the active layer pattern 4 on the side closer to the substrate 1.

The buffer layer 3 may be formed by depositing silicon nitride (SiNx) and/or silicon oxide (SiO 2) by a Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD process has the advantages of low basic temperature, high deposition rate, good film forming quality (uniform film forming thickness), fewer pinholes, difficult cracking and the like, and can ensure that the surface of the buffer layer 3 formed on the surface of the dielectric layer 5, which is far away from the substrate base plate 1, is a flattened surface. It should be noted that, because the film-forming thickness of the buffer layer 3 deposited by the PECVD process is uniform, when the dielectric layer 5 is not present (see fig. 3), the surface of the buffer layer 3 on the side away from the substrate base plate 1 is not a planarized surface, and at this time, the surface of the active layer formed on the buffer layer 3 facing the substrate base plate cannot be parallel to the plane of the substrate base plate, so the buffer layer 3 cannot replace the dielectric layer 5 in the embodiment of the present disclosure.

In some embodiments, the maximum thickness d1 of the photoresist pattern 2 and the maximum thickness d2 of the dielectric layer 5 satisfy:

and d2 is less than or equal to 10 um. In some embodiments of the present invention, the,

the photoresist pattern 2 can provide a better light-shielding effect and is relatively light and thin. In the embodiment of the present disclosure, the maximum thickness of the dielectric layer 5 should be greater than the maximum thickness of the photoresist pattern 2 to ensure that the dielectric layer 5 can form a planarized surface, but the thickness of the dielectric layer 5 should not be too large in consideration of light transmittance, the overall thickness of the substrate, and the like.

With continued reference to fig. 4, in some embodiments, the display substrate further comprises: a gate insulating layer 9, a gate electrode 6 (in fig. 1b the gate line 6a is located in the portion of the semiconductor region 10) and a source drain 7 (divided into a source and a drain). Wherein, the gate insulating layer 9 is positioned on one side of the active layer pattern 4 far away from the substrate base plate 1; the grid electrode 6 is positioned on one side of the grid insulating layer 9 far away from the substrate base plate 1; the source and drain electrodes 7 are located on one side of the active layer pattern 4 far away from the substrate base plate 1 and are overlapped with the active layer pattern 4. The TFT in the embodiment of the present disclosure is a top gate TFT, and details of a specific structure of the top gate TFT are not described herein.

It should be noted that fig. 4 only illustrates a case where the insulating layer 8 is formed on the side of the gate electrode 6 away from the substrate 1, and the source/drain electrode 7 is located on the side of the insulating layer 8 away from the substrate 1 and is connected to the active layer pattern 4 through a via hole on the insulating layer 8 and the gate insulating layer 9. In the embodiment of the present disclosure, the source/drain 7 may also be located between the gate insulating layer 9 and the active layer pattern 4, and the source/drain 7 is directly connected to the active layer pattern 4; the source and drain 7 may also be located on a side of the gate insulating layer 9 away from the substrate 1 and disposed on the same layer as the gate 6, and the source and drain 7 is connected to the active layer pattern 4 through a via hole in the gate insulating layer 9 (no corresponding figures are given in these two cases). In order to ensure that the surface of the substrate is a flattened surface when the active layer pattern 4 is prepared, the preparation process of the source/drain electrode 7 is performed after the preparation process of the active layer pattern 4, that is, the source/drain electrode 7 is positioned on the side of the active layer pattern 4 away from the substrate 1.

Fig. 6 is a schematic view of a V-I curve of a TFT at different points on a display substrate according to an embodiment of the present disclosure, as shown in fig. 6, in the embodiment of the present disclosure, due to the existence of the dielectric layer 5, occurrence of Crack can be effectively avoided, and it is assumed that an ideal threshold voltage of the TFT is 1V. In the thickness of the resist pattern 2

When the source-drain voltage Vds provided for the TFTs at different points on the display substrate is 0.1V, the V-I curves of the TFTs at different points on the display substrate are measured to converge through a lighting test, and a curve cluster A' is formed; under the condition that source-drain voltages Vds which are 10V are provided for the TFTs at different points on the display substrate, V-I curves of the TFTs at different points on the display substrate are measured to be converged through a lighting test at the moment, and a curve cluster B' is formed. At the moment, in the range of 0-1V of the gate-source voltage, the curve cluster A 'and the curve cluster B' are obviously converged, namely, under the condition of different source-drain voltages, the threshold voltage of the TFT is not shifted, which indicates that the electrical characteristics of the TFT are normal. That is, it can be detected through the lighting test that the electrical characteristics of the TFT on the display substrate provided by the present disclosure are normal.

Fig. 7 is a schematic structural diagram of another display substrate provided in an embodiment of the present disclosure, and fig. 8 is a schematic cross-sectional diagram of an intermediate product when a p-Si thin film is formed in a process of manufacturing the display substrate shown in fig. 7, as shown in fig. 7 and 8, unlike the case shown in fig. 4 and 5, in which the buffer layer 3 is not present in the display substrate and the intermediate product shown in fig. 7 and 8.

In the embodiment, the dielectric layer 5 may be made of a material with better compactness and high temperature resistance, such as an organic resin material (specifically, PI material), at this time, the dielectric layer 5 may not only perform a planarization function, but also prevent metal ions and impurities in the substrate 1 from diffusing to the p-Si thin film 4a in the ELA process, at this time, the buffer layer 3 is not required to be further disposed, which is beneficial to thinning the display substrate. In addition, the dielectric layer 5 is made of a high-temperature resistant material, so that the dielectric layer 5 can be effectively prevented from being subjected to large thermal deformation in an ELA process.

Fig. 9 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure, and as shown in fig. 9, the method for manufacturing a display substrate according to the foregoing embodiment includes:

step S1 is to form a photoresist pattern on one side of the substrate.

Wherein, the orthographic projection of the light resistance pattern on the substrate at least completely covers the semiconductor area 10 of the active layer pattern to be formed subsequently, the light resistance pattern comprises at least one side surface, the surface of the side surface and the plane of the substrate have an inclined angle, and the orthographic projection of the side surface on the substrate and the orthographic projection of the active layer pattern to be formed subsequently on the substrate are overlapped.

In some embodiments, the range of tilt angles includes: 50 to 90 degrees.

In some embodiments, the maximum thickness d1 of the photoresist pattern satisfies:

in some embodiments of the present invention, the,

at this time, the photoresist pattern can provide a better light-shielding effect and is relatively light and thin.

And step S2, forming a dielectric layer covering the surface and the side face of the photoresist pattern far away from the substrate base plate, wherein the surface of the dielectric layer far away from the substrate base plate is parallel to the plane of the substrate base plate.

In some embodiments, the dielectric layer is disposed over the entire surface of the substrate and is transparent. At the moment, a composition process is not needed in the process of preparing the dielectric layer, so that the preparation difficulty can be reduced.

In some embodiments, the maximum thickness of the dielectric layer d2 satisfies: d2 is more than d1 and less than or equal to 10 um.

In some embodiments, the material of the dielectric layer comprises an organic resin material. In this case, step S2 specifically includes: firstly, coating an organic resin material on the surface and the side surface of one side of a light resistance pattern, which is far away from a substrate; then, the organic resin material is cured to obtain the dielectric layer.

Further, the organic resin material includes: a polyimide; the curing treatment is a heat curing treatment.

And step S3, forming an active layer pattern on one side of the dielectric layer far away from the substrate.

In step S3, the step of forming the active layer pattern includes: firstly, adopting PECVD (plasma enhanced chemical vapor deposition) to deposit an a-Si film which is a planarization film; then, the a-Si film is processed through an ELA process, so that the a-Si is crystallized to be p-Si, the a-Si film is uniformly heated in the ELA process, and the property difference of the p-Si formed after crystallization at each position is small (the p-Si crystal grain range is 0.3 um-0.5 um), so that the Crack existing on the formed p-Si film can be effectively avoided; and finally, carrying out patterning process on the p-Si film to obtain an active layer pattern, wherein the active layer pattern does not have Crack.

It should be noted that the patterning process in the embodiment of the present disclosure specifically includes steps of photoresist coating, mask exposure, development, film etching, photoresist stripping, and the like.

In some embodiments, between step S1 and step S2 further comprising: and forming a buffer layer on one side of the dielectric layer, which is far away from the substrate base plate, wherein the surface of one side of the buffer layer, which is far away from the substrate base plate, is a flattened surface. At this time, a buffer layer is present on the prepared display substrate, as shown in fig. 1a and 2. Wherein the buffer layer 3 may be prepared by depositing a silicon nitride and/or silicon oxide material by a PECVD process.

In some embodiments, after step S3, the method further includes: and forming a gate insulating layer, a gate electrode and a source drain electrode. The formation of the gate insulating layer, the gate electrode, and the source/drain electrodes may be performed by a conventional array process (also referred to as an array process), and will not be described herein again.

The embodiment of the present disclosure further provides a display panel, which includes the display substrate provided in the above embodiment and a counter substrate disposed opposite to the display substrate.

In some embodiments, the display panel may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

When the display panel is a liquid crystal panel, the counter substrate is specifically a pair of box substrates, and liquid crystal is filled between the pair of box substrates and the display substrate; when the display panel is an OLED panel, the opposite substrate is specifically a cover plate, and the cover plate can realize encapsulation of the OLED.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims (11)

1. A display substrate, comprising:

a substrate base plate;

an active layer pattern on one side of the substrate base plate and having a semiconductor region for conduction;

the photoresist pattern is positioned between the substrate base plate and the active layer pattern, the orthographic projection of the photoresist pattern on the substrate base plate at least completely covers the semiconductor area, the photoresist pattern comprises at least one side surface, an inclined angle is formed between the plane of the side surface and the plane of the substrate base plate, and the orthographic projection of the side surface on the substrate base plate and the orthographic projection of the active layer pattern on the substrate base plate are overlapped;

the dielectric layer is positioned between the active layer pattern and the light resistance pattern and is configured to enable the surface, facing the substrate, of the active layer to be parallel to the plane of the substrate;

the maximum thickness of the photoresist pattern is d1, the maximum thickness of the dielectric layer is d2, and d1 and d2 satisfy the following conditions: d1 < d 2.

2. The display substrate of claim 1, wherein the range of tilt angles comprises: 50 to 90 degrees.

3. The display substrate of claim 1, wherein the material of the dielectric layer comprises: an organic resin material;

the glass transition temperature of the organic resin material is greater than 250 ℃.

4. The display substrate of claim 3, wherein the organic resin material comprises: and (3) a polyimide.

5. The display substrate of claim 4, wherein the polyimide is cured in an amount ranging from: 10 to 20 percent.

6. The display substrate of claim 1, wherein the dielectric layer is disposed over the entire surface of the substrate and is transparent.

7. The display substrate of claim 1, wherein the dielectric layer has a coefficient of thermal expansion less than or equal to 20 ppm/K.

8. The display substrate of claim 1, wherein the maximum thickness d1 of the photoresist pattern satisfies:

the maximum thickness d2 of the dielectric layer satisfies the following conditions: d2 is less than or equal to 10 um.

9. The display substrate of claim 1, further comprising:

and the buffer layer is positioned between the dielectric layer and the active layer pattern, and the surface of one side, away from the substrate base plate, of the buffer layer is parallel to the plane of the substrate base plate.

10. The display substrate of any of claims 1-9, further comprising:

the grid insulating layer is positioned on one side of the active layer pattern, which is far away from the substrate;

the grid electrode is positioned on one side of the grid insulating layer, which is far away from the substrate base plate;

and the source and drain electrodes are positioned on one side of the active layer pattern, which is far away from the substrate base plate, and are connected with the active layer pattern.

11. A display panel, comprising: a display substrate according to any one of claims 1-10 and a counter substrate arranged opposite to the display substrate.

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