KR100635564B1 - Method fabricating of flat panel display - Google Patents

Abstract

The present invention relates to a method for manufacturing a flat panel display device, wherein a step is formed around an opening of a photoresist pattern to increase the retreat speed of the edge of the opening of the photoresist pattern during an etching process using the photoresist pattern as an etching mask. By forming a low taper, it is possible to improve step coverage in a subsequent process and thereby improve the reliability of the device.

Contact hole, via contact hole, photoresist pattern, low taper.

Description

Method of manufacturing flat panel display device {Method fabricating of flat panel display}

1 is a cross-sectional view of an organic light emitting display device according to the prior art.

2A and 2B are cross-sectional views illustrating a method for forming a contact hole according to the prior art.

3A and 3B are cross-sectional views illustrating a method for forming a contact hole according to another embodiment of the prior art.

4 is a cross-sectional view of an organic light emitting display device according to the present invention;

5A and 5B are cross-sectional views illustrating a method for forming a contact hole according to the present invention.

 <Description of the symbols for the main parts of the drawings>

100, 400: transparent insulation substrate 110, 410: buffer film

120, 420: polysilicon layer pattern 122, 422: source / drain regions

124 and 424 channel region 130 and 430 gate insulating film

132 and 432 gate electrodes 140 and 440 interlayer insulating film

150, 450: source electrode 152, 452: drain electrode

160, 460: protective film 170, 470: planarization film

180, 480: pixel electrodes 190, 490: pixel defining layer pattern

200, 300, 500: substrate 210, 310, 510: etched layer

220, 320, 520: photosensitive film pattern

230, 330, 530: contact hole or via contact hole

442: contact hole 472: via contact hole

The present invention relates to a method for manufacturing a flat panel display device, and more particularly, a method of manufacturing a flat panel display device, in which a step is formed in an opening of a photoresist pattern to control a retreat speed during an etching process to form a smooth etching surface of an etched layer. It is about.

In general, silicon thin film transistors are applied to large area integrated circuits such as flat panel display devices, image sensors, copiers, printers, and scanners.

The flat panel display device includes an LCD (Liquid Crystal Display) and an organic electroluminescent device. The organic electroluminescent device is a representative technology of a flat panel display device, and is mainly classified into two types, an active type and a passive type. In the active device, each pixel is controlled by an active device such as a thin film transistor, and thus, a screen having a high resolution is much superior to a passive display device in terms of speed, viewing angle, and contrast ratio.

The main reason for using silicon thin film transistors in organic electroluminescent devices is that they can be processed at a low temperature of 400 ° C or less, have excellent stability of device characteristics, and can be easily directly applied to large glass substrates.

1 is a cross-sectional view of an organic light emitting display device according to the prior art.

First, a buffer film 110 having a predetermined thickness is formed on the front surface of the transparent insulating substrate 100 by a plasma-enhanced chemical vapor deposition (PECVD) method. In this case, the buffer layer 110 prevents the diffusion of impurities in the transparent insulating substrate 100 during the crystallization process of the amorphous silicon layer formed in a subsequent process.

Next, an amorphous silicon layer (not shown) having a predetermined thickness is deposited on the buffer layer 110, and the amorphous silicon layer is formed using Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), or the like. Crystallization is performed using a metal induced lateral crystallization (MILC) method, and then patterned by a photolithography process to form a polysilicon pattern 120.

Next, a gate insulating film 130 having a predetermined thickness is formed on the entire surface. The gate insulating film 130 is formed of a silicon oxide film.

A metal film (not shown) used as the gate electrode material is formed on the gate insulating layer 130. In this case, the metal layer may be formed of a single layer of an aluminum alloy, such as aluminum (Al) or aluminum-neodymium (Al-Nd), or multiple layers in which an aluminum alloy is laminated on a chromium (Cr) or molybdenum (Mo) alloy. . Subsequently, the metal layer is etched by the photolithography process to form the gate electrode 132. Thereafter, an ion is implanted into the polysilicon pattern 120 at both lower sides of the gate electrode 132 to form a source / drain region 122. The channel / drain region 122 is a channel region 124.

Next, an interlayer insulating film 140 is formed on the entire surface. The interlayer insulating layer 140 may be formed of a silicon oxide film, a silicon nitride film, or a stacked structure thereof.

Next, the interlayer insulating layer 140 and the gate insulating layer 130 are etched by a photolithography process to form contact holes (not shown) that expose the source / drain regions 122.

Next, an electrode material is formed on the entire surface. In this case, as the electrode material, molybdenum tungsten (MoW) or aluminum-neodymium (Al-Nd) may be used.

Next, the electrode material is etched by the photovisual process to form source / drain electrodes 150 and 152 connected to the source / drain regions 122 through the contact hole.

Next, the passivation layer 160 is formed on the entire surface. In this case, the passivation layer 160 may be formed of a silicon oxide film or a silicon nitride film, may be formed of a laminated structure, or a silicon oxynitride film may be used.

Next, the passivation layer 160 is etched by a photolithography process to form a first via contact hole (not shown) exposing any one of the source / drain electrodes 150 and 152.

Next, a planarization layer 170 is formed on the entire surface including the first via contact hole.

Next, the planarization layer 170 is etched by a photolithography process to form a second via contact hole (not shown) that exposes one of the source / drain electrodes 150 and 152.

Thereafter, a conductive layer for pixel electrodes (not shown) is formed on the entire surface, and the conductive layer for pixel electrodes is etched by a photolithography process to pass the source / drain electrodes 150 and 152 through the second via contact hole. ) To form a pixel electrode 180 connected to either. The pixel electrode 180 is formed of a stacked structure of a reflective film and a transparent electrode or a single structure of a transparent electrode.

Although not shown, an organic layer including at least an emission layer is formed on the pixel electrode 180, and then an opposite electrode is formed on the entire surface. The counter electrode is formed of a transparent electrode or a reflective electrode.

2A and 2B are cross-sectional views illustrating a method for forming a contact hole according to the related art, and illustrate a process of etching the etched layer 210 formed on the substrate 200 using the photoresist pattern 220. The etched layer 210 may be an insulating film or a conductive layer. When the etched layer 210 is an insulating film, a pattern formed in the etched layer 210 may be a contact hole 230 or a via contact hole 230.

In the etching process, when the micro pattern of the highly integrated device is formed, the opening profile of the photoresist pattern 220 is vertically formed, and the etching layer 210 is etched using the photoresist pattern 220 as an etching mask. There is little variation in the size of the pattern, and the etching profile is vertically formed. This is because most of the retraction amount T-t of the photoresist pattern 220 is generated in the vertical direction during the etching process.

3A and 3B are cross-sectional views illustrating a method of forming a contact hole according to another exemplary embodiment of the prior art, in which the opening angle θ1 of the photosensitive film pattern 320 is decreased to increase the retreat speed at the edge of the opening. Thus, after the etching process, the inclination was formed on the etching surface of the etching layer 310. After the etching process, the thickness of the photoresist pattern 320 decreased to (T1-t1), but the decrease in the vertical direction and the horizontal direction is not significantly different.

The etching process is advantageous in a structure in which a low taper is required regardless of the size of the pattern, such as an organic light emitting display device.

As described above, the organic light emitting display device according to the related art has to form a contact hole or a via contact hole having a low taper etching profile in order to improve step coverage. There is difficulty. Compared to the photoresist pattern of FIG. 2A, the photoresist pattern of FIG. 3A is advantageous to control the etching surface of the layer to be etched. However, since the angle θ2 of the etching surface of the layer to be etched is large, step coverage cannot be improved. As a result, when step coverage defects occur, a phenomenon of disconnection or short circuit with other wires occurs, thereby degrading reliability of the device.

Accordingly, the present invention is to solve the problems of the prior art as described above, by forming a photoresist pattern having a multi-profile having a low step height of the opening to increase the retreat rate control of the photoresist pattern during the etching process of the contact hole or via contact hole An object of the present invention is to provide a method for manufacturing a flat panel display device which can improve step coverage by forming an etching surface gently.

In order to achieve the above object, the manufacturing method of the flat panel display device according to the present invention,

Forming an etched layer on the substrate having a predetermined substructure;

Forming a photoresist film on the etched layer;

Forming a photoresist pattern having a multi-profile having a step shape having a step difference at the opening side by a photo process;

Etching the layer to be etched using the photoresist pattern as an etch mask, and adjusting a retreat speed of the photoresist pattern to form a contact hole having a gentle slope;

Removing the photoresist pattern;

Forming a conductive layer pattern connected to the substrate through the contact hole;

The etched layer is formed using at least one thin film selected from the group consisting of a gate insulating film, an interlayer insulating film, a protective film, a planarization film, and a pixel defining film,

The etched layer is formed of at least one thin film selected from the group consisting of SiN _x film, SiON film and SiO ₂ .

The etching layer is formed of one material selected from the group consisting of polyimide, benzocyclobutene series resin, benzocyclobutene series resin, spin on glass and acrylate,

The photo process is performed by an exposure process using a halftone mask,

The edge of the photoresist pattern has an angle of 40 ° or less,

The step of the photosensitive film pattern is one having a step or more of the double step,

An edge of the photoresist pattern is faster than the upper side of the photoresist pattern having a high step,

The etching process is a dry etching process by a reactive ion etch (RIE) or inductive coupled plasma (ICP),

The dry etching process is performed by using a mixed gas using SF6 or CF4 gas as an etching gas and O2 gas as an additive gas,

The etching surface of the contact hole has an angle of 20 ° or less with the substrate surface,

The contact hole may be a via contact hole.

Hereinafter, a method of manufacturing a flat panel display device according to the present invention will be described with reference to the accompanying drawings.

4 is a cross-sectional view of an organic light emitting display device according to the present invention.

First, a buffer film 110 having a predetermined thickness is formed on the front surface of the transparent insulating substrate 400 by plasma-enhanced chemical vapor deposition (PECVD). In this case, the buffer layer 410 prevents the diffusion of impurities in the transparent insulating substrate 400 during the crystallization process of the amorphous silicon layer formed in a subsequent process.

Next, an amorphous silicon layer (not shown) having a predetermined thickness is deposited on the buffer layer 410, and the amorphous silicon layer is formed using Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), or the like. After crystallization by using a MILC (Metal Induced Lateral Crystallization) method, and then patterned by a photolithography process to form a polysilicon pattern 420.

Next, a gate insulating film 430 having a predetermined thickness is formed on the entire surface. The gate insulating film 430 is formed of a silicon oxide film.

A metal film (not shown) used as a gate electrode material is formed on the gate insulating film 430. In this case, the metal layer may be formed of a single layer of an aluminum alloy, such as aluminum (Al) or aluminum-neodymium (Al-Nd), or multiple layers in which an aluminum alloy is laminated on a chromium (Cr) or molybdenum (Mo) alloy. . Subsequently, the metal layer is etched by a photolithography process to form a gate electrode 432. Thereafter, an ion is implanted into the polysilicon pattern 420 at both lower sides of the gate electrode 432 to form a source / drain region 422. The channel / drain region 422 is a channel region 424.

Next, an interlayer insulating film 440 is formed on the entire surface. The interlayer insulating film 440 may be formed of a silicon oxide film, a silicon nitride film, or a stacked structure thereof.

Next, a first photosensitive film (not shown) is formed on the interlayer insulating film 440.

Exposure and development are carried out by a photographic process to form a first photoresist pattern (not shown) having an opening. In this case, the first photoresist pattern is formed in a photo process using a halftone mask to form a low step of the edge of the opening of the first photoresist pattern. In this case, the step of the first photoresist pattern may be formed of a double or more steps.

Next, the interlayer insulating layer 440 and the gate insulating layer 430 are etched using the first photoresist pattern as an etching mask to form a contact hole 442 exposing the source / drain regions 422. The etching process is a dry etching process using reactive ion etch (RIE) or inductive coupled plasma (ICP), and is performed using a mixed gas using SF6 or CF4 gas as an etching gas and O2 gas as an additive gas. do. In the etching process, it is preferable that the etching surface and the horizontal surface of the contact hole 442 have an angle of 20 ° or less by adjusting the retreat speed of the first photoresist pattern. Here, forming the etch surface and the horizontal surface of the contact hole 442 to have an angle of 20 ° or less to smoothly form the etch surface of the contact hole 442 to facilitate deposition of a thin film formed in a subsequent process. to be.

Next, an electrode material is formed on the entire surface. In this case, molybdenum tungsten (MoW) or aluminum-neodymium (Al-Nd) may be used as the electrode material.

Next, the electrode material is etched by the photovisual process to form source / drain electrodes 450 and 452 connected to the source / drain regions 422 through the contact hole 442.

Next, a protective film 460 is formed over the entire surface. In this case, the passivation layer 460 may be formed of a silicon oxide layer or a silicon nitride layer, which is an inorganic insulating layer, may be formed of a stacked structure, and a silicon oxynitride layer (SiON) may be used.

Next, a planarization layer 470 is formed on the passivation layer 460. The planarization layer 470 is an organic insulating layer and is a material selected from the group consisting of polyimide, benzocyclobutene series resin, spin on glass, and acrylate. Can be formed.

Thereafter, a second photoresist layer (not shown) is formed on the planarization layer 470.

Exposure and development are carried out in a photographic process to form a second photosensitive film pattern (not shown) having an opening. In this case, the second photoresist pattern is formed in a photo process using a halftone mask to form a low step of the edge of the opening of the second photoresist pattern. In this case, the step of the second photoresist layer pattern may be formed as a double or more step.

Next, the planarization layer 470 and the passivation layer 460 are etched using the second photoresist pattern as an etch mask to form a via contact hole 472 exposing the source / drain electrodes 450 and 452. . The etching process is a dry etching process using a reactive ion etch (RIE) or an inductive coupled plasma (ICP), and a mixed gas using SF ₆ or CF ₄ gas as an etching gas and O ₂ gas as an additive gas. It is carried out using. In the etching process, it is preferable that the etching surface and the horizontal surface of the via contact hole 472 are formed to have an angle of 20 ° or less by adjusting the retreat speed of the second photoresist pattern. Here, the etching surface and the horizontal surface of the via contact hole 472 may be formed to have an angle of 20 ° or less to smoothly form the etching surface of the via contact hole 472 to facilitate deposition of a thin film formed in a subsequent process. To do this. In particular, when the pixel electrode is formed in the subsequent process and the pixel defining layer 490 is formed, step coverage is improved on the via contact hole 472 to prevent the pixel electrode from shorting with the counter electrode. The via contact hole 472 may be formed by etching the passivation layer 460 and the planarization layer 470 using different etching masks.

Next, the second photoresist pattern is removed.

Thereafter, a conductive layer for pixel electrode (not shown) is formed on the entire surface, and the conductive layer for pixel electrode is etched by a photolithography process to pass through the source / drain electrode 450 through the via contact hole 472. The pixel electrode 480 connected to any one of 452 is formed. The pixel electrode 480 is formed of a stacked structure of a reflective film and a transparent electrode or a single structure of a transparent electrode.

Next, a pixel defining layer pattern 490 defining an emission region is formed on the entire surface. In the process of forming the pixel definition layer pattern 490, the method may be performed in the same manner as the etching process of the interlayer insulating layer 440 and the planarization layer 470. This favors the deposition of subsequent organic films.

Although not shown, an organic layer including at least an emission layer is formed on the pixel electrode 480, and then an opposite electrode is formed on the entire surface. The counter electrode is formed of a transparent electrode or a reflective electrode.

5A and 5B are cross-sectional views illustrating a method of forming a contact hole according to the present invention, and may be applied to the method of forming the contact hole and the via contact hole of FIG. 4.

Referring to FIG. 5A, an etched layer 510 is formed on the substrate 500, and a photoresist pattern 520 having an opening is formed on the etched layer 510. The photosensitive film pattern 520 is formed by an exposure and development process using a halftone mask, and a step is formed. In FIG. 5A, the photoresist pattern 520 is illustrated as having a double step, but may have a double or more step. A portion 'A', which is indicated by a dotted line in FIG. 5A, is an edge of the opening of the photoresist pattern 520 and forms an etched surface of a contact hole or a via contact hole 530 formed by etching the etched layer 510. In order to have an angle θ3 of 40 ° or less.

Referring to FIG. 5B, the etched layer 510 is etched using the photoresist pattern 520 as an etch mask to form a contact hole or a via contact hole 530. After the etching process, the thickness of the photoresist pattern 520 is reduced by (T2-t2). At this time, the retreat speed of the photoresist pattern 520 advances rapidly at a portion θ3 smaller than a portion having a large edge angle at a position lower than a high step. This is schematically illustrated in FIG. 5B by the arrow length to the retraction speed of the photoresist pattern 520. Here, it is advantageous for the step coverage to have an angle θ4 of which the etching surface of the contact hole or the via contact hole 530 forms a horizontal plane of 20 ° or less.

Therefore, the manufacturing method of the flat panel display device according to the present invention can easily adjust the etching profile of the etched layer by increasing the retreat speed at the opening edge of the photosensitive film pattern during the etching process by forming a low step of the opening edge of the photosensitive film pattern The etching profile may form a smooth contact hole or via contact hole. Therefore, the step coverage characteristic can be improved on the upper side of the contact hole or the via contact hole, thereby preventing the phenomenon such as short circuit or short circuit between the devices, thereby improving the reliability of the device.

Claims (11)

Forming an etched layer on the substrate having a predetermined substructure; Forming a photoresist film on the etched layer; Forming a photoresist pattern having a multi-profile having a step shape having a step difference at the opening side by a photo process; Etching the layer to be etched using the photoresist pattern as an etch mask, and adjusting a retreat speed of the photoresist pattern to form a contact hole having a gentle slope; Removing the photoresist pattern; And forming a conductive layer pattern connected to the substrate through the contact hole. The method of claim 1, And the etched layer is formed using at least one thin film selected from the group consisting of a gate insulating film, an interlayer insulating film, a protective film, a planarization film, and a pixel definition film. The method of claim 2, The etching layer is a method of manufacturing a flat panel display device, characterized in that formed of at least one thin film selected from the group consisting of SiN _x film, SiON film and SiO ₂ . The method of claim 1, The etched layer is formed of one material selected from the group consisting of polyimide, benzocyclobutene series resin, benzocyclobutene series resin, spin on glass, and acrylate. Method of manufacturing flat panel display device. The method of claim 1, And said photographic process is performed by an exposure process using a halftone mask. The method of claim 1, The edge of the photosensitive film pattern is a manufacturing method of a flat panel display element, characterized in that having an angle of 40 ° or less. The method of claim 1, A method of manufacturing a flat panel display device, characterized in that the receding speed of the edge of the photoresist pattern is higher than that of the photoresist pattern having a high step. The method of claim 1, The etching process is a method of manufacturing a flat panel display device characterized in that the dry etching process by a reactive ion etch (RIE) or inductive coupled plasma (ICP). The method of claim 8, The dry etching process is performed using a mixed gas using SF6 or CF4 gas as an etching gas and O2 gas as an additive gas. The method of claim 1, And the etching surface of the contact hole has an angle of 20 ° or less with the surface of the substrate. The method according to claim 1 or 10, And the contact hole is a via contact hole.

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