JPH0627492A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To prevent the remaining of etching of electrode patterns of trench type auxiliary capacitors and trench type thin-film transistors (TFTs). CONSTITUTION:This active matrix substrate 4 has pixel electrodes 1 arranged in a matrix form, the TFTs 2 connected to these pixel electrodes and the auxiliary capacitors 3 for holding charges via these TFTs 2. Each of the auxiliary capacitors 3 consists of a first polysilicon layer 6 formed along the inside wall of the trench 5 formed on the main surface of the substrate 4 and continuously up to the top of the main surface, a dielectric film 7 formed on this first polysilicon layer 6 and a second polysilicon layer 8 formed on this dielectric film 7. The region 16 of the first polysilicon layer 6 formed on the main surface has the area size including the aperture 17 of the trench 5. At least one sides 18 of the first polysilicon layer 6 formed in the base parts of the trenches 9 of the TFTs exist on the side inner than the base ends 19 of the trenches.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a structure of an active matrix substrate on which pixel electrodes, thin film transistors (TFTs), auxiliary capacitors and the like are formed. More specifically, it relates to a thin film transistor having a trench structure and an electrode shape of a storage capacitor.

[0002]

2. Description of the Related Art A conventional liquid crystal display device comprises a pair of substrates opposed to each other with a predetermined gap and a liquid crystal layer filled and sealed in the gap. Particularly, in an active matrix liquid crystal display device, pixel electrodes arranged in a matrix on the inner surface of one substrate, a thin film transistor (TFT) connected to the pixel electrode, and an auxiliary capacitance for holding an electric charge via the thin film transistor. And are formed. A substrate having such a structure is hereinafter referred to as an active matrix substrate. After the thin film transistor is selected and the image signal is written in the pixel electrode, the thin film transistor is not selected and the written image signal is held. An image is displayed by so-called sampling hold. The storage capacitor is connected in parallel with the pixel in order to suppress the attenuation of the image signal during the non-selection period.

The pixel electrode serves as an effective display area, and the thin film transistor and the storage capacitor constitute an ineffective display area. Along with the miniaturization and high definition of pixels, the ratio of the effective display area to the entire display area, that is, the aperture ratio is sacrificed, and the contrast is lowered. As measures against this, a thin film transistor having a trench structure and an auxiliary capacitor have been conventionally proposed, and disclosed in, for example, Japanese Patent Laid-Open No. 64-81262.

[0004]

FIG. 17 shows a conventional auxiliary capacitor trench structure. The auxiliary capacitance is provided by utilizing a groove or trench 101 formed by etching in the main surface of the active matrix substrate. A first electrode 102 having a continuous pattern shape is formed along the main surface of the substrate and the inner wall of the trench 101. The first electrode is made of, for example, a polysilicon thin film. Since the area utilization efficiency can be improved by using the substrate three-dimensionally in this way, there is an advantage that the size of the auxiliary capacitor can be miniaturized accordingly. The first electrode 102 is processed into a predetermined pattern shape by etching after depositing a polysilicon thin film on the entire surface of the substrate. Although not shown, an auxiliary capacitance can be formed by depositing a dielectric film and a second electrode on the first electrode 102.

Conventionally, there has been a problem or a problem that an unnecessary polysilicon thin film 103 remains on the bottom surface of the trench 101 even if the etching process is performed. Such an etching residue causes a variation in each auxiliary capacitance, resulting in variation. Etching is performed using, for example, a positive photoresist. After coating the photoresist on the polysilicon thin film, an exposure process is performed using a stepper to remove the exposed portion, and the resist is patterned.
Thereafter, the polysilicon thin film is selectively etched using the photoresist as a mask to form a pattern of the first electrode 102. However, the depth of the trench 101 is 1
Since the thickness is from 10 μm to 10 μm, the resist film thickness is increased only in the trench portion, and a sufficient exposure amount cannot be absorbed. Therefore, the resist on the bottom surface of the trench 101 and on the lower part of the side wall is not exposed, and the resist on this portion cannot be removed. Therefore, the etching residue of the polysilicon thin film is generated. Further, even when a one-to-one projection type exposure apparatus or a projection type exposure apparatus is used instead of the stepper, the amount of exposure to the bottom surface portion of the trench 101 is insufficient, and etching residue occurs.

FIG. 18 shows a trench structure of a conventional thin film transistor. In the illustrated example, two thin film transistors are provided in a common groove or trench 104 formed in the surface of the active matrix substrate. The polysilicon thin film 105A, which is the semiconductor region of one thin film transistor, is continuously formed in a predetermined pattern along the main surface of the substrate and the inner wall of the trench 104. Further, the polysilicon thin film 105B of the other transistor is similarly formed with a predetermined interval. Trench 104
On the other hand, a pair of thin film transistors can be formed by embedding a common gate electrode 106 after embedding a gate insulating film (not shown). As in the case of FIG. 17, an etching residue 107 of the polysilicon thin film is formed on the bottom surface of the trench 104. The etching residue 107 is not preferable because it causes capacitive coupling and parasitic capacitance of the thin film transistor.

[0007]

In view of the above-mentioned problems of the prior art, the present invention improves the pattern shape of a trench type thin film element to reduce variations in auxiliary capacitance and capacitive coupling or parasitic capacitance of thin film transistors. The purpose is to suppress. In order to achieve such an object, the means shown in FIG. 1 was taken. As shown in (A), the active matrix substrate according to the present invention has, as its basic components, pixel electrodes 1 arranged in a matrix, a thin film transistor (TFT) 2 connected to this pixel electrode, and this TFT 2.
And an auxiliary capacitor 3 for holding the electric charge via. A liquid crystal display device can be obtained by stacking the active matrix substrate 4 having such a configuration and the other substrate (not shown) having counter electrodes with a predetermined gap therebetween and holding a liquid crystal layer (not shown).

Each auxiliary capacitance 3 has a trench structure,
It is formed by utilizing the groove or trench 5 formed on the main surface of the substrate 4. The auxiliary capacitor 3 has a laminated structure and is formed continuously along the inner wall of the trench 5 and on the main surface of the substrate 4, for example, a first electrode layer such as a first polysilicon layer 6
And the dielectric film 7 formed on the first polysilicon layer 6.
And a second electrode layer formed on the dielectric film 7, for example, a second polysilicon layer 8.

On the other hand, the TFT 2 is also formed by utilizing the other trench 9. In the trench 9, a semiconductor region made of the above-mentioned first polysilicon layer 6 is formed. This semiconductor region is continuously formed in a predetermined pattern along the main surface of the substrate 4 and the inner wall of the trench 9. A gate insulating film 10 is deposited on the semiconductor region. This film 10 can be made of, for example, the same material as the dielectric film 7 described above. Further, a gate electrode made of the second polysilicon layer 8 is formed on the gate insulating film 10 so as to overlap with each other to form a trench type TFT 2. A metal wiring 12 made of aluminum or the like is electrically connected to the drain region D of the TFT 2 via a first interlayer insulating film, for example, a first PSG film 11. The above-mentioned pixel electrode 1 is electrically connected to the source region of the TFT 2 through the first PSG film 11. Further, the metal wiring 12 is covered with a second interlayer insulating film, for example, a second PSG film 13. Although both the auxiliary capacitance 3 and the TFT 2 have a trench structure in this example, the present invention is not limited to this, and at least one of them includes an active matrix substrate having a trench structure.

FIG. 1B schematically shows the first characteristic feature of the present invention. The first polysilicon layer 6 forming the storage capacitor 3 includes two pattern regions. That is, an inner pattern region 14 that completely covers the inner wall and bottom of the trench 5 and a surface pattern region 16 formed on the main surface 15 of the substrate. The surface pattern region 16 is continuous with the inner pattern region 14 and also surrounds the opening 17 of the trench 5. Preferably, the surface pattern region 16 extends from the end of the opening 17 toward the periphery by 0.5 μm or more. That is, the width of the surface pattern region 16 having a frame shape is 0.5 μm or more.

The second characteristic feature of the present invention is schematically shown in (C). The first polysilicon layer 6 having a predetermined patterning shape is formed so as to cross the trench 9 and the TFT 2 is formed.
Make up. The first polysilicon layer 6 has a strip pattern shape in plan view, and at least one side 18 of the pattern formed on the bottom surface of the trench 9 is located inside the bottom end portion 19 of the trench 9. To do. Similarly, at least one side 20 of the pattern of the first polysilicon layer 6 located on the main surface of the substrate is also inside the opening end 21 of the trench. Although the pattern shape shown in (C) is applied to the TFT 2 in this example, the present invention is not limited to this.
The pattern shape shown in (C) may be applied to the auxiliary capacitor 3 instead of the pattern shape shown in (B).

[0012]

As shown in FIG. 1B, according to the first feature of the present invention, the inner wall and bottom surface of the trench are completely covered with the first polysilicon layer and surround the trench opening. Similarly, the first polysilicon layer on the main surface of the substrate is patterned. In other words, in the structure shown in (B),
After depositing the first polysilicon layer on the entire surface of the substrate, only the portion on the main surface may be etched, and it is not necessary to etch the first polysilicon layer deposited on the bottom surface of the trench. Therefore, it is possible to suppress variations in the trench type auxiliary capacitance without the risk of etching residue as in the conventional case.

As shown in FIG. 1C, the second aspect of the present invention
According to the feature, the first polysilicon layer 6 is patterned in a strip shape when seen in a plan view, and at least one side 18 of the first polysilicon layer 6 is formed on the bottom surface of the trench 9.
And a constant space is provided between the inner wall end 19 of the trench 9. In other words, unlike the conventional method, the pattern shape has no etching residue and the trench type TFT
It is possible to suppress the capacitive coupling and parasitic capacitance of. The pattern shape shown in (C) can be applied to the auxiliary capacitance instead of the pattern shape shown in (B). In this case, since the surface area of the trench type auxiliary capacitance can be reduced, higher density integration can be achieved and the pixel aperture ratio can be improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a schematic plan view showing an embodiment of the trench type auxiliary capacitance according to the present invention. In this embodiment, ten trenches 31 are formed in stripes. A first polysilicon film 32 is patterned so as to cover all the trenches 31, and one end thereof is connected to a pad 33 for electrode extraction. The first polysilicon film 32 completely covers the inner wall and bottom of each trench 31, and the pattern region deposited on the main surface of the substrate has a width including an alignment margin of at least 0.5 μm. Each trench 31 is included. Since the patterning of the first polysilicon film 32 only needs to be performed by etching the surface region, the etching residue on the bottom surface of the trench 31 does not occur unlike the conventional case. Further, after the dielectric film is deposited, the second polysilicon film 34 is aligned with the trench 31 and patterned. One end of the second polysilicon film 34 is provided with another electrode extraction pad 3
Connected to 5. In this way, the pair of pads 3
An auxiliary capacitance is obtained between 3,35.

For comparison, FIG. 3 shows a planar structure of a conventional trench type auxiliary capacitance. The same components as those of the embodiment shown in FIG. 2 are designated by the same reference numerals to facilitate understanding. In the conventional example shown in FIG. 3, the first polysilicon film 32
The pattern width on the main surface of the substrate is
Is set to be shorter than the total length, and both end sides of the bottom surface of the trench 31 are exposed when viewed two-dimensionally. An etching residue 36 of the first polysilicon film 32 is generated in this portion, which causes variation in the auxiliary capacitance.

FIG. 4 is a schematic perspective view of the trench type auxiliary capacitance shown in FIG. 2, in which the longitudinal dimension of the trench is compressed and shown for ease of illustration. The value of the auxiliary capacitance is calculated with reference to this figure. The trench 31 has a width W, for example.
Is 1 μm, length L is 100 μm, and height H is 3 μ
Each is set to m. A margin M of 0.5 μm is set for the plane pattern size of the first polysilicon film 32 formed on the main surface 37 of the substrate. The margin M needs to be at least 0.5 μm and is appropriately determined in consideration of the alignment accuracy of the exposure apparatus and the over-etching amount of the first polysilicon film 32.

In the embodiment shown in FIG. 4, the side surface portion, the end surface portion and the bottom surface portion of the trench 31 are all covered with the first polysilicon film 32, and the total thereof becomes the electrode area. The area of the pair of side and bottom parts is 100 μm × (3 μm + 1 μ
m + 3μm) = 700μm ^2, and the area of the pair of end surface portions 1μm × 3μm × ² = 6μm 2, and the total area is calculated as 706μm ^2. In this embodiment, the trench 31
Since 10 electrodes are formed in parallel, the total electrode area is 706
[mu] m ² × 10 pieces = 7060μm ² becomes always the value of the design value is obtained. Further, a dielectric film (not shown) is a SiO ₂ film having a film thickness of 40 nm and a Si film having a film thickness of 15 nm.
With a double layer structure of N film, the unit capacity is 7.38 × 10 ⁻⁸
It becomes F / cm ² . Therefore, the value of the trench type auxiliary capacitance shown in FIG. 4 is 7060 × 10 ⁻⁸ × 7.38 × 10 ⁻⁸ = 5.
The value is 2102 pF, which is a value as designed.

On the other hand, for comparison, the value of the conventional trench type auxiliary capacitance is calculated with reference to FIG. The structure shown in FIG. 5 is a schematic perspective view of the conventional example shown in FIG. The width dimension W and the height dimension H of the trench 31 are the same as those in the embodiment shown in FIG. 4, but the length dimension is added with the original design value L and the dimension E of both end portions of the etching residue 36. To be The electrode area is calculated assuming that this dimension E is, for example, 10 μm. 720 .mu.m ² plus electrode area 20 [mu] m ² of the original electrode area 700 .mu.m ² and etching residue 36
Is the electrode area of each trench. Therefore, the value of the auxiliary capacitance including 10 trenches is 7200 × 10 ⁻⁸ × 7.
It is given by 38 × 10 ⁻⁸ = 5.316 pF. A deviation of about 2% occurs with respect to the original design value of 5.2102 pF. This error increases as the longitudinal dimension E of the etching residue 36 increases. On the other hand, in the present invention, since the etching residue does not occur on the bottom surface of the trench, it is possible to stably secure the auxiliary capacitance substantially equal to the design value. By suppressing the variation in the auxiliary capacitance, the voltage holding ability of each pixel becomes uniform, and, for example, bright spot defects on the display screen are reduced.

FIG. 6 is a schematic perspective view showing the structure of a trench type TFT according to the present invention. A first polysilicon film 42, which is patterned in a strip shape, is formed so as to intersect with the width direction of the trench 41. At the bottom of the trench 41, the patterned side of the first polysilicon film 42 is spaced inward from the bottom end 50, and the etching residue is completely removed. The gate insulating film 43 is patterned so as to be aligned with the first polysilicon film 42 which is patterned in a strip shape. This gate insulating film 43
Has a three-layer structure of, for example, SiO ₂ / SiN / SiO ₂ , and has improved gate breakdown voltage. Furthermore, the trench 41
The second polysilicon film 44 is patterned so as to be aligned with the longitudinal direction of the gate electrodes to form the gate electrode wiring.
Since the trench pattern and the gate wiring pattern match, the manufacturing process can be simplified. In addition, a source contact hole 45 and a drain contact hole 46 for electrode connection are formed on the surface of the first polysilicon film 42 separately on both sides of the gate electrode wiring.

FIG. 7 shows the first polysilicon film 4 shown in FIG.
It is explanatory drawing which shows the patterning method of 2. First, a first polysilicon film (not shown) is deposited on the entire inner wall and bottom of the trench 41. Next, a positive photoresist 47 is coated. Subsequently, a projection type exposure apparatus is used to irradiate the photoresist 47 through the photomask 48 to remove the photosensitive portion and form a stripe-shaped resist pattern. The strip-shaped first polysilicon film 42 is obtained by performing etching through this resist pattern. In particular, by partially notching a region of the mask pattern 49 formed on the photomask 48, which is aligned with the trench 41 and exposing the bottom surface portion sufficiently, the etching residue can be completely suppressed. It should be noted that it is possible to eliminate the insufficient exposure of the bottom surface of the trench by optimizing the exposure conditions without providing a notch in the mask pattern 49. For example, in the case of using a projection type exposure apparatus, by extending the exposure time of about 10 seconds in the past to about 25 to 30 seconds, it is possible to sufficiently expose the bottom surface of the trench having a depth of about 3 μm. I can do it.

FIG. 8 is a schematic perspective view showing another embodiment of the trench type auxiliary capacitance according to the present invention. Basically, the structure is similar to that shown in FIG. 1B, but the area occupied by the trench capacitance is reduced by reducing the surface pattern region area of the first polysilicon film 51. The aperture ratio is being improved. As shown in the drawing, one side 52 of the surface pattern region is set at a position that does not extend outside the opening end 54 of the trench 53. In the illustrated example, one side 52 of the surface pattern region is located inside the trench opening end portion 54, but it may be maximally aligned. The patterning process of such a shape can be easily performed by, for example, the method shown in FIG. Also on the bottom surface of the trench 53, the one side portion 55 of the first polysilicon film 51 is located inside the end surface 56 of the bottom surface of the trench, and no etching residue is generated as in the conventional case.

The surface occupation area of the trench type auxiliary capacitance shown in FIG. 8 will be calculated with reference to FIG. As shown in (A),
In this example, it is assumed that one side 52 of the surface pattern region of the first polysilicon film is aligned with the trench opening end portion 54. By doing so, the first polysilicon film can be entirely deposited on the four side surfaces and the bottom surface of the trench. The area of the trench opening is represented by A × B. On the other hand, the surface pattern area size of the first polysilicon film is represented by C × D.

For comparison, FIG. 9B shows the surface occupied area of the trench type capacitor shown in FIG. 1B. When the area A × B of the trench opening is set to be the same, the same auxiliary capacitance value can be obtained. Further, since the surface pattern region of the first polysilicon film surrounds the entire trench opening, its area is D × E.
, The occupied area is increased as compared with the embodiment shown in FIG. 9A, which is disadvantageous from the viewpoint of improving the aperture ratio.

Finally, a method of manufacturing the active matrix substrate shown in FIG. 1 will be described with reference to FIGS. First, FIG. 10 shows a process up to the patterning of the first polysilicon film. In step A, a substrate 61 made of quartz glass or the like is prepared. Next, in step B, the main surface of the substrate 61 is etched to form trenches 62 and 63. One trench 62 is for a TFT and the other trench 63 is for a storage capacitor. This etching is
For example, wet etching is performed using a mixed solution of HF: NH ₄ F = 1: 6. Substrate 61 in step C
A first polysilicon film 64 is deposited over the entire main surface of. By this treatment, the inner walls and bottoms of the trenches 62 and 63 are completely covered. The first polysilicon film 64 is deposited by using, for example, the LPCVD method to have a film thickness of 80 nm. Then, silicon or the like is ion-implanted and annealing for solid phase growth is added. Then, in step D, the patterning of the first polysilicon film 64 is performed. For the trench 62 where the TFT is formed, for example, a first polysilicon film having a pattern as shown in FIG. 1C is formed, and for the auxiliary capacitance trench 63, for example, as shown in FIG. A first polysilicon film having a pattern as shown in B) is formed. Instead of this, a first polysilicon film region having a pattern as shown in FIG. 8 may be formed. In any case, unlike the conventional case, there is no fear that etching residue will occur on the bottom surface of the trench.

Next, the film forming process of the insulating film will be described with reference to FIG. First, in step E, the first polysilicon film 64
The surface of the film is thermally oxidized to form a 10 nm SiO ₂ insulating film 65. The insulating film 65 formed in this manner forms the trench 62.
It becomes a gate insulating film inside and a dielectric film inside the other trench 63. Next, in step F, with one of the trenches 62 masked by the resist 66, ions of arsenic or the like are implanted into the trenches 63 to reduce the resistance of the first polysilicon film 64. The low resistance first polysilicon film 64 is used as the first electrode of the auxiliary capacitance. Subsequently, in step G, a SiO ₂ insulating film is further formed to a thickness of 60 nm by the HTO method.

The process up to the second polysilicon film patterning process will be described with reference to FIG. In step H, a second polysilicon film 67 is deposited on the entire main surface of the substrate 61 to completely fill the trenches 62 and 63. The second polysilicon film 67 is formed by LPCVD to have a film thickness of 350 nm, for example. After that, PSG or the like is covered to reduce the resistance of the second polysilicon film 67, and then PSG is removed. Next, in Step I, the second polysilicon film is patterned to form the gate electrode 68 in the trench 62 and the second electrode 69 of the auxiliary capacitance in the other trench 63. The patterning of the second polysilicon film is performed by using, for example, CF ₄
Plasma etching is performed using a mixed gas of / O ₂ = 95/5.

The impurity ion implantation process will be described with reference to FIG. In step J, the upper portion of the trench 62 is covered with a resist 70, and arsenic is ion-implanted at a relatively low concentration to form a so-called LDD region. Next, in step K, the upper portion of the trench 62 is covered with a resist 71 having a larger area, and then arsenic ions are ion-implanted at a relatively high concentration.
The source / drain regions of the channel TFT are formed. Subsequently, in step L, the trench 62 in which the N-channel transistor is formed and the trench 6 in which the auxiliary capacitance is formed
Boron is ion-implanted in a state where 3 is covered with a resist 72 to form a P-channel TFT (not shown).

The patterning process for the first PSG film will be described with reference to FIG. First, in step M, the first PSG film 73 is deposited on the entire surface of the substrate 61 by the LPCVD method. Subsequently, in step N, the first PSG film 73 is etched to form a first contact hole 75 communicating with the drain region D of the N-channel TFT 74 formed in the trench 62. The patterning of the first PSG film 73 is performed by wet etching using, for example, a mixed solution of HF / NH ₄ F.

The metal wiring process will be described with reference to FIG. In step O, a metal film 76 made of Al / Si is deposited on the surface of the substrate 61 by sputtering to have a film thickness of 600 nm. At this time, the first contact hole 75 is formed on the metal film 7.
6 is completely filled with the drain region D of the TFT 74.
Is conducted to. Next, in step P, the metal film is patterned to form the metal wiring 77. This patterning is performed by wet etching using, for example, a phosphoric acid aqueous solution of H ₃ PO ₄ / H ₂ O = 2/10. In step Q, the second PSG is formed on the surface of the substrate 61 by the LPCVD method or the like.
Coat the membrane 78. Thereafter, if desired, a nitride film or the like may be temporarily deposited and the first polysilicon film 64 may be hydrogenated.

Finally, the pixel electrode patterning process will be described with reference to FIG. In step R, the insulating film 65 and the first PSG film 7 are formed by dry etching or wet etching.
2. A second contact hole 79 communicating with the source region S of the TFT 74 is opened in the stack of the second PSG film 78. Next, in step S, the ITO film 80 is formed on the surface of the substrate 61.
Deposit. At this time, the second contact hole 79 is completely filled, and the source region S is electrically connected. The film thickness of the ITO film 80 is set to 140 nm, for example, and the film forming temperature is set to 400 ° C. Finally, in step T, the ITO film is patterned into a predetermined shape and the pixel electrode 81 is formed.
Is obtained. The TFT substrate 82 formed in this manner and the counter substrate 84 on which the counter electrode 83 is formed are bonded together,
An active matrix type liquid crystal display device can be obtained by filling and sealing the liquid crystal layer 85 in the gap between the two.

[0031]

As described above, according to the present invention, the auxiliary capacitor formed on the active matrix substrate is continuously formed along the inner wall of the trench and on the substrate surface. Layer, a dielectric film formed on the first electrode layer, and a second electrode layer formed on the dielectric film, and a first electrode formed on the substrate surface. The region of the layer has an area dimension that encompasses the opening of the trench. According to this configuration, it is not necessary to perform patterning on the first electrode layer deposited on the bottom surface of the trench, and etching residue does not occur. According to another aspect of the present invention, at least one of the auxiliary capacitor and the thin film transistor formed on the active matrix substrate has a first electrode layer formed continuously along the trench and on the substrate surface, An insulating film formed on the first electrode layer and a second electrode layer formed on the insulating film, and at least one of the first electrode layers formed on the bottom surface of the trench. It has a pattern shape in which the side is located inside the bottom end of the trench. Therefore, the etching residue on the bottom surface of the trench is removed. Thus, by removing the etching residue of the first electrode from the bottom surface of the trench, there is an effect that the cause of fluctuation of the trench type auxiliary capacitance is removed and an image display without uneven brightness can be obtained. Further, since parasitic capacitance or capacitive coupling of the trench type thin film transistor can be suppressed, there is an effect that a stable image display can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic configuration of an active matrix substrate according to the present invention.

FIG. 2 is a plan view showing an example of a trench type auxiliary capacitance according to the present invention.

FIG. 3 is a plan view showing an example of a conventional trench type auxiliary capacitance.

FIG. 4 is a schematic perspective view of the trench type auxiliary capacitance shown in FIG.

5 is a schematic perspective view of the conventional trench type auxiliary capacitance shown in FIG.

FIG. 6 is a schematic perspective view showing an example of a trench type thin film transistor according to the present invention.

7 is an explanatory diagram showing a patterning method of the trench type thin film transistor shown in FIG.

FIG. 8 is a perspective view showing another example of the trench type auxiliary capacitance according to the present invention.

9 is a schematic plan view for calculating an occupied area of the trench type auxiliary capacitance shown in FIG.

FIG. 10 is a process drawing showing the manufacturing method of the active matrix substrate shown in FIG.

FIG. 11 is a process drawing showing the same manufacturing method.

FIG. 12 is a process drawing showing the same manufacturing method.

FIG. 13 is a process drawing showing the same manufacturing method.

FIG. 14 is a process drawing showing the same manufacturing method.

FIG. 15 is a process drawing showing the same manufacturing method.

FIG. 16 is a process drawing showing the same manufacturing method.

FIG. 17 is a perspective view of a conventional trench type auxiliary capacitance.

FIG. 18 is a perspective view showing an example of a conventional trench type thin film transistor.

[Explanation of symbols]

 1 Pixel Electrode 2 Thin Film Transistor (TFT) 3 Auxiliary Capacitance 4 Active Matrix Substrate 5 Trench 6 First Polysilicon Layer 7 Dielectric Film 8 Second Polysilicon Layer 9 Trench 10 Gate Insulation Film

Claims (7)

[Claims] 1. An active matrix substrate comprising: pixel electrodes arranged in a matrix on an insulating substrate; a thin film transistor connected to the pixel electrode; and an auxiliary capacitor for holding an electric charge via the thin film transistor. A first electrode layer in which an auxiliary capacitance is formed continuously along the inner wall of the groove formed in the main surface of the insulating substrate and up to the main surface, and a dielectric formed on the first electrode layer. A region of the first electrode layer formed on the main surface and having a film and a second electrode layer formed on the dielectric film, and having an area dimension including the opening of the groove. An active matrix substrate that is characterized. 2. The active matrix substrate according to claim 1, wherein the opening of the groove is arranged 0.5 μm or more inside the region of the first electrode layer. 3. One substrate having pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors, and a counter electrode. A liquid crystal display device comprising the other substrate arranged to face the one substrate and a liquid crystal layer held between the two substrates, wherein the auxiliary capacitance is a groove formed on a main surface of the one substrate. A first electrode layer continuously formed along the inner wall of the substrate and up to the main surface, a dielectric film formed on the first electrode layer, and a second electrode formed on the dielectric film And a region of the first electrode layer formed on the main surface, the liquid crystal display device having an area dimension including the opening of the groove. 4. A semiconductor formed of the same material as that of the first electrode layer, wherein the thin film transistor is formed at the same time as the groove along an inner wall of another groove formed on the main surface of one substrate. 4. A layer, a gate electrode formed of the same material as the second electrode layer, and a gate insulating film sandwiched between the gate electrode and the semiconductor layer. Liquid crystal display device. 5. An active matrix substrate comprising pixel electrodes arranged in a matrix on an insulating substrate, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors, At least one of the auxiliary capacitor and the thin film transistor, a first electrode layer formed continuously along the inner wall of the groove formed on the main surface of the insulating substrate and up to the main surface, and on the first electrode layer And an insulating film formed on the insulating film and a second electrode layer formed on the insulating film,
An active matrix substrate, wherein at least one side of the first electrode layer formed on the bottom surface of the groove is inside the bottom end of the groove. 6. The active matrix according to claim 5, wherein at least one side of the first electrode layer formed on the main surface of the insulating substrate does not extend outside the opening end of the groove. substrate. 7. One substrate having pixel electrodes arranged in a matrix, thin film transistors connected to the pixel electrodes, and auxiliary capacitors for holding charges via the thin film transistors, and a counter electrode. In a liquid crystal display device comprising the other substrate arranged to face the one substrate and a liquid crystal layer held between the two substrates, at least one of the auxiliary capacitor and the thin film transistor is provided on the main surface of the insulating substrate. A first electrode layer continuously formed along the inner wall of the formed groove and up to the main surface, an insulating film formed on the first electrode layer, and an insulating film formed on the insulating film Consisting of a second electrode layer,
A liquid crystal display device, wherein at least one side of the first electrode layer formed on the bottom surface of the groove is inside the bottom end of the groove.